| Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #include <asm.h> |
| 24 | |
| 25 | .text |
| 26 | |
| 27 | /* void arch_enable_ints(void); */ |
| 28 | FUNCTION(arch_enable_ints) |
| 29 | mrs r0, cpsr |
| 30 | bic r0, r0, #(1<<7) /* clear the I bit */ |
| 31 | msr cpsr_c, r0 |
| 32 | bx lr |
| 33 | |
| 34 | /* void arch_disable_ints(void); */ |
| 35 | FUNCTION(arch_disable_ints) |
| 36 | mrs r0, cpsr |
| 37 | orr r0, r0, #(1<<7) |
| 38 | msr cpsr_c, r0 |
| 39 | bx lr |
| 40 | |
| 41 | /* int atomic_swap(int *ptr, int val); */ |
| 42 | FUNCTION(atomic_swap) |
| 43 | swp r0, r2, [r1] |
| 44 | bx lr |
| 45 | |
| 46 | /* int atomic_add(int *ptr, int val); */ |
| 47 | FUNCTION(atomic_add) |
| 48 | /* disable interrupts, do the add, and reenable */ |
| 49 | mrs r2, cpsr |
| 50 | mov r12, r2 |
| 51 | orr r2, r2, #(3<<6) |
| 52 | msr cpsr_c, r2 |
| 53 | |
| 54 | /* ints disabled, old cpsr state in r12 */ |
| 55 | |
| 56 | /* do the add, leave the previous value in r0 */ |
| 57 | mov r3, r0 |
| 58 | ldr r0, [r3] |
| 59 | add r2, r0, r1 |
| 60 | str r2, [r3] |
| 61 | |
| 62 | /* restore interrupts and exit */ |
| 63 | msr cpsr_c, r12 |
| 64 | bx lr |
| 65 | |
| 66 | /* int atomic_and(int *ptr, int val); */ |
| 67 | FUNCTION(atomic_and) |
| 68 | /* disable interrupts, do the and, and reenable */ |
| 69 | mrs r2, cpsr |
| 70 | mov r12, r2 |
| 71 | orr r2, r2, #(3<<6) |
| 72 | msr cpsr_c, r2 |
| 73 | |
| 74 | /* ints disabled, old cpsr state in r12 */ |
| 75 | |
| 76 | /* do the and, leave the previous value in r0 */ |
| 77 | mov r3, r0 |
| 78 | ldr r0, [r3] |
| 79 | and r2, r0, r1 |
| 80 | str r2, [r3] |
| 81 | |
| 82 | /* restore interrupts and exit */ |
| 83 | msr cpsr_c, r12 |
| 84 | bx lr |
| 85 | |
| 86 | /* int atomic_or(int *ptr, int val); */ |
| 87 | FUNCTION(atomic_or) |
| 88 | /* disable interrupts, do the or, and reenable */ |
| 89 | mrs r2, cpsr |
| 90 | mov r12, r2 |
| 91 | orr r2, r2, #(3<<6) |
| 92 | msr cpsr_c, r2 |
| 93 | |
| 94 | /* ints disabled, old cpsr state in r12 */ |
| 95 | |
| 96 | /* do the or, leave the previous value in r0 */ |
| 97 | mov r3, r0 |
| 98 | ldr r0, [r3] |
| 99 | orr r2, r0, r1 |
| 100 | str r2, [r3] |
| 101 | |
| 102 | /* restore interrupts and exit */ |
| 103 | msr cpsr_c, r12 |
| 104 | bx lr |
| 105 | |
| 106 | /* void arch_idle(); */ |
| 107 | FUNCTION(arch_idle) |
| 108 | #if ARM_CPU_CORTEX_A8 |
| 109 | .word 0xe320f003 /* wfi */ |
| 110 | #elif ARM_CPU_ARM1136 || ARM_CPU_ARM926 |
| 111 | mov r0, #0 |
| 112 | mcr p15, 0, r0, c7, c0, #4 |
| 113 | #elif ARM_CPU_ARM7 |
| 114 | /* nothing to do here */ |
| 115 | #else |
| 116 | #error unknown cpu |
| 117 | #endif |
| 118 | bx lr |
| 119 | |
| 120 | /* uint32_t arm_read_cr1(void) */ |
| 121 | FUNCTION(arm_read_cr1) |
| 122 | mrc p15, 0, r0, c1, c0, 0 |
| 123 | bx lr |
| 124 | |
| 125 | /* void arm_write_cr1(uint32_t val) */ |
| 126 | FUNCTION(arm_write_cr1) |
| 127 | mcr p15, 0, r0, c1, c0, 0 |
| 128 | bx lr |
| 129 | |
| 130 | /* uint32_t arm_read_cr1_aux(void) */ |
| 131 | FUNCTION(arm_read_cr1_aux) |
| 132 | mrc p15, 0, r0, c1, c0, 1 |
| 133 | bx lr |
| 134 | |
| 135 | /* void arm_write_cr1_aux(uint32_t val) */ |
| 136 | FUNCTION(arm_write_cr1_aux) |
| 137 | mcr p15, 0, r0, c1, c0, 1 |
| 138 | bx lr |
| 139 | |
| 140 | /* void arm_write_ttbr(uint32_t val) */ |
| 141 | FUNCTION(arm_write_ttbr) |
| 142 | mcr p15, 0, r0, c2, c0, 0 |
| 143 | bx lr |
| 144 | |
| 145 | /* void arm_write_dacr(uint32_t val) */ |
| 146 | FUNCTION(arm_write_dacr) |
| 147 | mcr p15, 0, r0, c3, c0, 0 |
| 148 | bx lr |
| 149 | |
| 150 | /* void arm_invalidate_tlb(void) */ |
| 151 | FUNCTION(arm_invalidate_tlb) |
| 152 | mov r0, #0 |
| 153 | mcr p15, 0, r0, c8, c7, 0 |
| 154 | bx lr |
| 155 | |
| 156 | /* void arch_switch_stacks_and_call(addr_t call, addr_t stack) */ |
| 157 | FUNCTION(arch_switch_stacks_and_call) |
| 158 | mov sp, r1 |
| 159 | bx r0 |