Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <platform/iomap.h> |
| 31 | #include <reg.h> |
| 32 | #include <target.h> |
| 33 | #include <platform.h> |
| 34 | #include <uart_dm.h> |
| 35 | #include <mmc.h> |
| 36 | #include <platform/gpio.h> |
| 37 | #include <dev/keys.h> |
| 38 | #include <spmi_v2.h> |
| 39 | #include <pm8x41.h> |
| 40 | #include <board.h> |
| 41 | #include <baseband.h> |
| 42 | #include <hsusb.h> |
| 43 | #include <scm.h> |
| 44 | #include <platform/gpio.h> |
| 45 | #include <platform/gpio.h> |
| 46 | #include <platform/irqs.h> |
| 47 | #include <platform/clock.h> |
| 48 | #include <crypto5_wrapper.h> |
| 49 | #include <partition_parser.h> |
| 50 | #include <stdlib.h> |
| 51 | |
| 52 | #if LONG_PRESS_POWER_ON |
| 53 | #include <shutdown_detect.h> |
| 54 | #endif |
| 55 | |
| 56 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 57 | #define PMIC_ARB_OWNER_ID 0 |
| 58 | #define TLMM_VOL_UP_BTN_GPIO 85 |
| 59 | |
| 60 | #define FASTBOOT_MODE 0x77665500 |
| 61 | #define PON_SOFT_RB_SPARE 0x88F |
| 62 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 63 | struct mmc_device *dev; |
| 64 | |
| 65 | static uint32_t mmc_pwrctl_base[] = |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 66 | { MSM_SDC1_BASE, MSM_SDC2_BASE }; |
| 67 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 68 | static uint32_t mmc_sdhci_base[] = |
| 69 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE }; |
| 70 | |
| 71 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 72 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ }; |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 73 | |
| 74 | void target_early_init(void) |
| 75 | { |
| 76 | #if WITH_DEBUG_UART |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 77 | uart_dm_init(2, 0, BLSP1_UART1_BASE); |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 78 | #endif |
| 79 | } |
| 80 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 81 | static void set_sdc_power_ctrl() |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 82 | { |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 83 | /* Drive strength configs for sdc pins */ |
| 84 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 85 | { |
| 86 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0}, |
| 87 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0}, |
| 88 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK , 0}, |
| 89 | }; |
| 90 | |
| 91 | /* Pull configs for sdc pins */ |
| 92 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 93 | { |
| 94 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0}, |
| 95 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0}, |
| 96 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0}, |
| 97 | }; |
| 98 | |
| 99 | /* Set the drive strength & pull control values */ |
| 100 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 101 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
| 102 | } |
| 103 | |
| 104 | void target_sdc_init() |
| 105 | { |
| 106 | struct mmc_config_data config; |
| 107 | |
| 108 | /* Set drive strength & pull ctrl values */ |
| 109 | set_sdc_power_ctrl(); |
| 110 | |
| 111 | /* Try slot 1*/ |
| 112 | config.slot = 1; |
| 113 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 114 | config.max_clk_rate = MMC_CLK_177MHZ; |
| 115 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 116 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 117 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 118 | config.hs400_support = 1; |
| 119 | |
| 120 | if (!(dev = mmc_init(&config))) { |
| 121 | /* Try slot 2 */ |
| 122 | config.slot = 2; |
| 123 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 124 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 125 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 126 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 127 | config.hs400_support = 0; |
| 128 | |
| 129 | if (!(dev = mmc_init(&config))) { |
| 130 | dprintf(CRITICAL, "mmc init failed!"); |
| 131 | ASSERT(0); |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | void *target_mmc_device() |
| 137 | { |
| 138 | return (void *) dev; |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /* Return 1 if vol_up pressed */ |
| 142 | static int target_volume_up() |
| 143 | { |
| 144 | uint8_t status = 0; |
| 145 | |
| 146 | gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE); |
| 147 | |
| 148 | /* Wait for the gpio config to take effect - debounce time */ |
| 149 | thread_sleep(10); |
| 150 | |
| 151 | /* Get status of GPIO */ |
| 152 | status = gpio_status(TLMM_VOL_UP_BTN_GPIO); |
| 153 | |
| 154 | /* Active high signal. */ |
| 155 | return status; |
| 156 | } |
| 157 | |
| 158 | /* Return 1 if vol_down pressed */ |
| 159 | uint32_t target_volume_down() |
| 160 | { |
| 161 | /* Volume down button tied in with PMIC RESIN. */ |
| 162 | return pm8x41_resin_status(); |
| 163 | } |
| 164 | |
| 165 | static void target_keystatus() |
| 166 | { |
| 167 | keys_init(); |
| 168 | |
| 169 | if(target_volume_down()) |
| 170 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 171 | |
| 172 | if(target_volume_up()) |
| 173 | keys_post_event(KEY_VOLUMEUP, 1); |
| 174 | } |
| 175 | |
| 176 | /* Configure PMIC and Drop PS_HOLD for shutdown */ |
| 177 | void shutdown_device() |
| 178 | { |
| 179 | dprintf(CRITICAL, "Going down for shutdown.\n"); |
| 180 | |
| 181 | /* Configure PMIC for shutdown */ |
| 182 | pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN); |
| 183 | |
| 184 | /* Drop PS_HOLD for MSM */ |
| 185 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 186 | |
| 187 | mdelay(5000); |
| 188 | |
| 189 | dprintf(CRITICAL, "shutdown failed\n"); |
| 190 | |
| 191 | ASSERT(0); |
| 192 | } |
| 193 | |
| 194 | |
| 195 | void target_init(void) |
| 196 | { |
| 197 | uint32_t base_addr; |
| 198 | uint8_t slot; |
| 199 | |
| 200 | dprintf(INFO, "target_init()\n"); |
| 201 | |
| 202 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 203 | |
| 204 | target_keystatus(); |
| 205 | |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 206 | target_sdc_init(); |
| 207 | if (partition_read_table()) |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 208 | { |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 209 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 210 | ASSERT(0); |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 211 | } |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 212 | |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 213 | #if LONG_PRESS_POWER_ON |
| 214 | shutdown_detect(); |
| 215 | #endif |
| 216 | } |
| 217 | |
| 218 | void target_serialno(unsigned char *buf) |
| 219 | { |
| 220 | uint32_t serialno; |
| 221 | if (target_is_emmc_boot()) { |
| 222 | serialno = mmc_get_psn(); |
| 223 | snprintf((char *)buf, 13, "%x", serialno); |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | unsigned board_machtype(void) |
| 228 | { |
Aparna Mallavarapu | e9bdacd | 2015-03-15 14:24:21 +0530 | [diff] [blame] | 229 | return LINUX_MACHTYPE_UNKNOWN; |
| 230 | } |
| 231 | |
| 232 | /* Detect the target type */ |
| 233 | void target_detect(struct board_data *board) |
| 234 | { |
| 235 | /* This is already filled as part of board.c */ |
| 236 | } |
| 237 | |
| 238 | /* Detect the modem type */ |
| 239 | void target_baseband_detect(struct board_data *board) |
| 240 | { |
| 241 | uint32_t platform; |
| 242 | |
| 243 | platform = board->platform; |
| 244 | |
| 245 | switch(platform) { |
| 246 | case MSM8952: |
| 247 | case MSM8956: |
| 248 | case MSM8976: |
| 249 | board->baseband = BASEBAND_MSM; |
| 250 | break; |
| 251 | default: |
| 252 | dprintf(CRITICAL, "Platform type: %u is not supported\n",platform); |
| 253 | ASSERT(0); |
| 254 | }; |
| 255 | } |
| 256 | |
| 257 | unsigned target_baseband() |
| 258 | { |
| 259 | return board_baseband(); |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | unsigned check_reboot_mode(void) |
| 263 | { |
| 264 | uint32_t restart_reason = 0; |
| 265 | |
| 266 | /* Read reboot reason and scrub it */ |
| 267 | restart_reason = readl(RESTART_REASON_ADDR); |
| 268 | writel(0x00, RESTART_REASON_ADDR); |
| 269 | |
| 270 | return restart_reason; |
| 271 | } |
| 272 | |
| 273 | unsigned check_hard_reboot_mode(void) |
| 274 | { |
| 275 | uint8_t hard_restart_reason = 0; |
| 276 | uint8_t value = 0; |
| 277 | |
| 278 | /* Read reboot reason and scrub it |
| 279 | * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason |
| 280 | */ |
| 281 | value = pm8x41_reg_read(PON_SOFT_RB_SPARE); |
| 282 | hard_restart_reason = value >> 5; |
| 283 | pm8x41_reg_write(PON_SOFT_RB_SPARE, value & 0x1f); |
| 284 | |
| 285 | return hard_restart_reason; |
| 286 | } |
| 287 | |
| 288 | int set_download_mode(enum dload_mode mode) |
| 289 | { |
| 290 | int ret = 0; |
| 291 | ret = scm_dload_mode(mode); |
| 292 | |
| 293 | pm8x41_clear_pmic_watchdog(); |
| 294 | |
| 295 | return ret; |
| 296 | } |
| 297 | |
| 298 | int emmc_recovery_init(void) |
| 299 | { |
| 300 | return _emmc_recovery_init(); |
| 301 | } |
| 302 | |
| 303 | void reboot_device(unsigned reboot_reason) |
| 304 | { |
| 305 | uint8_t reset_type = 0; |
| 306 | uint32_t ret = 0; |
| 307 | |
| 308 | /* Need to clear the SW_RESET_ENTRY register and |
| 309 | * write to the BOOT_MISC_REG for known reset cases |
| 310 | */ |
| 311 | if(reboot_reason != DLOAD) |
| 312 | scm_dload_mode(NORMAL_MODE); |
| 313 | |
| 314 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 315 | |
| 316 | /* For Reboot-bootloader and Dload cases do a warm reset |
| 317 | * For Reboot cases do a hard reset |
| 318 | */ |
| 319 | if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD)) |
| 320 | reset_type = PON_PSHOLD_WARM_RESET; |
| 321 | else |
| 322 | reset_type = PON_PSHOLD_HARD_RESET; |
| 323 | |
| 324 | pm8x41_reset_configure(reset_type); |
| 325 | |
| 326 | ret = scm_halt_pmic_arbiter(); |
| 327 | if (ret) |
| 328 | dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret); |
| 329 | |
| 330 | /* Drop PS_HOLD for MSM */ |
| 331 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 332 | |
| 333 | mdelay(5000); |
| 334 | |
| 335 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 336 | } |
| 337 | |
| 338 | #if USER_FORCE_RESET_SUPPORT |
| 339 | /* Return 1 if it is a force resin triggered by user. */ |
| 340 | uint32_t is_user_force_reset(void) |
| 341 | { |
| 342 | uint8_t poff_reason1 = pm8x41_get_pon_poff_reason1(); |
| 343 | uint8_t poff_reason2 = pm8x41_get_pon_poff_reason2(); |
| 344 | |
| 345 | dprintf(SPEW, "poff_reason1: %d\n", poff_reason1); |
| 346 | dprintf(SPEW, "poff_reason2: %d\n", poff_reason2); |
| 347 | if (pm8x41_get_is_cold_boot() && (poff_reason1 == KPDPWR_AND_RESIN || |
| 348 | poff_reason2 == STAGE3)) |
| 349 | return 1; |
| 350 | else |
| 351 | return 0; |
| 352 | } |
| 353 | #endif |
| 354 | |
| 355 | unsigned target_pause_for_battery_charge(void) |
| 356 | { |
| 357 | uint8_t pon_reason = pm8x41_get_pon_reason(); |
| 358 | uint8_t is_cold_boot = pm8x41_get_is_cold_boot(); |
| 359 | dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__, |
| 360 | pon_reason, is_cold_boot); |
| 361 | /* In case of fastboot reboot,adb reboot or if we see the power key |
| 362 | * pressed we do not want go into charger mode. |
| 363 | * fastboot reboot is warm boot with PON hard reset bit not set |
| 364 | * adb reboot is a cold boot with PON hard reset bit set |
| 365 | */ |
| 366 | if (is_cold_boot && |
| 367 | (!(pon_reason & HARD_RST)) && |
| 368 | (!(pon_reason & KPDPWR_N)) && |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 369 | ((pon_reason & USB_CHG))) |
Aparna Mallavarapu | ca67688 | 2015-01-19 20:39:06 +0530 | [diff] [blame] | 370 | return 1; |
| 371 | else |
| 372 | return 0; |
| 373 | } |
Aparna Mallavarapu | 7b638e6 | 2015-03-26 05:51:57 +0530 | [diff] [blame] | 374 | |
| 375 | void target_uninit(void) |
| 376 | { |
| 377 | mmc_put_card_to_sleep(dev); |
| 378 | sdhci_mode_disable(&dev->host); |
| 379 | } |
| 380 | |
| 381 | void target_usb_init(void) |
| 382 | { |
| 383 | uint32_t val; |
| 384 | |
| 385 | /* Select and enable external configuration with USB PHY */ |
| 386 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET); |
| 387 | |
| 388 | /* Enable sess_vld */ |
| 389 | val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; |
| 390 | writel(val, USB_GENCONFIG_2); |
| 391 | |
| 392 | /* Enable external vbus configuration in the LINK */ |
| 393 | val = readl(USB_USBCMD); |
| 394 | val |= SESS_VLD_CTRL; |
| 395 | writel(val, USB_USBCMD); |
| 396 | } |
| 397 | |
| 398 | void target_usb_stop(void) |
| 399 | { |
| 400 | /* Disable VBUS mimicing in the controller. */ |
| 401 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR); |
| 402 | } |