blob: 5fbfe56de9558f0ba42b6a3b6cb584d5780acc0c [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +05301/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <reg.h>
32#include <target.h>
33#include <platform.h>
34#include <uart_dm.h>
35#include <mmc.h>
36#include <platform/gpio.h>
37#include <dev/keys.h>
38#include <spmi_v2.h>
39#include <pm8x41.h>
40#include <board.h>
41#include <baseband.h>
42#include <hsusb.h>
43#include <scm.h>
44#include <platform/gpio.h>
45#include <platform/gpio.h>
46#include <platform/irqs.h>
47#include <platform/clock.h>
48#include <crypto5_wrapper.h>
49#include <partition_parser.h>
50#include <stdlib.h>
51
52#if LONG_PRESS_POWER_ON
53#include <shutdown_detect.h>
54#endif
55
56#define PMIC_ARB_CHANNEL_NUM 0
57#define PMIC_ARB_OWNER_ID 0
58#define TLMM_VOL_UP_BTN_GPIO 85
59
60#define FASTBOOT_MODE 0x77665500
61#define PON_SOFT_RB_SPARE 0x88F
62
63static uint32_t mmc_sdc_base[] =
64 { MSM_SDC1_BASE, MSM_SDC2_BASE };
65
66
67void target_early_init(void)
68{
69#if WITH_DEBUG_UART
70 uart_dm_init(1, 0, BLSP1_UART1_BASE);
71#endif
72}
73
74void target_mmc_caps(struct mmc_host *host)
75{
76 host->caps.ddr_mode = 0;
77 host->caps.hs200_mode = 0;
78 host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
79 host->caps.hs_clk_rate = MMC_CLK_50MHZ;
80}
81
82/* Return 1 if vol_up pressed */
83static int target_volume_up()
84{
85 uint8_t status = 0;
86
87 gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
88
89 /* Wait for the gpio config to take effect - debounce time */
90 thread_sleep(10);
91
92 /* Get status of GPIO */
93 status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
94
95 /* Active high signal. */
96 return status;
97}
98
99/* Return 1 if vol_down pressed */
100uint32_t target_volume_down()
101{
102 /* Volume down button tied in with PMIC RESIN. */
103 return pm8x41_resin_status();
104}
105
106static void target_keystatus()
107{
108 keys_init();
109
110 if(target_volume_down())
111 keys_post_event(KEY_VOLUMEDOWN, 1);
112
113 if(target_volume_up())
114 keys_post_event(KEY_VOLUMEUP, 1);
115}
116
117/* Configure PMIC and Drop PS_HOLD for shutdown */
118void shutdown_device()
119{
120 dprintf(CRITICAL, "Going down for shutdown.\n");
121
122 /* Configure PMIC for shutdown */
123 pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
124
125 /* Drop PS_HOLD for MSM */
126 writel(0x00, MPM2_MPM_PS_HOLD);
127
128 mdelay(5000);
129
130 dprintf(CRITICAL, "shutdown failed\n");
131
132 ASSERT(0);
133}
134
135
136void target_init(void)
137{
138 uint32_t base_addr;
139 uint8_t slot;
140
141 dprintf(INFO, "target_init()\n");
142
143 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
144
145 target_keystatus();
146
147 /* Trying Slot 1*/
148 slot = 1;
149 base_addr = mmc_sdc_base[slot - 1];
150 if (mmc_boot_main(slot, base_addr))
151 {
152
153 /* Trying Slot 2 next */
154 slot = 2;
155 base_addr = mmc_sdc_base[slot - 1];
156 if (mmc_boot_main(slot, base_addr)) {
157 dprintf(CRITICAL, "mmc init failed!");
158 ASSERT(0);
159 }
160 }
161#if LONG_PRESS_POWER_ON
162 shutdown_detect();
163#endif
164}
165
166void target_serialno(unsigned char *buf)
167{
168 uint32_t serialno;
169 if (target_is_emmc_boot()) {
170 serialno = mmc_get_psn();
171 snprintf((char *)buf, 13, "%x", serialno);
172 }
173}
174
175unsigned board_machtype(void)
176{
177}
178
179unsigned check_reboot_mode(void)
180{
181 uint32_t restart_reason = 0;
182
183 /* Read reboot reason and scrub it */
184 restart_reason = readl(RESTART_REASON_ADDR);
185 writel(0x00, RESTART_REASON_ADDR);
186
187 return restart_reason;
188}
189
190unsigned check_hard_reboot_mode(void)
191{
192 uint8_t hard_restart_reason = 0;
193 uint8_t value = 0;
194
195 /* Read reboot reason and scrub it
196 * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason
197 */
198 value = pm8x41_reg_read(PON_SOFT_RB_SPARE);
199 hard_restart_reason = value >> 5;
200 pm8x41_reg_write(PON_SOFT_RB_SPARE, value & 0x1f);
201
202 return hard_restart_reason;
203}
204
205int set_download_mode(enum dload_mode mode)
206{
207 int ret = 0;
208 ret = scm_dload_mode(mode);
209
210 pm8x41_clear_pmic_watchdog();
211
212 return ret;
213}
214
215int emmc_recovery_init(void)
216{
217 return _emmc_recovery_init();
218}
219
220void reboot_device(unsigned reboot_reason)
221{
222 uint8_t reset_type = 0;
223 uint32_t ret = 0;
224
225 /* Need to clear the SW_RESET_ENTRY register and
226 * write to the BOOT_MISC_REG for known reset cases
227 */
228 if(reboot_reason != DLOAD)
229 scm_dload_mode(NORMAL_MODE);
230
231 writel(reboot_reason, RESTART_REASON_ADDR);
232
233 /* For Reboot-bootloader and Dload cases do a warm reset
234 * For Reboot cases do a hard reset
235 */
236 if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD))
237 reset_type = PON_PSHOLD_WARM_RESET;
238 else
239 reset_type = PON_PSHOLD_HARD_RESET;
240
241 pm8x41_reset_configure(reset_type);
242
243 ret = scm_halt_pmic_arbiter();
244 if (ret)
245 dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret);
246
247 /* Drop PS_HOLD for MSM */
248 writel(0x00, MPM2_MPM_PS_HOLD);
249
250 mdelay(5000);
251
252 dprintf(CRITICAL, "Rebooting failed\n");
253}
254
255#if USER_FORCE_RESET_SUPPORT
256/* Return 1 if it is a force resin triggered by user. */
257uint32_t is_user_force_reset(void)
258{
259 uint8_t poff_reason1 = pm8x41_get_pon_poff_reason1();
260 uint8_t poff_reason2 = pm8x41_get_pon_poff_reason2();
261
262 dprintf(SPEW, "poff_reason1: %d\n", poff_reason1);
263 dprintf(SPEW, "poff_reason2: %d\n", poff_reason2);
264 if (pm8x41_get_is_cold_boot() && (poff_reason1 == KPDPWR_AND_RESIN ||
265 poff_reason2 == STAGE3))
266 return 1;
267 else
268 return 0;
269}
270#endif
271
272unsigned target_pause_for_battery_charge(void)
273{
274 uint8_t pon_reason = pm8x41_get_pon_reason();
275 uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
276 dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
277 pon_reason, is_cold_boot);
278 /* In case of fastboot reboot,adb reboot or if we see the power key
279 * pressed we do not want go into charger mode.
280 * fastboot reboot is warm boot with PON hard reset bit not set
281 * adb reboot is a cold boot with PON hard reset bit set
282 */
283 if (is_cold_boot &&
284 (!(pon_reason & HARD_RST)) &&
285 (!(pon_reason & KPDPWR_N)) &&
286 ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
287 return 1;
288 else
289 return 0;
290}