Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_MSMCOPPER_IOMAP_H_ |
| 30 | #define _PLATFORM_MSMCOPPER_IOMAP_H_ |
| 31 | |
Deepa Dinamani | 81eddd5 | 2012-05-31 11:18:50 -0700 | [diff] [blame] | 32 | #define SDRAM_START_ADDR 0x00000000 |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 33 | #define SDRAM_SEC_BANK_START_ADDR 0x10000000 |
Deepa Dinamani | 81eddd5 | 2012-05-31 11:18:50 -0700 | [diff] [blame] | 34 | |
| 35 | #define MSM_SHARED_BASE 0x0FA00000 |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 36 | |
| 37 | #define KPSS_BASE 0xF9000000 |
| 38 | |
| 39 | #define MSM_GIC_DIST_BASE KPSS_BASE |
| 40 | #define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000) |
| 41 | #define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000) |
| 42 | #define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000) |
| 43 | #define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000) |
| 44 | #define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000) |
Deepa Dinamani | 1f01f19 | 2012-08-10 16:04:10 -0700 | [diff] [blame^] | 45 | #define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000) |
| 46 | #define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000) |
| 47 | #define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 48 | |
| 49 | #define PERIPH_SS_BASE 0xF9800000 |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 50 | |
| 51 | #define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 52 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 53 | #define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800) |
| 54 | #define MSM_SDC3_BAM_BASE (PERIPH_SS_BASE + 0x00044000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 55 | #define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 56 | #define MSM_SDC3_DML_BASE (PERIPH_SS_BASE + 0x00064800) |
| 57 | #define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 58 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 59 | #define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800) |
| 60 | #define MSM_SDC4_BAM_BASE (PERIPH_SS_BASE + 0x000C4000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 61 | #define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 62 | #define MSM_SDC4_DML_BASE (PERIPH_SS_BASE + 0x000E4800) |
| 63 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 64 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000) |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 65 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000) |
| 66 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000) |
| 67 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000) |
| 68 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000) |
| 69 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000) |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 70 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 71 | |
| 72 | #define CLK_CTL_BASE 0xFC400000 |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 73 | |
Deepa Dinamani | c2a9b36 | 2012-02-23 15:15:54 -0800 | [diff] [blame] | 74 | #define SPMI_BASE 0xFC4C0000 |
| 75 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 76 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
| 77 | |
| 78 | #define TLMM_BASE_ADDR 0xFD500000 |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 79 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) |
| 80 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) |
| 81 | |
Deepa Dinamani | d642b80 | 2012-05-16 10:49:01 -0700 | [diff] [blame] | 82 | #define MPM2_MPM_CTRL_BASE 0xFC4A1000 |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 83 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 84 | |
| 85 | /* GPLL */ |
| 86 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x001C) |
| 87 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
| 88 | |
| 89 | /* SDCC */ |
| 90 | #define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */ |
| 91 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */ |
| 92 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8) |
| 93 | #define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC) |
| 94 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */ |
| 95 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */ |
| 96 | #define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */ |
| 97 | #define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */ |
| 98 | #define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */ |
| 99 | |
| 100 | /* UART */ |
| 101 | #define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x684) |
| 102 | #define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x68C) |
| 103 | #define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x690) |
| 104 | #define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x694) |
| 105 | #define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x698) |
| 106 | #define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x69C) |
| 107 | |
| 108 | #define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784) |
| 109 | #define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C) |
| 110 | #define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790) |
| 111 | #define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794) |
| 112 | #define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798) |
| 113 | #define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C) |
| 114 | |
| 115 | /* USB */ |
| 116 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 117 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 118 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 119 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 120 | |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 121 | #endif |