Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <qpnp_wled.h> |
| 38 | #include <board.h> |
| 39 | #include <mdp5.h> |
| 40 | #include <scm.h> |
| 41 | #include <endian.h> |
| 42 | #include <platform/gpio.h> |
| 43 | #include <platform/clock.h> |
| 44 | #include <platform/iomap.h> |
| 45 | #include <target/display.h> |
| 46 | #include "include/panel.h" |
| 47 | #include "include/display_resource.h" |
| 48 | |
| 49 | #define HFPLL_LDO_ID 12 |
| 50 | |
| 51 | #define GPIO_STATE_LOW 0 |
| 52 | #define GPIO_STATE_HIGH 2 |
| 53 | #define RESET_GPIO_SEQ_LEN 3 |
| 54 | |
| 55 | #define PWM_DUTY_US 13 |
| 56 | #define PWM_PERIOD_US 27 |
| 57 | #define PMIC_WLED_SLAVE_ID 3 |
| 58 | #define PMIC_MPP_SLAVE_ID 2 |
| 59 | |
| 60 | static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off) |
| 61 | { |
| 62 | mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base); |
| 63 | |
| 64 | dmb(); |
| 65 | |
| 66 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */ |
| 67 | writel(0x80, pll_base + off + 0x0174); |
| 68 | |
| 69 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */ |
| 70 | writel(0x00, pll_base + off + 0x0174); |
| 71 | udelay(5000); |
| 72 | /* Strength ctrl 0 */ |
| 73 | writel(0x77, pll_base + off + 0x0184); |
| 74 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
| 75 | writel(0x7f, pll_base + off + 0x0170); |
| 76 | |
| 77 | /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */ |
| 78 | writel(0x00, pll_base + off + 0x01d4); |
| 79 | |
| 80 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */ |
| 81 | writel(0x00, pll_base + off + 0x0178); |
| 82 | } |
| 83 | |
| 84 | static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base) |
| 85 | { |
| 86 | uint32_t pll_locked; |
| 87 | |
| 88 | /* |
| 89 | * PLL power up sequence. |
| 90 | * Add necessary delays recommeded by hardware. |
| 91 | */ |
| 92 | writel(0x0D, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */ |
| 93 | writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */ |
| 94 | writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */ |
| 95 | udelay(500); |
| 96 | |
| 97 | dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */ |
| 98 | dmb(); |
| 99 | |
| 100 | pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base); |
| 101 | if (!pll_locked) |
| 102 | dprintf(INFO, "%s: DSI PLL lock failed\n", __func__); |
| 103 | else |
| 104 | dprintf(INFO, "%s: DSI PLL lock Success\n", __func__); |
| 105 | |
| 106 | return pll_locked; |
| 107 | } |
| 108 | |
| 109 | static int msm8994_wled_backlight_ctrl(uint8_t enable) |
| 110 | { |
| 111 | uint8_t slave_id = 3; |
| 112 | |
| 113 | if (enable) { |
| 114 | pm8x41_wled_config_slave_id(slave_id); |
| 115 | qpnp_wled_enable_backlight(enable); |
| 116 | } |
| 117 | qpnp_ibb_enable(enable); |
| 118 | return NO_ERROR; |
| 119 | } |
| 120 | |
| 121 | static int msm8994_pwm_backlight_ctrl(uint8_t enable) |
| 122 | { |
| 123 | dprintf(INFO, "%s: NOt implemented\n", __func__); |
| 124 | return NO_ERROR; |
| 125 | } |
| 126 | |
Kuogee Hsieh | 208736d | 2014-08-22 14:16:55 -0700 | [diff] [blame^] | 127 | void lcd_reg_enable(void) |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 128 | { |
| 129 | struct pm8x41_gpio gpio = { |
| 130 | .direction = PM_GPIO_DIR_OUT, |
| 131 | .function = PM_GPIO_FUNC_HIGH, |
| 132 | .vin_sel = 2, /* VIN_2 */ |
| 133 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 134 | .out_strength = PM_GPIO_OUT_DRIVE_MED, |
| 135 | }; |
| 136 | |
Kuogee Hsieh | 208736d | 2014-08-22 14:16:55 -0700 | [diff] [blame^] | 137 | pm8x41_gpio_config(lcd_reg_en.pin_id, &gpio); |
| 138 | pm8x41_gpio_set(lcd_reg_en.pin_id, 1); |
| 139 | } |
| 140 | |
| 141 | void lcd_reg_disable(void) |
| 142 | { |
| 143 | pm8x41_gpio_set(lcd_reg_en.pin_id, 0); |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 147 | { |
| 148 | uint32_t ret = NO_ERROR; |
| 149 | struct pm8x41_mpp mpp; |
| 150 | int rc; |
| 151 | |
| 152 | if (!bl) { |
| 153 | dprintf(CRITICAL, "backlight structure is not available\n"); |
| 154 | return ERR_INVALID_ARGS; |
| 155 | } |
| 156 | |
| 157 | switch (bl->bl_interface_type) { |
| 158 | case BL_WLED: |
| 159 | /* Enable MPP4 */ |
| 160 | pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID); |
| 161 | mpp.base = PM8x41_MMP4_BASE; |
| 162 | mpp.vin = MPP_VIN2; |
| 163 | if (enable) { |
| 164 | pm_pwm_enable(false); |
| 165 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 166 | if (rc < 0) { |
| 167 | mpp.mode = MPP_HIGH; |
| 168 | } else { |
| 169 | mpp.mode = MPP_DTEST1; |
| 170 | pm_pwm_enable(true); |
| 171 | } |
| 172 | pm8x41_config_output_mpp(&mpp); |
| 173 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 174 | } else { |
| 175 | pm_pwm_enable(false); |
| 176 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 177 | } |
| 178 | /* Need delay before power on regulators */ |
| 179 | mdelay(20); |
| 180 | /* Enable WLED backlight control */ |
| 181 | ret = msm8994_wled_backlight_ctrl(enable); |
| 182 | break; |
| 183 | case BL_PWM: |
| 184 | ret = msm8994_pwm_backlight_ctrl(enable); |
| 185 | break; |
| 186 | default: |
| 187 | dprintf(CRITICAL, "backlight type:%d not supported\n", |
| 188 | bl->bl_interface_type); |
| 189 | return ERR_NOT_SUPPORTED; |
| 190 | } |
| 191 | |
| 192 | return ret; |
| 193 | } |
| 194 | |
| 195 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 196 | { |
| 197 | uint32_t ret; |
| 198 | struct mdss_dsi_pll_config *pll_data; |
| 199 | uint32_t dual_dsi = pinfo->mipi.dual_dsi; |
| 200 | |
| 201 | pll_data = pinfo->mipi.dsi_pll_config; |
| 202 | if (enable) { |
| 203 | mdp_gdsc_ctrl(enable); |
| 204 | mmss_bus_clock_enable(); |
| 205 | mdp_clock_enable(); |
| 206 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 207 | if (ret) { |
| 208 | dprintf(CRITICAL, |
| 209 | "%s: Failed to restore MDP security configs", |
| 210 | __func__); |
| 211 | mdp_clock_disable(); |
| 212 | mmss_bus_clock_disable(); |
| 213 | mdp_gdsc_ctrl(0); |
| 214 | return ret; |
| 215 | } |
| 216 | mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE, |
| 217 | MIPI_DSI0_BASE, pll_data); |
| 218 | dsi_pll_20nm_enable_seq(DSI0_PLL_BASE); |
| 219 | mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi, |
| 220 | pll_data->pclk_m, |
| 221 | pll_data->pclk_n, |
| 222 | pll_data->pclk_d); |
| 223 | } else if(!target_cont_splash_screen()) { |
| 224 | /* Disable clocks if continuous splash off */ |
| 225 | mmss_dsi_clock_disable(dual_dsi); |
| 226 | mdp_clock_disable(); |
| 227 | mmss_bus_clock_disable(); |
| 228 | mdp_gdsc_ctrl(enable); |
| 229 | } |
| 230 | |
| 231 | return NO_ERROR; |
| 232 | } |
| 233 | |
| 234 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 235 | struct msm_panel_info *pinfo) |
| 236 | { |
| 237 | uint32_t i = 0; |
| 238 | |
| 239 | if (enable) { |
| 240 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 241 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 242 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 243 | /* reset */ |
| 244 | for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 245 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 246 | gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 247 | else |
| 248 | gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 249 | mdelay(resetseq->sleep[i]); |
| 250 | } |
| 251 | } else { |
| 252 | gpio_set(reset_gpio.pin_id, 0); |
| 253 | } |
| 254 | |
| 255 | return NO_ERROR; |
| 256 | } |
| 257 | |
Kuogee Hsieh | 93bcff6 | 2014-08-22 14:02:08 -0700 | [diff] [blame] | 258 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 259 | { |
| 260 | if (enable) { |
| 261 | regulator_enable(); /* L2, L12, L14, and L28 */ |
| 262 | mdelay(10); |
| 263 | qpnp_ibb_enable(true); /* +5V and -5V */ |
| 264 | mdelay(50); |
Kuogee Hsieh | 208736d | 2014-08-22 14:16:55 -0700 | [diff] [blame^] | 265 | |
| 266 | if (pinfo->lcd_reg_en) |
| 267 | lcd_reg_enable(); |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 268 | } else { |
Kuogee Hsieh | 208736d | 2014-08-22 14:16:55 -0700 | [diff] [blame^] | 269 | if (pinfo->lcd_reg_en) |
| 270 | lcd_reg_disable(); |
| 271 | |
Dhaval Patel | 019057a | 2014-08-12 13:52:25 -0700 | [diff] [blame] | 272 | regulator_disable(); |
| 273 | } |
| 274 | |
| 275 | return NO_ERROR; |
| 276 | } |
| 277 | |
| 278 | int target_display_pre_on() |
| 279 | { |
| 280 | writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0); |
| 281 | writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1); |
| 282 | writel(0xC0000CCD, MDP_CLK_CTRL0); |
| 283 | writel(0xD0000CCC, MDP_CLK_CTRL1); |
| 284 | writel(0x00CCCCCC, MDP_CLK_CTRL2); |
| 285 | writel(0x000000CC, MDP_CLK_CTRL6); |
| 286 | writel(0x0CCCC0C0, MDP_CLK_CTRL3); |
| 287 | writel(0xCCCCC0C0, MDP_CLK_CTRL4); |
| 288 | writel(0xCCCCC0C0, MDP_CLK_CTRL5); |
| 289 | writel(0x00CCC000, MDP_CLK_CTRL7); |
| 290 | |
| 291 | writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0); |
| 292 | writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1); |
| 293 | writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2); |
| 294 | writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3); |
| 295 | writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0); |
| 296 | writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1); |
| 297 | writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2); |
| 298 | writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3); |
| 299 | writel(0x00013fff, VBIF_VBIF_ABIT_SHORT); |
| 300 | writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF); |
| 301 | writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN); |
| 302 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 303 | |
| 304 | return NO_ERROR; |
| 305 | } |
| 306 | |
| 307 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 308 | { |
| 309 | int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX); |
| 310 | bool ret = true; |
| 311 | |
| 312 | ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size); |
| 313 | |
| 314 | return ret; |
| 315 | } |
| 316 | |
| 317 | void target_display_init(const char *panel_name) |
| 318 | { |
| 319 | if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR)) |
| 320 | msm_display_off(); |
| 321 | } |
| 322 | |
| 323 | void target_display_shutdown(void) |
| 324 | { |
| 325 | gcdb_display_shutdown(); |
| 326 | } |