Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <string.h> |
| 32 | #include <smem.h> |
| 33 | #include <err.h> |
| 34 | #include <msm_panel.h> |
| 35 | #include <mipi_dsi.h> |
| 36 | #include <pm8x41.h> |
| 37 | #include <pm8x41_wled.h> |
| 38 | #include <qpnp_wled.h> |
| 39 | #include <board.h> |
| 40 | #include <mdp5.h> |
| 41 | #include <endian.h> |
| 42 | #include <regulator.h> |
| 43 | #include <qtimer.h> |
| 44 | #include <arch/defines.h> |
| 45 | #include <platform/gpio.h> |
| 46 | #include <platform/clock.h> |
| 47 | #include <platform/iomap.h> |
| 48 | #include <target/display.h> |
| 49 | #include <mipi_dsi_autopll_thulium.h> |
| 50 | |
| 51 | #include "include/panel.h" |
| 52 | #include "include/display_resource.h" |
| 53 | #include "gcdb_display.h" |
| 54 | |
| 55 | #define GPIO_STATE_LOW 0 |
| 56 | #define GPIO_STATE_HIGH 2 |
| 57 | #define RESET_GPIO_SEQ_LEN 3 |
| 58 | |
| 59 | #define PWM_DUTY_US 13 |
| 60 | #define PWM_PERIOD_US 27 |
| 61 | #define PMIC_WLED_SLAVE_ID 3 |
| 62 | #define PMIC_MPP_SLAVE_ID 2 |
| 63 | |
| 64 | #define MAX_POLL_READS 15 |
| 65 | #define POLL_TIMEOUT_US 1000 |
| 66 | |
| 67 | #define STRENGTH_SIZE_IN_BYTES_8996 10 |
| 68 | #define REGULATOR_SIZE_IN_BYTES_8996 5 |
| 69 | #define LANE_SIZE_IN_BYTES_8996 20 |
| 70 | |
Dhaval Patel | a2aa6c1 | 2015-05-27 17:03:06 -0700 | [diff] [blame] | 71 | #define DSC_CMD_PANEL "dsc_cmd_panel" |
| 72 | #define DSC_VID_PANEL "dsc_vid_panel" |
| 73 | #define DSC_CMD_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_cmd" |
| 74 | #define DSC_VID_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_video" |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 75 | /*---------------------------------------------------------------------------*/ |
| 76 | /* GPIO configuration */ |
| 77 | /*---------------------------------------------------------------------------*/ |
| 78 | static struct gpio_pin reset_gpio = { |
| 79 | "msmgpio", 8, 3, 1, 0, 1 |
| 80 | }; |
| 81 | |
| 82 | static struct gpio_pin lcd_reg_en = { /* boost regulator */ |
| 83 | "pmi8994_gpios", 8, 3, 1, 0, 1 |
| 84 | }; |
| 85 | |
| 86 | static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */ |
| 87 | "pm8994_gpios", 14, 3, 1, 0, 1 |
| 88 | }; |
| 89 | |
| 90 | static uint32_t thulium_dsi_pll_lock_status(uint32_t pll_base, uint32_t off, |
| 91 | uint32_t bit) |
| 92 | { |
| 93 | uint32_t cnt, status; |
| 94 | |
| 95 | /* check pll lock first */ |
| 96 | for (cnt = 0; cnt < MAX_POLL_READS; cnt++) { |
| 97 | status = readl(pll_base + off); |
| 98 | dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n", |
| 99 | __func__, pll_base, cnt, status); |
| 100 | status &= BIT(bit); /* bit 5 */ |
| 101 | if (status) |
| 102 | break; |
| 103 | udelay(POLL_TIMEOUT_US); |
| 104 | } |
| 105 | |
| 106 | return status; |
| 107 | } |
| 108 | |
| 109 | static uint32_t thulium_dsi_pll_enable_seq(uint32_t phy_base, uint32_t pll_base) |
| 110 | { |
| 111 | uint32_t pll_locked; |
| 112 | |
| 113 | writel(0x01, phy_base + 0x48); |
| 114 | dmb(); |
| 115 | |
| 116 | pll_locked = thulium_dsi_pll_lock_status(pll_base, 0xcc, 5); |
| 117 | if (pll_locked) |
| 118 | pll_locked = thulium_dsi_pll_lock_status(pll_base, 0xcc, 0); |
| 119 | |
| 120 | if (!pll_locked) |
| 121 | dprintf(ERROR, "%s: DSI PLL lock failed\n", __func__); |
| 122 | else |
| 123 | dprintf(SPEW, "%s: DSI PLL lock Success\n", __func__); |
| 124 | |
| 125 | return pll_locked; |
| 126 | } |
| 127 | |
| 128 | static int thulium_wled_backlight_ctrl(uint8_t enable) |
| 129 | { |
| 130 | qpnp_wled_enable_backlight(enable); |
| 131 | qpnp_ibb_enable(enable); |
| 132 | return NO_ERROR; |
| 133 | } |
| 134 | |
| 135 | static int thulium_pwm_backlight_ctrl(uint8_t enable) |
| 136 | { |
| 137 | uint8_t slave_id = 3; /* lpg at pmi */ |
| 138 | |
| 139 | if (enable) { |
| 140 | /* lpg channel 4 */ |
| 141 | |
| 142 | /* LPG_ENABLE_CONTROL */ |
| 143 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0); |
| 144 | mdelay(100); |
| 145 | |
| 146 | /* LPG_VALUE_LSB, duty cycle = 0x80/0x200 = 1/4 */ |
| 147 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x44, 0x80); |
| 148 | /* LPG_VALUE_MSB */ |
| 149 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x45, 0x00); |
| 150 | /* LPG_PWM_SYNC */ |
| 151 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x47, 0x01); |
| 152 | |
| 153 | /* LPG_PWM_SIZE_CLK, */ |
| 154 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x41, 0x13); |
| 155 | /* LPG_PWM_FREQ_PREDIV */ |
| 156 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x42, 0x02); |
| 157 | /* LPG_PWM_TYPE_CONFIG */ |
| 158 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x43, 0x20); |
| 159 | /* LPG_ENABLE_CONTROL */ |
| 160 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x04); |
| 161 | |
| 162 | /* SEC_ACCESS */ |
| 163 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xD0, 0xA5); |
| 164 | /* DTEST4, OUT_HI */ |
| 165 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xE5, 0x01); |
| 166 | /* LPG_ENABLE_CONTROL */ |
| 167 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0xA4); |
| 168 | } else { |
| 169 | /* LPG_ENABLE_CONTROL */ |
| 170 | pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0); |
| 171 | } |
| 172 | |
| 173 | return NO_ERROR; |
| 174 | } |
| 175 | |
| 176 | static void lcd_reg_enable(void) |
| 177 | { |
| 178 | uint8_t slave_id = 2; /* gpio at pmi */ |
| 179 | |
| 180 | struct pm8x41_gpio gpio = { |
| 181 | .direction = PM_GPIO_DIR_OUT, |
| 182 | .function = PM_GPIO_FUNC_HIGH, |
| 183 | .vin_sel = 2, /* VIN_2 */ |
| 184 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 185 | .out_strength = PM_GPIO_OUT_DRIVE_MED, |
| 186 | }; |
| 187 | |
| 188 | pm8x41_gpio_config_sid(slave_id, lcd_reg_en.pin_id, &gpio); |
| 189 | pm8x41_gpio_set_sid(slave_id, lcd_reg_en.pin_id, 1); |
| 190 | } |
| 191 | |
| 192 | static void lcd_reg_disable(void) |
| 193 | { |
| 194 | uint8_t slave_id = 2; /* gpio at pmi */ |
| 195 | |
| 196 | pm8x41_gpio_set_sid(slave_id, lcd_reg_en.pin_id, 0); |
| 197 | } |
| 198 | |
| 199 | static void lcd_bklt_reg_enable(void) |
| 200 | { |
| 201 | struct pm8x41_gpio gpio = { |
| 202 | .direction = PM_GPIO_DIR_OUT, |
| 203 | .function = PM_GPIO_FUNC_HIGH, |
| 204 | .vin_sel = 2, /* VIN_2 */ |
| 205 | .output_buffer = PM_GPIO_OUT_CMOS, |
| 206 | .out_strength = PM_GPIO_OUT_DRIVE_LOW, |
| 207 | }; |
| 208 | |
| 209 | pm8x41_gpio_config(bklt_gpio.pin_id, &gpio); |
| 210 | pm8x41_gpio_set(bklt_gpio.pin_id, 1); |
| 211 | } |
| 212 | |
| 213 | static void lcd_bklt_reg_disable(void) |
| 214 | { |
| 215 | pm8x41_gpio_set(bklt_gpio.pin_id, 0); |
| 216 | } |
| 217 | |
| 218 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 219 | { |
| 220 | uint32_t ret = NO_ERROR; |
| 221 | struct pm8x41_mpp mpp; |
| 222 | int rc; |
| 223 | |
| 224 | if (!bl) { |
| 225 | dprintf(CRITICAL, "backlight structure is not available\n"); |
| 226 | return ERR_INVALID_ARGS; |
| 227 | } |
| 228 | |
| 229 | switch (bl->bl_interface_type) { |
| 230 | case BL_WLED: |
| 231 | /* Enable MPP4 */ |
| 232 | pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID); |
| 233 | mpp.base = PM8x41_MMP4_BASE; |
| 234 | mpp.vin = MPP_VIN2; |
| 235 | if (enable) { |
| 236 | pm_pwm_enable(false); |
| 237 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 238 | if (rc < 0) { |
| 239 | mpp.mode = MPP_HIGH; |
| 240 | } else { |
| 241 | mpp.mode = MPP_DTEST1; |
| 242 | pm_pwm_enable(true); |
| 243 | } |
| 244 | pm8x41_config_output_mpp(&mpp); |
| 245 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 246 | } else { |
| 247 | pm_pwm_enable(false); |
| 248 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 249 | } |
| 250 | /* Need delay before power on regulators */ |
| 251 | mdelay(20); |
| 252 | /* Enable WLED backlight control */ |
| 253 | ret = thulium_wled_backlight_ctrl(enable); |
| 254 | break; |
| 255 | case BL_PWM: |
| 256 | /* Enable MPP1 */ |
| 257 | pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID); |
| 258 | mpp.base = PM8x41_MMP1_BASE; |
| 259 | mpp.vin = MPP_VIN2; |
| 260 | mpp.mode = MPP_DTEST4; |
| 261 | if (enable) { |
| 262 | pm8x41_config_output_mpp(&mpp); |
| 263 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 264 | } else { |
| 265 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 266 | } |
| 267 | /* Need delay before power on regulators */ |
| 268 | mdelay(20); |
| 269 | ret = thulium_pwm_backlight_ctrl(enable); |
| 270 | break; |
| 271 | default: |
| 272 | dprintf(CRITICAL, "backlight type:%d not supported\n", |
| 273 | bl->bl_interface_type); |
| 274 | return ERR_NOT_SUPPORTED; |
| 275 | } |
| 276 | |
| 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 281 | { |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 282 | uint32_t flags, dsi_phy_pll_out; |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 283 | uint32_t ret = NO_ERROR; |
| 284 | uint32_t board_version = board_soc_version(); |
| 285 | |
| 286 | if (pinfo->dest == DISPLAY_2) { |
| 287 | flags = MMSS_DSI_CLKS_FLAG_DSI1; |
| 288 | if (pinfo->mipi.dual_dsi) |
| 289 | flags |= MMSS_DSI_CLKS_FLAG_DSI0; |
| 290 | } else { |
| 291 | flags = MMSS_DSI_CLKS_FLAG_DSI0; |
| 292 | if (pinfo->mipi.dual_dsi) |
| 293 | flags |= MMSS_DSI_CLKS_FLAG_DSI1; |
| 294 | } |
| 295 | |
| 296 | if (!enable) { |
| 297 | /* stop pll */ |
| 298 | writel(0x0, pinfo->mipi.phy_base + 0x48); |
| 299 | dmb(); |
| 300 | |
| 301 | mmss_dsi_clock_disable(flags); |
| 302 | goto clks_disable; |
| 303 | } |
| 304 | |
| 305 | if (board_version == 0x20000 || board_version == 0x20001) |
| 306 | video_gdsc_enable(); |
| 307 | mmss_gdsc_enable(); |
| 308 | mmss_bus_clock_enable(); |
| 309 | mdp_clock_enable(); |
| 310 | mdss_dsi_auto_pll_thulium_config(pinfo); |
| 311 | |
| 312 | if (!thulium_dsi_pll_enable_seq(pinfo->mipi.phy_base, |
| 313 | pinfo->mipi.pll_base)) { |
| 314 | ret = ERROR; |
| 315 | dprintf(CRITICAL, "PLL failed to lock!\n"); |
| 316 | goto clks_disable; |
| 317 | } |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 318 | |
| 319 | if (pinfo->mipi.use_dsi1_pll) |
| 320 | dsi_phy_pll_out = DSI1_PHY_PLL_OUT; |
| 321 | else |
| 322 | dsi_phy_pll_out = DSI0_PHY_PLL_OUT; |
| 323 | mmss_dsi_clock_enable(dsi_phy_pll_out, flags); |
| 324 | |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 325 | return NO_ERROR; |
| 326 | |
| 327 | clks_disable: |
| 328 | mdp_clock_disable(); |
| 329 | mmss_bus_clock_disable(); |
| 330 | mmss_gdsc_disable(); |
| 331 | if (board_version == 0x20000 || board_version == 0x20001) |
| 332 | video_gdsc_disable(); |
| 333 | |
| 334 | return ret; |
| 335 | } |
| 336 | |
| 337 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 338 | struct msm_panel_info *pinfo) |
| 339 | { |
| 340 | uint32_t i = 0; |
| 341 | |
| 342 | if (enable) { |
| 343 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 344 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 345 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 346 | /* reset */ |
| 347 | for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 348 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 349 | gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 350 | else |
| 351 | gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 352 | mdelay(resetseq->sleep[i]); |
| 353 | } |
| 354 | lcd_bklt_reg_enable(); |
| 355 | } else { |
| 356 | lcd_bklt_reg_disable(); |
| 357 | gpio_set(reset_gpio.pin_id, 0); |
| 358 | } |
| 359 | |
| 360 | return NO_ERROR; |
| 361 | } |
| 362 | |
| 363 | static void wled_init(struct msm_panel_info *pinfo) |
| 364 | { |
| 365 | struct qpnp_wled_config_data config = {0}; |
| 366 | struct labibb_desc *labibb; |
| 367 | int display_type = 0; |
| 368 | |
| 369 | labibb = pinfo->labibb; |
| 370 | |
| 371 | if (labibb) |
| 372 | display_type = labibb->amoled_panel; |
| 373 | |
| 374 | config.display_type = display_type; |
| 375 | config.lab_init_volt = 4600000; /* fixed, see pmi register */ |
| 376 | config.ibb_init_volt = 1400000; /* fixed, see pmi register */ |
| 377 | |
| 378 | if (labibb && labibb->force_config) { |
| 379 | config.lab_min_volt = labibb->lab_min_volt; |
| 380 | config.lab_max_volt = labibb->lab_max_volt; |
| 381 | config.ibb_min_volt = labibb->ibb_min_volt; |
| 382 | config.ibb_max_volt = labibb->ibb_max_volt; |
| 383 | config.pwr_up_delay = labibb->pwr_up_delay; |
| 384 | config.pwr_down_delay = labibb->pwr_down_delay; |
| 385 | config.ibb_discharge_en = labibb->ibb_discharge_en; |
| 386 | } else { |
| 387 | /* default */ |
| 388 | config.pwr_up_delay = 3; |
| 389 | config.pwr_down_delay = 3; |
| 390 | config.ibb_discharge_en = 1; |
| 391 | if (display_type) { /* amoled */ |
| 392 | config.lab_min_volt = 4600000; |
| 393 | config.lab_max_volt = 4600000; |
| 394 | config.ibb_min_volt = 4000000; |
| 395 | config.ibb_max_volt = 4000000; |
| 396 | } else { /* lcd */ |
| 397 | config.lab_min_volt = 5500000; |
| 398 | config.lab_max_volt = 5500000; |
| 399 | config.ibb_min_volt = 5500000; |
| 400 | config.ibb_max_volt = 5500000; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__, |
| 405 | config.display_type, |
| 406 | config.lab_min_volt, config.lab_max_volt, |
| 407 | config.ibb_min_volt, config.ibb_max_volt, |
| 408 | config.lab_init_volt, config.ibb_init_volt, |
| 409 | config.pwr_up_delay, config.pwr_down_delay, |
| 410 | config.ibb_discharge_en); |
| 411 | |
| 412 | |
| 413 | /* QPNP WLED init for display backlight */ |
| 414 | pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID); |
| 415 | |
| 416 | qpnp_wled_init(&config); |
| 417 | } |
| 418 | |
| 419 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
| 420 | { |
| 421 | uint32_t val = BIT(1) | BIT(13) | BIT(27); |
| 422 | |
| 423 | if (enable) { |
| 424 | regulator_enable(val); |
| 425 | mdelay(10); |
| 426 | wled_init(pinfo); |
| 427 | qpnp_ibb_enable(true); /* +5V and -5V */ |
| 428 | mdelay(50); |
| 429 | |
| 430 | if (pinfo->lcd_reg_en) |
| 431 | lcd_reg_enable(); |
| 432 | } else { |
| 433 | if (pinfo->lcd_reg_en) |
| 434 | lcd_reg_disable(); |
| 435 | |
| 436 | regulator_disable(val); |
| 437 | } |
| 438 | |
| 439 | return NO_ERROR; |
| 440 | } |
| 441 | |
| 442 | int target_display_pre_on() |
| 443 | { |
| 444 | writel(0xC0000CCC, MDP_CLK_CTRL0); |
| 445 | writel(0xC0000CCC, MDP_CLK_CTRL1); |
| 446 | writel(0x00CCCCCC, MDP_CLK_CTRL2); |
| 447 | writel(0x000000CC, MDP_CLK_CTRL6); |
| 448 | writel(0x0CCCC0C0, MDP_CLK_CTRL3); |
| 449 | writel(0xCCCCC0C0, MDP_CLK_CTRL4); |
| 450 | writel(0xCCCCC0C0, MDP_CLK_CTRL5); |
| 451 | writel(0x00CCC000, MDP_CLK_CTRL7); |
| 452 | |
| 453 | return NO_ERROR; |
| 454 | } |
| 455 | |
| 456 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 457 | { |
| 458 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE_IN_BYTES_8996 * |
| 459 | sizeof(uint32_t)); |
| 460 | memcpy(phy_db->regulator, panel_regulator_settings, |
| 461 | REGULATOR_SIZE_IN_BYTES_8996 * sizeof(uint32_t)); |
| 462 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE_IN_BYTES_8996); |
| 463 | return NO_ERROR; |
| 464 | } |
| 465 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 466 | bool target_display_panel_node(char *pbuf, uint16_t buf_size) |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 467 | { |
| 468 | int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX); |
| 469 | bool ret = true; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 470 | struct oem_panel_data oem = mdss_dsi_get_oem_data(); |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 471 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 472 | if (!strcmp(oem.panel, HDMI_PANEL_NAME)) { |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 473 | if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN + |
| 474 | strlen(HDMI_CONTROLLER_STRING))) { |
| 475 | dprintf(CRITICAL, "command line argument is greater than buffer size\n"); |
| 476 | return false; |
| 477 | } |
| 478 | |
| 479 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 480 | buf_size -= prefix_string_len; |
| 481 | strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size); |
| 482 | buf_size -= LK_OVERRIDE_PANEL_LEN; |
| 483 | strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size); |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 484 | } else if (!strcmp(oem.panel, DSC_CMD_PANEL)) { |
Dhaval Patel | a2aa6c1 | 2015-05-27 17:03:06 -0700 | [diff] [blame] | 485 | if (buf_size < (prefix_string_len + |
| 486 | strlen(DSC_CMD_PANEL_STRING))) { |
| 487 | dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n"); |
| 488 | return false; |
| 489 | } |
| 490 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 491 | buf_size -= prefix_string_len; |
| 492 | pbuf += prefix_string_len; |
| 493 | strlcpy(pbuf, DSC_CMD_PANEL_STRING, buf_size); |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 494 | } else if (!strcmp(oem.panel, DSC_VID_PANEL)) { |
Dhaval Patel | a2aa6c1 | 2015-05-27 17:03:06 -0700 | [diff] [blame] | 495 | if (buf_size < (prefix_string_len + |
| 496 | strlen(DSC_VID_PANEL_STRING))) { |
| 497 | dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n"); |
| 498 | return false; |
| 499 | } |
| 500 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 501 | buf_size -= prefix_string_len; |
| 502 | pbuf += prefix_string_len; |
| 503 | strlcpy(pbuf, DSC_VID_PANEL_STRING, buf_size); |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 504 | } else { |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 505 | ret = gcdb_display_cmdline_arg(pbuf, buf_size); |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | return ret; |
| 509 | } |
| 510 | |
| 511 | void target_display_init(const char *panel_name) |
| 512 | { |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 513 | struct oem_panel_data oem; |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 514 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 515 | set_panel_cmd_string(panel_name); |
| 516 | oem = mdss_dsi_get_oem_data(); |
| 517 | if (!strcmp(oem.panel, NO_PANEL_CONFIG) |
| 518 | || !strcmp(oem.panel, SIM_VIDEO_PANEL) |
| 519 | || !strcmp(oem.panel, SIM_DUALDSI_VIDEO_PANEL) |
| 520 | || !strcmp(oem.panel, SIM_CMD_PANEL) |
| 521 | || !strcmp(oem.panel, SIM_DUALDSI_CMD_PANEL) |
| 522 | || !strcmp(oem.panel, DSC_CMD_PANEL) |
| 523 | || !strcmp(oem.panel, DSC_VID_PANEL) |
| 524 | || oem.skip) { |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 525 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 526 | oem.panel); |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 527 | return; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 528 | } else if (!strcmp(oem.panel, HDMI_PANEL_NAME)) { |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 529 | return; |
| 530 | } |
| 531 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 532 | if (gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR)) { |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 533 | target_force_cont_splash_disable(true); |
| 534 | msm_display_off(); |
| 535 | } |
| 536 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 537 | if (!oem.cont_splash) { |
Dhaval Patel | b95039c | 2015-03-16 11:14:06 -0700 | [diff] [blame] | 538 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 539 | target_force_cont_splash_disable(true); |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | void target_display_shutdown(void) |
| 544 | { |
| 545 | gcdb_display_shutdown(); |
| 546 | } |