blob: 2f09b977e8608540153e6e75d1b89ec798d28102 [file] [log] [blame]
Umang Agrawald13b5fe2017-12-19 12:09:31 +05301/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <bits.h>
30#include <debug.h>
31#include <reg.h>
32
33#define QPNP_LCDB_BASE 0x3ec00
34#define QPNP_LCDB_BST_OUTPUT_VOLTAGE_REG 0x41
35#define QPNP_LCDB_LDO_OUTPUT_VOLTAGE_REG 0x71
36#define QPNP_LCDB_NCP_OUTPUT_VOLTAGE_REG 0x81
37#define QPNP_LCDB_ENABLE_CTL_REG 0x46
38#define QPNP_LCDB_PWRUP_PWRDN_CTL_REG 0x66
39#define QPNP_LCDB_MODULE_RDY_REG 0x45
40
41#define QPNP_LCDB_BST_OUTPUT_VOLTAGE_MASK 0x3F
42#define QPNP_LCDB_LDO_OUTPUT_VOLTAGE_MASK 0x1F
43#define QPNP_LCDB_NCP_OUTPUT_VOLTAGE_MASK 0x1F
44#define QPNP_LCDB_ENABLE_CTL_MASK 0x80
45#define QPNP_LCDB_PWRUP_DLY_MASK 0x0C
46#define QPNP_LCDB_PWRDN_DLY_MASK 0x03
47#define QPNP_LCDB_MODULE_RDY_MASK 0x80
48
49#define LCDB_LDO_INIT_VOLTAGE_UV 4000000
Umang Agrawal2e447c82018-09-11 15:00:47 +053050#define LCDB_LDO_MAX_VOLTAGE_UV 6000000
Umang Agrawald13b5fe2017-12-19 12:09:31 +053051#define LCDB_NCP_INIT_VOLTAGE_UV 4000000
Umang Agrawal2e447c82018-09-11 15:00:47 +053052#define LCDB_NCP_MAX_VOLTAGE_UV 6000000
Umang Agrawald13b5fe2017-12-19 12:09:31 +053053#define LCDB_BOOST_INIT_VOLTAGE_UV 4700000
54#define LDO_VREG_STEP_SIZE_UV 50000
55#define NCP_VREG_STEP_SIZE_UV 50000
56#define BST_VREG_STEP_SIZE_UV 25000
57#define LCDB_BOOST_HEADROOM_VOLT_UV 150000
58#define QPNP_LCDB_PWRUP_DLY_MAX_MS 3
59#define QPNP_LCDB_PWRDN_DLY_MAX_MS 3
60#define LCDB_MODULE_RDY BIT(7)
61
62#define LCDB_ENABLE_SHIFT 7
63#define LCDB_PWRUP_DLY_SHIFT 2
Umang Agrawal2e447c82018-09-11 15:00:47 +053064#define LCDB_STEP_UV 500000
65
66#define min(a, b) (a) < (b) ? a : b
Umang Agrawald13b5fe2017-12-19 12:09:31 +053067
68struct qpnp_lcdb {
69 uint32_t lcdb_base;
70 uint16_t lcdb_pwrup_dly_ms;
71 uint16_t lcdb_pwrdn_dly_ms;
72 uint32_t ldo_min_volt;
73 uint32_t ldo_max_volt;
74 uint32_t ldo_init_volt;
75 uint32_t ncp_min_volt;
76 uint32_t ncp_max_volt;
77 uint32_t ncp_init_volt;
78 uint32_t bst_init_volt;
79};
80
81/* LCDB Init */
82int qpnp_lcdb_init(struct qpnp_wled_config_data *config);
83
84/* LCDB Enable */
85int qpnp_lcdb_enable(bool enable);