| Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_THULIUM_IOMAP_H_ |
| 30 | #define _PLATFORM_THULIUM_IOMAP_H_ |
| 31 | |
| 32 | #define MSM_SHARED_BASE 0x86000000 |
| 33 | |
| 34 | #define MSM_IOMAP_HMSS_START 0x09800000 |
| 35 | |
| 36 | #define MSM_IOMAP_BASE 0x00000000 |
| 37 | #define MSM_IOMAP_END 0x10000000 |
| 38 | |
| 39 | #define MSM_SHARED_IMEM_BASE 0x066BF000 |
| 40 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 41 | |
| 42 | #define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000) |
| 43 | #define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000) |
| 44 | |
| 45 | #define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000) |
| 46 | #define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE |
| 47 | |
| 48 | #define PERIPH_SS_BASE 0x07400000 |
| 49 | |
| 50 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000) |
| 51 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
| 52 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
| 53 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900) |
| 54 | |
| 55 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000) |
| 56 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000) |
| 57 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000) |
| 58 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000) |
| 59 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000) |
| 60 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000) |
| 61 | |
| 62 | #define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000) |
| 63 | |
| 64 | /* USB3.0 */ |
| 65 | #define MSM_USB30_BASE 0x6A00000 |
| 66 | #define MSM_USB30_QSCRATCH_BASE 0x6AF8800 |
| 67 | /* SS QMP (Qulacomm Multi Protocol) */ |
| 68 | #define QMP_PHY_BASE 0x7410000 |
| 69 | |
| 70 | /* QUSB2 PHY */ |
| 71 | #define QUSB2_PHY_BASE 0x7411000 |
| 72 | #define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4) |
| 73 | #define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038) |
| 74 | #define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4) |
| 75 | #define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080) |
| 76 | #define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084) |
| 77 | #define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088) |
| 78 | #define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C) |
| 79 | |
| 80 | /* Clocks */ |
| 81 | #define CLK_CTL_BASE 0x300000 |
| 82 | |
| 83 | /* GPLL */ |
| 84 | #define GPLL0_MODE (CLK_CTL_BASE + 0x0000) |
| 85 | #define GPLL4_MODE (CLK_CTL_BASE + 0x77000) |
| 86 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000) |
| 87 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004) |
| 88 | |
| 89 | /* UART Clocks */ |
| Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame^] | 90 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x29004) |
| 91 | #define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29008) |
| 92 | #define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C) |
| 93 | #define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010) |
| 94 | #define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014) |
| 95 | #define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018) |
| 96 | #define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C) |
| Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 97 | |
| 98 | /* USB3 clocks */ |
| 99 | #define USB_30_BCR (CLK_CTL_BASE + 0xF000) |
| 100 | #define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008) |
| 101 | #define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014) |
| 102 | #define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018) |
| 103 | #define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C) |
| 104 | #define USB30_MASTER_N (CLK_CTL_BASE + 0xF020) |
| 105 | #define USB30_MASTER_D (CLK_CTL_BASE + 0xF024) |
| 106 | #define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C) |
| 107 | |
| 108 | #define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF014) |
| 109 | #define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF018) |
| 110 | #define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010) |
| 111 | #define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C) |
| 112 | #define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C) |
| 113 | #define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010) |
| 114 | #define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000) |
| 115 | #define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004) |
| 116 | #define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020) |
| 117 | #define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024) |
| 118 | #define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004) |
| 119 | #define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004) |
| 120 | |
| 121 | /* SDCC */ |
| 122 | #define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */ |
| 123 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */ |
| 124 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008) |
| 125 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */ |
| 126 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */ |
| 127 | #define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */ |
| 128 | #define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */ |
| 129 | #define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */ |
| 130 | |
| 131 | /* SDCC2 */ |
| 132 | #define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */ |
| 133 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */ |
| 134 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008) |
| 135 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */ |
| 136 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */ |
| 137 | #define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */ |
| 138 | #define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */ |
| 139 | #define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */ |
| 140 | |
| 141 | #define UFS_BASE 0x624000 |
| 142 | |
| 143 | #define SPMI_BASE 0x4000000 |
| 144 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 145 | #define SPMI_PIC_BASE (SPMI_BASE + 0x1800000) |
| Channagoud Kadabi | 7b20dea | 2014-11-11 13:27:33 -0800 | [diff] [blame] | 146 | #define PMIC_ARB_CORE 0x400F000 |
| Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 147 | |
| 148 | #define MSM_CE_BAM_BASE 0x67A000 |
| 149 | #define MSM_CE_BASE 0x644000 |
| 150 | |
| 151 | #define TLMM_BASE_ADDR 0x1010000 |
| 152 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000) |
| 153 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000) |
| 154 | |
| 155 | #define MPM2_MPM_CTRL_BASE 0x4A1000 |
| 156 | #define MPM2_MPM_PS_HOLD 0x4AB000 |
| 157 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000 |
| 158 | |
| 159 | /* DRV strength for sdcc */ |
| 160 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000) |
| 161 | |
| 162 | /* SDHCI - power control registers */ |
| 163 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 164 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 165 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 166 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 167 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
| 168 | |
| 169 | /* Boot config */ |
| 170 | #define SEC_CTRL_CORE_BASE 0x70000 |
| 171 | #define BOOT_CONFIG_OFFSET 0x00006044 |
| 172 | #define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET) |
| 173 | |
| 174 | /* Fix This */ |
| 175 | #define PLATFORM_QMP_OFFSET 0x8 |
| 176 | |
| 177 | #endif |