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gerrit-public.fairphone.software / kernel / lk / 36cd703c4640f8998ff37d2821dc394bd29670f3 / . / platform / qsd8k / panel.c
blob: a5e77525f041d1a843d71ccdeaa2e92b55778a6c [file] [log] [blame]
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]1/* Copyright 2007, Google Inc. */
2
3#include <debug.h>
4#include <dev/gpio.h>
5#include <kernel/thread.h>
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]6#include <mddi.h>
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]7
8#define MDDI_CLIENT_CORE_BASE 0x108000
9#define LCD_CONTROL_BLOCK_BASE 0x110000
10#define SPI_BLOCK_BASE 0x120000
11#define I2C_BLOCK_BASE 0x130000
12#define PWM_BLOCK_BASE 0x140000
13#define GPIO_BLOCK_BASE 0x150000
14#define SYSTEM_BLOCK1_BASE 0x160000
15#define SYSTEM_BLOCK2_BASE 0x170000
16
17
18#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
19#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
20#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
21#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
22#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
23#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
24#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
25#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
26#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
27#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
28#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
29#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
30#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
31#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
32#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
33#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
34#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
35#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
36#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
37#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
38#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
39#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
40
41
42#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
43#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
44#define START (LCD_CONTROL_BLOCK_BASE|0x08)
45#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
46#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
47#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
48#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
49#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
50#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
51#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
52#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
53
54#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
55#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
56#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
57#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
58#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
59#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
60#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
61#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
62#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
63#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
64#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
65#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
66#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
67#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
68#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
69#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
70#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
71#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
72#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
73#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
74#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
75#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
76#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
77#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
78
79#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
80
81#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
82#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
83#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
84
85
86#define SSICTL (SPI_BLOCK_BASE|0x00)
87#define SSITIME (SPI_BLOCK_BASE|0x04)
88#define SSITX (SPI_BLOCK_BASE|0x08)
89#define SSIRX (SPI_BLOCK_BASE|0x0C)
90#define SSIINTC (SPI_BLOCK_BASE|0x10)
91#define SSIINTS (SPI_BLOCK_BASE|0x14)
92#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
93#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
94#define SSIID (SPI_BLOCK_BASE|0x20)
95
96
97#define I2CSETUP (I2C_BLOCK_BASE|0x00)
98#define I2CCTRL (I2C_BLOCK_BASE|0x04)
99
100
101#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
102#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
103#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
104#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
105#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
106#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
107#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
108#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
109#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
110#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
111#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
112#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
113#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
114#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
115#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
116#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
117#define TIMERITCR (PWM_BLOCK_BASE|0x60)
118#define TIMERITOP (PWM_BLOCK_BASE|0x64)
119#define PWMCR (PWM_BLOCK_BASE|0x68)
120#define PWMID (PWM_BLOCK_BASE|0x6C)
121#define PWMMON (PWM_BLOCK_BASE|0x70)
122
123
124#define GPIODATA (GPIO_BLOCK_BASE|0x00)
125#define GPIODIR (GPIO_BLOCK_BASE|0x04)
126#define GPIOIS (GPIO_BLOCK_BASE|0x08)
127#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
128#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
129#define GPIOIE (GPIO_BLOCK_BASE|0x14)
130#define GPIORIS (GPIO_BLOCK_BASE|0x18)
131#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
132#define GPIOIC (GPIO_BLOCK_BASE|0x20)
133#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
134#define GPIOPC (GPIO_BLOCK_BASE|0x28)
135
136#define GPIOID (GPIO_BLOCK_BASE|0x30)
137
138
139#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
140#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
141#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]142#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]143#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
144#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
145
146struct init_table {
147 unsigned int reg;
148 unsigned int val;
149};
150
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]151static struct init_table toshiba_480x800_init_table[] = {
152 { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
153 { DPSET1, 0x00000113 }, // # MDC.DPSET1
154 { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
155 { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
156 { 0, 15 }, // wait_ms(15);
157 { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
158 { CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
159
160 { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
161 { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
162 { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
163 { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
164 { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
165 { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
166 { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
167 { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
168 { GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
169 { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
170 { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
171 { CLKENB, 0x0000A0EB }, // # enable eDRAM clock
172
173 { PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
174 { 0, 1 }, // wait_ms(1);
175 { SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
176 { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
177 { CNT_DIS, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
178 { SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
179
180 { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
181 { 0, 2 }, // wait_ms(2);
182 { SSITX, 0x00000000 }, // # SPI.SSITX
183 { 0, 2 }, // wait_ms(2);
184 { SSITX, 0x00000000 }, // # SPI.SSITX
185 { 0, 2 }, // wait_ms(2);
186
187 { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
188 { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
189 { SSITX, 0x00080036 }, // # Command setting of SPI block
190 { SSITX, 0x00000100 }, // # Memory access control
191 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
192 { SSITX, 0x0008003A }, // # Command setting of SPI block
193 { SSITX, 0x00000160 }, // # Display mode setup(2)
194 { SSITX, 0x000800B1 }, // # Command setting of SPI block
195 { SSITX, 0x0000015D }, // # RGB Interface data format
196 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
197 { SSITX, 0x000800B2 }, // # Command setting of SPI block
198 { SSITX, 0x00000133 }, // # Drivnig method
199 { SSITX, 0x000800B3 }, // # Command setting of SPI block
200 { SSITX, 0x00000122 }, // # Booster operation setup
201 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
202 { SSITX, 0x000800B4 }, // # Command setting of SPI block
203 { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
204 { SSITX, 0x000800B5 }, // # Command setting of SPI block
205 { SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
206 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
207 { SSITX, 0x000800B6 }, // # Command setting of SPI block
208 { SSITX, 0x00000127 }, // # VCOM Voltage adjustment
209 { SSITX, 0x000800B7 }, // # Command setting of SPI block
210 { SSITX, 0x00000103 }, // # Configure an external display signal
211 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
212 { SSITX, 0x000800B9 }, // # Command setting of SPI block
213 { SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
214 { SSITX, 0x000800BD }, // # Command setting of SPI block
215 { SSITX, 0x000001A1 }, // # ASW signal control
216 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
217 { SSITX, 0x000800BB }, // # Command setting of SPI block
218 { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
219 { SSITX, 0x000800BF }, // # Command setting of SPI block
220 { SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
221 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
222 { SSITX, 0x000800BE }, // # Command setting of SPI block
223 { SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
224 { SSITX, 0x000800C0 }, // # Command setting of SPI block
225 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
226 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
227 { SSITX, 0x000800C1 }, // # Command setting of SPI block
228 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
229 { SSITX, 0x000800C2 }, // # Command setting of SPI block
230 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
231 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
232 { SSITX, 0x000800C3 }, // # Command setting of SPI block
233 { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
234 { SSITX, 0x00000132 }, //
235 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
236 { SSITX, 0x000800C4 }, // # Command setting of SPI block
237 { SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
238 { SSITX, 0x00000132 }, //
239 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
240 { SSITX, 0x000800C5 }, // # Command setting of SPI block
241 { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
242 { SSITX, 0x00000132 }, //
243 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
244 { SSITX, 0x000800C6 }, // # Command setting of SPI block
245 { SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
246 { SSITX, 0x00000132 }, //
247 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
248 { SSITX, 0x000800C7 }, // # Command setting of SPI block
249 { SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
250 { SSITX, 0x00000145 }, //
251 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
252 { SSITX, 0x000800C8 }, // # Command setting of SPI block
253 { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
254 { SSITX, 0x000800C9 }, // # Command setting of SPI block
255 { SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
256 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
257 { SSITX, 0x000800CA }, // # Command setting of SPI block
258 { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
259 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
260 { SSITX, 0x000800EC }, // # Command setting of SPI block
261 { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
262 { SSITX, 0x000001FC }, //
263 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
264 { SSITX, 0x000800CF }, // # Command setting of SPI block
265 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
266 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
267 { SSITX, 0x000800D0 }, // # Command setting of SPI block
268 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
269 { SSITX, 0x00000104 }, //
270 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
271 { SSITX, 0x000800D1 }, // # Command setting of SPI block
272 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
273 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
274 { SSITX, 0x000800D2 }, // # Command setting of SPI block
275 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
276 { SSITX, 0x00000128 }, //
277 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
278 { SSITX, 0x000800D3 }, // # Command setting of SPI block
279 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
280 { SSITX, 0x00000128 }, //
281 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
282 { SSITX, 0x000800D4 }, // # Command setting of SPI block
283 { SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
284 { SSITX, 0x000001A4 }, //
285 { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
286 { SSITX, 0x000800D5 }, // # Command setting of SPI block
287 { SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
288 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
289 { SSITX, 0x000800EF }, // # Command setting of SPI block
290 { SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
291 { SSITX, 0x00000100 }, //
292 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
293
294 { BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
295 { BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
296 { BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
297 { BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
298 { BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
299 { CLKENB, 0x0000A1EB }, // SYS.CLKENB ); // DCLK supply
300 { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
301 { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
302 { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
303 { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
304 { HCYCLE, 0x000000FD }, // LCD.HCYCLE ); // Setup to VGA size
305 { HSW, 0x00000003 }, // LCD.HSW
306 { HDE_START, 0x00000007 }, // LCD.HDE_START
307 { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
308 { VCYCLE, 0x00000325 }, // LCD.VCYCLE
309 { VSW, 0x00000001 }, // LCD.VSW
310 { VDE_START, 0x00000003 }, // LCD.VDE_START
311 { VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
312
313 { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
314
315 { 0, 10 }, // wait_ms( 10 );
316 { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
317 { SSITX, 0x00000180 }, // Display data setup
318 { SSITX, 0x0008003B }, // Command setting of SPI block
319 { SSITX, 0x00000100 }, // Quad Data configuration - VGA
320 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
321 { SSITX, 0x000800B0 }, // Command setting of SPI block
322 { SSITX, 0x00000116 }, // Power supply ON/OFF control
323 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
324 { SSITX, 0x000800B8 }, // Command setting of SPI block
325 { SSITX, 0x000801FF }, // Output control
326 { SSITX, 0x000001F5 },
327 { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
328 { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
329 { SSITX, 0x00000029 }, // Display on (Command only)
330
331 //{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
332
333 { 0, 0 }
334};
335
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]336static struct init_table toshiba_480x640_init_table[] = {
337 { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]338 { DPSET1, 0x00000113 }, // # MDC.DPSET1
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]339 { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
340 { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
341 { 0, 14 }, // wait_ms(14);
342 { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
343 { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
344 { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
345 { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
346 { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
347 { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
348 { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
349 { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
350 { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
351 { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
352 { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
353 { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
354 { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
355 { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
356 { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
357 { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]358 //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]359#if 0
360 { PWM0OFF, 0x00001387 }, // SURF 100% backlight
361 { PWM0OFF, 0x00000000 }, // FFA 100% backlight
362#endif
363 { PWM0OFF, 0x000009C3 }, // 50% BL
364 { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
365 { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]366 //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]367 { PWM1OFF, 0x00001387 },
368 { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
369 { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
370 { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]371 { 0, 1 }, // wait_ms(1);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]372 { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
373 { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
374 { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
375
376 { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
377 { 0, 1 }, // wait_ms(1);
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]378 { SSITX, 0x00000000 }, // # SPI.SSITX
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]379 { 0, 1 }, // wait_ms(1);
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]380 { SSITX, 0x00000000 }, // # SPI.SSITX
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]381 { 0, 1 }, // wait_ms(1);
382 { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
383 { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
384 { SSITX, 0x00080036 }, // # Command setting of SPI block
385 { SSITX, 0x00000100 }, // # Memory access control
386 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
387 { SSITX, 0x000800BB }, // # Command setting of SPI block
388 { SSITX, 0x00000100 }, // # Display mode setup(2)
389 { SSITX, 0x0008003A }, // # Command setting of SPI block
390 { SSITX, 0x00000160 }, // # RGB Interface data format
391 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
392 { SSITX, 0x000800BF }, // # Command setting of SPI block
393 { SSITX, 0x00000100 }, // # Drivnig method
394 { SSITX, 0x000800B1 }, // # Command setting of SPI block
395 { SSITX, 0x0000015D }, // # Booster operation setup
396 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
397 { SSITX, 0x000800B2 }, // # Command setting of SPI block
398 { SSITX, 0x00000133 }, // # Booster mode setup
399 { SSITX, 0x000800B3 }, // # Command setting of SPI block
400 { SSITX, 0x00000122 }, // # Booster frequencies setup
401 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
402 { SSITX, 0x000800B4 }, // # Command setting of SPI block
403 { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
404 { SSITX, 0x000800B5 }, // # Command setting of SPI block
405 { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
406 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
407 { SSITX, 0x000800B6 }, // # Command setting of SPI block
408 { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
409 { SSITX, 0x000800B7 }, // # Command setting of SPI block
410 { SSITX, 0x00000103 }, // # Configure an external display signal
411 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
412 { SSITX, 0x000800B9 }, // # Command setting of SPI block
413 { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
414 { SSITX, 0x000800BD }, // # Command setting of SPI block
415 { SSITX, 0x00000102 }, // # ASW signal control
416 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
417 { SSITX, 0x000800BE }, // # Command setting of SPI block
418 { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
419 { SSITX, 0x000800C0 }, // # Command setting of SPI block
420 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
421 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
422 { SSITX, 0x000800C1 }, // # Command setting of SPI block
423 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
424 { SSITX, 0x000800C2 }, // # Command setting of SPI block
425 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
426 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
427 { SSITX, 0x000800C3 }, // # Command setting of SPI block
428 { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]429 { SSITX, 0x0000010A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]430 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
431 { SSITX, 0x000800C4 }, // # Command setting of SPI block
432 { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]433 { SSITX, 0x00000160 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]434 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
435 { SSITX, 0x000800C5 }, // # Command setting of SPI block
436 { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]437 { SSITX, 0x00000160 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]438 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
439 { SSITX, 0x000800C6 }, // # Command setting of SPI block
440 { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]441 { SSITX, 0x00000160 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]442 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
443 { SSITX, 0x000800C7 }, // # Command setting of SPI block
444 { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]445 { SSITX, 0x00000143 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]446 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
447 { SSITX, 0x000800C8 }, // # Command setting of SPI block
448 { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
449 { SSITX, 0x000800C9 }, // # Command setting of SPI block
450 { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
451 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
452 { SSITX, 0x000800CA }, // # Command setting of SPI block
453 { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
454 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
455 { SSITX, 0x000800EC }, // # Command setting of SPI block
456 { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]457 { SSITX, 0x00000118 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]458 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
459 { SSITX, 0x000800CF }, // # Command setting of SPI block
460 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
461 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
462 { SSITX, 0x000800D0 }, // # Command setting of SPI block
463 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]464 { SSITX, 0x00000104 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]465 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
466 { SSITX, 0x000800D1 }, // # Command setting of SPI block
467 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
468 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
469 { SSITX, 0x000800D2 }, // # Command setting of SPI block
470 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]471 { SSITX, 0x0000013A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]472 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
473 { SSITX, 0x000800D3 }, // # Command setting of SPI block
474 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]475 { SSITX, 0x0000013A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]476 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
477 { SSITX, 0x000800D4 }, // # Command setting of SPI block
478 { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]479 { SSITX, 0x0000016E }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]480 { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
481 { SSITX, 0x000800D5 }, // # Command setting of SPI block
482 { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
483 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
484 { SSITX, 0x000800ED }, // # Command setting of SPI block
485 { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]486 { SSITX, 0x0000010A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]487 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
488 { SSITX, 0x000800D6 }, // # Command setting of SPI block
489 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
490 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
491 { SSITX, 0x000800D7 }, // # Command setting of SPI block
492 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]493 { SSITX, 0x0000010A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]494 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
495 { SSITX, 0x000800D8 }, // # Command setting of SPI block
496 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
497 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
498 { SSITX, 0x000800D9 }, // # Command setting of SPI block
499 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]500 { SSITX, 0x00000114 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]501 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
502 { SSITX, 0x000800DE }, // # Command setting of SPI block
503 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]504 { SSITX, 0x00000114 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]505 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
506 { SSITX, 0x000800DF }, // # Command setting of SPI block
507 { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]508 { SSITX, 0x0000013F }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]509 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
510 { SSITX, 0x000800E0 }, // # Command setting of SPI block
511 { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
512 { SSITX, 0x000800E2 }, // # Command setting of SPI block
513 { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
514 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
515 { SSITX, 0x000800E3 }, // # Command setting of SPI block
516 { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
517 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
518 { SSITX, 0x000800E4 }, // # Command setting of SPI block
519 { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]520 { SSITX, 0x00000103 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]521 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
522 { SSITX, 0x000800E5 }, // # Command setting of SPI block
523 { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]524 { SSITX, 0x00000104 }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]525 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
526 { SSITX, 0x000800E6 }, // # Command setting of SPI block
527 { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
528 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
529 { SSITX, 0x000800E7 }, // # Command setting of SPI block
530 { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]531 { SSITX, 0x0000010A }, //
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]532 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
533 { SSITX, 0x000800E8 }, // # Command setting of SPI block
534 { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]535
536
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]537 { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
538 { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
539 { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
540 { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
541 { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
542 { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
543 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
544 { ASY_DATB, 0x00000001 }, // # Oscillator start
545 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
546 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
547 { 0, 10 }, // wait_ms(10);
548 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]549 { ASY_DATB, 0x80000000 }, //
550 { ASY_DATC, 0x80000000 }, //
551 { ASY_DATD, 0x80000000 }, //
552 { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
553 { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]554 { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
555 { ASY_DATB, 0x00004005 }, // # LCD driver control
556 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
557 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
558 { 0, 20 }, // wait_ms(20);
559 { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
560 { ASY_DATB, 0x00000000 }, // # LTPS I/F control
561 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
562 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
563
564 { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
565 { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
566
567 /******************************/
568
569 { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
570 { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
571
572 { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
573 { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
574 { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
575 { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
576 { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
577 { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
578 { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
579 { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
580 { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
581 { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
582 { HSW, 0x00000003 }, // LCD.HSW
583 { HDE_START, 0x00000007 }, // LCD.HDE_START
584 { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
585 { VCYCLE, 0x00000285 }, // LCD.VCYCLE
586 { VSW, 0x00000001 }, // LCD.VSW
587 { VDE_START, 0x00000003 }, // LCD.VDE_START
588 { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
589
590 { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
591
592 { 0, 10 }, // wait_ms( 10 );
593 { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
594 { SSITX, 0x00000180 }, // Display data setup
595 { SSITX, 0x0008003B }, // Command setting of SPI block
596 { SSITX, 0x00000100 }, // Quad Data configuration - VGA
597 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
598 { SSITX, 0x000800B0 }, // Command setting of SPI block
599 { SSITX, 0x00000116 }, // Power supply ON/OFF control
600 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
601 { SSITX, 0x000800B8 }, // Command setting of SPI block
602 { SSITX, 0x000801FF }, // Output control
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]603 { SSITX, 0x000001F5 },
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]604 { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
605 { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
606 { SSITX, 0x00000029 }, // Display on (Command only)
607
608 { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
609
610 { 0, 0 }
611};
612
613static void _panel_init(struct init_table *init_table)
614{
615 unsigned n;
616
617 dprintf(INFO, "panel_init()\n");
618
619 n = 0;
620 while (init_table[n].reg != 0 || init_table[n].val != 0) {
621 if (init_table[n].reg != 0)
622 mddi_remote_write(init_table[n].val, init_table[n].reg);
623 else
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700[diff] [blame]624 mdelay(init_table[n].val);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]625 n++;
626 }
627
628 dprintf(INFO, "panel_init() done\n");
629}
630
631void panel_init(struct mddi_client_caps *client_caps)
632{
633 switch(client_caps->manufacturer_name) {
634 case 0xd263: // Toshiba
635 dprintf(INFO, "Found Toshiba panel\n");
Chandan Uddaraju2943fd62010-06-21 10:56:39 -0700[diff] [blame]636 _panel_init(toshiba_480x800_init_table);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]637 break;
638 case 0x4474: //??
639 if (client_caps->product_code == 0xc065)
640 dprintf(INFO, "Found WVGA panel\n");
641 break;
642 }
643}
644
645void panel_poweron(void)
646{
647 gpio_set(88, 0);
648 gpio_config(88, GPIO_OUTPUT);
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700[diff] [blame]649 udelay(10);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]650 gpio_set(88, 1);
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700[diff] [blame]651 mdelay(10);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800[diff] [blame]652
653 //mdelay(1000); // uncomment for second stage boot
654}
655
656void panel_backlight(int on)
657{}