Ajay Singh Parmar | 380200a | 2014-07-23 23:12:25 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <err.h> |
| 32 | #include <reg.h> |
| 33 | #include <smem.h> |
| 34 | #include <bits.h> |
| 35 | #include <msm_panel.h> |
| 36 | #include <platform/timer.h> |
| 37 | #include <platform/iomap.h> |
| 38 | |
| 39 | #define HDMI_PHY_BASE 0xFD922500 |
| 40 | #define HDMI_PLL_BASE 0xFD922700 |
| 41 | |
| 42 | /* hdmi phy registers */ |
| 43 | #define HDMI_PHY_ANA_CFG0 (0x0000) |
| 44 | #define HDMI_PHY_ANA_CFG1 (0x0004) |
| 45 | #define HDMI_PHY_ANA_CFG2 (0x0008) |
| 46 | #define HDMI_PHY_ANA_CFG3 (0x000C) |
| 47 | #define HDMI_PHY_PD_CTRL0 (0x0010) |
| 48 | #define HDMI_PHY_PD_CTRL1 (0x0014) |
| 49 | #define HDMI_PHY_GLB_CFG (0x0018) |
| 50 | #define HDMI_PHY_DCC_CFG0 (0x001C) |
| 51 | #define HDMI_PHY_DCC_CFG1 (0x0020) |
| 52 | #define HDMI_PHY_TXCAL_CFG0 (0x0024) |
| 53 | #define HDMI_PHY_TXCAL_CFG1 (0x0028) |
| 54 | #define HDMI_PHY_TXCAL_CFG2 (0x002C) |
| 55 | #define HDMI_PHY_TXCAL_CFG3 (0x0030) |
| 56 | #define HDMI_PHY_BIST_CFG0 (0x0034) |
| 57 | #define HDMI_PHY_BIST_CFG1 (0x0038) |
| 58 | #define HDMI_PHY_BIST_PATN0 (0x003C) |
| 59 | #define HDMI_PHY_BIST_PATN1 (0x0040) |
| 60 | #define HDMI_PHY_BIST_PATN2 (0x0044) |
| 61 | #define HDMI_PHY_BIST_PATN3 (0x0048) |
| 62 | #define HDMI_PHY_STATUS (0x005C) |
| 63 | |
| 64 | /* hdmi phy unified pll registers */ |
| 65 | #define HDMI_UNI_PLL_REFCLK_CFG (0x0000) |
| 66 | #define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004) |
| 67 | #define HDMI_UNI_PLL_CHFPUMP_CFG (0x0008) |
| 68 | #define HDMI_UNI_PLL_VCOLPF_CFG (0x000C) |
| 69 | #define HDMI_UNI_PLL_VREG_CFG (0x0010) |
| 70 | #define HDMI_UNI_PLL_PWRGEN_CFG (0x0014) |
| 71 | #define HDMI_UNI_PLL_GLB_CFG (0x0020) |
| 72 | #define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024) |
| 73 | #define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028) |
| 74 | #define HDMI_UNI_PLL_LPFR_CFG (0x002C) |
| 75 | #define HDMI_UNI_PLL_LPFC1_CFG (0x0030) |
| 76 | #define HDMI_UNI_PLL_LPFC2_CFG (0x0034) |
| 77 | #define HDMI_UNI_PLL_SDM_CFG0 (0x0038) |
| 78 | #define HDMI_UNI_PLL_SDM_CFG1 (0x003C) |
| 79 | #define HDMI_UNI_PLL_SDM_CFG2 (0x0040) |
| 80 | #define HDMI_UNI_PLL_SDM_CFG3 (0x0044) |
| 81 | #define HDMI_UNI_PLL_SDM_CFG4 (0x0048) |
| 82 | #define HDMI_UNI_PLL_SSC_CFG0 (0x004C) |
| 83 | #define HDMI_UNI_PLL_SSC_CFG1 (0x0050) |
| 84 | #define HDMI_UNI_PLL_SSC_CFG2 (0x0054) |
| 85 | #define HDMI_UNI_PLL_SSC_CFG3 (0x0058) |
| 86 | #define HDMI_UNI_PLL_LKDET_CFG0 (0x005C) |
| 87 | #define HDMI_UNI_PLL_LKDET_CFG1 (0x0060) |
| 88 | #define HDMI_UNI_PLL_LKDET_CFG2 (0x0064) |
| 89 | #define HDMI_UNI_PLL_CAL_CFG0 (0x006C) |
| 90 | #define HDMI_UNI_PLL_CAL_CFG1 (0x0070) |
| 91 | #define HDMI_UNI_PLL_CAL_CFG2 (0x0074) |
| 92 | #define HDMI_UNI_PLL_CAL_CFG3 (0x0078) |
| 93 | #define HDMI_UNI_PLL_CAL_CFG4 (0x007C) |
| 94 | #define HDMI_UNI_PLL_CAL_CFG5 (0x0080) |
| 95 | #define HDMI_UNI_PLL_CAL_CFG6 (0x0084) |
| 96 | #define HDMI_UNI_PLL_CAL_CFG7 (0x0088) |
| 97 | #define HDMI_UNI_PLL_CAL_CFG8 (0x008C) |
| 98 | #define HDMI_UNI_PLL_CAL_CFG9 (0x0090) |
| 99 | #define HDMI_UNI_PLL_CAL_CFG10 (0x0094) |
| 100 | #define HDMI_UNI_PLL_CAL_CFG11 (0x0098) |
| 101 | #define HDMI_UNI_PLL_STATUS (0x00C0) |
| 102 | |
| 103 | #define SW_RESET BIT(2) |
| 104 | #define SW_RESET_PLL BIT(0) |
| 105 | |
| 106 | void hdmi_phy_reset(void) |
| 107 | { |
| 108 | uint32_t phy_reset_polarity = 0x0; |
| 109 | uint32_t pll_reset_polarity = 0x0; |
| 110 | uint32_t val; |
| 111 | |
| 112 | val = readl(HDMI_PHY_CTRL); |
| 113 | |
| 114 | phy_reset_polarity = val >> 3 & 0x1; |
| 115 | pll_reset_polarity = val >> 1 & 0x1; |
| 116 | |
| 117 | if (phy_reset_polarity == 0) |
| 118 | writel(val | SW_RESET, HDMI_PHY_CTRL); |
| 119 | else |
| 120 | writel(val & (~SW_RESET), HDMI_PHY_CTRL); |
| 121 | |
| 122 | if (pll_reset_polarity == 0) |
| 123 | writel(val | SW_RESET_PLL, HDMI_PHY_CTRL); |
| 124 | else |
| 125 | writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL); |
| 126 | |
| 127 | if (phy_reset_polarity == 0) |
| 128 | writel(val & (~SW_RESET), HDMI_PHY_CTRL); |
| 129 | else |
| 130 | writel(val | SW_RESET, HDMI_PHY_CTRL); |
| 131 | |
| 132 | if (pll_reset_polarity == 0) |
| 133 | writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL); |
| 134 | else |
| 135 | writel(val | SW_RESET_PLL, HDMI_PHY_CTRL); |
| 136 | } |
| 137 | |
| 138 | void hdmi_phy_init(void) |
| 139 | { |
| 140 | writel(0x1B, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0); |
| 141 | writel(0xF2, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1); |
| 142 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_CFG0); |
| 143 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN0); |
| 144 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN1); |
| 145 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN2); |
| 146 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_BIST_PATN3); |
| 147 | |
| 148 | writel(0x20, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1); |
| 149 | } |
| 150 | |
| 151 | void hdmi_phy_powerdown(void) |
| 152 | { |
| 153 | writel(0x7F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0); |
| 154 | } |
| 155 | |
| 156 | static uint32_t hdmi_poll_status(uint32_t addr) |
| 157 | { |
| 158 | uint32_t count; |
| 159 | |
| 160 | for (count = 20; count > 0; count--) { |
| 161 | if (readl(addr) & 0x1) { |
| 162 | return NO_ERROR; |
| 163 | } |
| 164 | udelay(100); |
| 165 | } |
| 166 | return ERR_TIMED_OUT; |
| 167 | } |
| 168 | |
| 169 | void hdmi_vco_disable(void) |
| 170 | { |
| 171 | writel(0x0, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 172 | udelay(5); |
| 173 | writel(0x0, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG); |
| 174 | } |
| 175 | |
| 176 | int hdmi_vco_enable(void) |
| 177 | { |
| 178 | /* Global Enable */ |
| 179 | writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG); |
| 180 | /* Power up power gen */ |
| 181 | writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0); |
| 182 | udelay(350); |
| 183 | |
| 184 | /* PLL Power-Up */ |
| 185 | writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 186 | udelay(5); |
| 187 | |
| 188 | /* Power up PLL LDO */ |
| 189 | writel(0x03, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 190 | udelay(350); |
| 191 | |
| 192 | /* PLL Power-Up */ |
| 193 | writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 194 | udelay(350); |
| 195 | |
| 196 | /* poll for PLL ready status */ |
| 197 | if (hdmi_poll_status(HDMI_PLL_BASE + HDMI_UNI_PLL_STATUS)) { |
| 198 | dprintf(CRITICAL, "%s: hdmi phy pll failed to Lock\n", |
| 199 | __func__); |
| 200 | hdmi_vco_disable(); |
| 201 | return ERROR; |
| 202 | } |
| 203 | |
| 204 | udelay(350); |
| 205 | /* poll for PHY ready status */ |
| 206 | if (hdmi_poll_status(HDMI_PHY_BASE + HDMI_PHY_STATUS)) { |
| 207 | dprintf(CRITICAL, "%s: hdmi phy failed to Lock\n", |
| 208 | __func__); |
| 209 | hdmi_vco_disable(); |
| 210 | return ERROR; |
| 211 | } |
| 212 | |
| 213 | return NO_ERROR; |
| 214 | } |
| 215 | |
| 216 | uint32_t hdmi_pll_config(void) |
| 217 | { |
| 218 | writel(0x81, HDMI_PHY_BASE + HDMI_PHY_GLB_CFG); |
| 219 | writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 220 | writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_REFCLK_CFG); |
| 221 | writel(0x19, HDMI_PLL_BASE + HDMI_UNI_PLL_VCOLPF_CFG); |
| 222 | writel(0x0E, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFR_CFG); |
| 223 | writel(0x20, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC1_CFG); |
| 224 | writel(0x0D, HDMI_PLL_BASE + HDMI_UNI_PLL_LPFC2_CFG); |
| 225 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG0); |
| 226 | writel(0x52, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG1); |
| 227 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG2); |
| 228 | writel(0x56, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG3); |
| 229 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_SDM_CFG4); |
| 230 | writel(0x10, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG0); |
| 231 | writel(0x1A, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG1); |
| 232 | writel(0x05, HDMI_PLL_BASE + HDMI_UNI_PLL_LKDET_CFG2); |
| 233 | writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV1_CFG); |
| 234 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV2_CFG); |
| 235 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_POSTDIV3_CFG); |
| 236 | writel(0x01, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG2); |
| 237 | writel(0x60, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG8); |
| 238 | writel(0x00, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG9); |
| 239 | writel(0xE6, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG10); |
| 240 | writel(0x02, HDMI_PLL_BASE + HDMI_UNI_PLL_CAL_CFG11); |
| 241 | writel(0x1F, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL0); |
| 242 | udelay(50); |
| 243 | |
| 244 | writel(0x0F, HDMI_PLL_BASE + HDMI_UNI_PLL_GLB_CFG); |
| 245 | writel(0x00, HDMI_PHY_BASE + HDMI_PHY_PD_CTRL1); |
| 246 | writel(0x10, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2); |
| 247 | writel(0xDB, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG0); |
| 248 | writel(0x43, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG1); |
| 249 | writel(0x02, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG2); |
| 250 | writel(0x00, HDMI_PHY_BASE + HDMI_PHY_ANA_CFG3); |
| 251 | writel(0x04, HDMI_PLL_BASE + HDMI_UNI_PLL_VREG_CFG); |
| 252 | writel(0xD0, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG0); |
| 253 | writel(0x1A, HDMI_PHY_BASE + HDMI_PHY_DCC_CFG1); |
| 254 | writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG0); |
| 255 | writel(0x00, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG1); |
| 256 | writel(0x02, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG2); |
| 257 | writel(0x05, HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG3); |
| 258 | udelay(200); |
| 259 | } |
| 260 | |