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Shashank Mittal246f8d02011-01-21 17:12:27 -08001/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <reg.h>
31#include <platform/iomap.h>
32#include <dev/gpio.h>
33
34#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
35#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
36
37/* output value */
38#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
39#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
40#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
41#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
42#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
Shashank Mittal39763072011-04-08 17:45:50 -070043#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 132-107 */
Shashank Mittal246f8d02011-01-21 17:12:27 -080044
45/* same pin map as above, output enable */
46#define GPIO_OE_0 GPIO1_REG(0x10)
47#define GPIO_OE_1 GPIO2_REG(0x08)
48#define GPIO_OE_2 GPIO1_REG(0x14)
49#define GPIO_OE_3 GPIO1_REG(0x18)
50#define GPIO_OE_4 GPIO1_REG(0x1C)
Shashank Mittal39763072011-04-08 17:45:50 -070051#define GPIO_OE_5 GPIO1_REG(0x54)
Shashank Mittal246f8d02011-01-21 17:12:27 -080052
53/* same pin map as above, input read */
54#define GPIO_IN_0 GPIO1_REG(0x34)
55#define GPIO_IN_1 GPIO2_REG(0x20)
56#define GPIO_IN_2 GPIO1_REG(0x38)
57#define GPIO_IN_3 GPIO1_REG(0x3C)
58#define GPIO_IN_4 GPIO1_REG(0x40)
Shashank Mittal39763072011-04-08 17:45:50 -070059#define GPIO_IN_5 GPIO1_REG(0x44)
Shashank Mittal246f8d02011-01-21 17:12:27 -080060
61/* same pin map as above, 1=edge 0=level interrup */
62#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
63#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
64#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
65#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
66#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
Shashank Mittal39763072011-04-08 17:45:50 -070067#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0)
Shashank Mittal246f8d02011-01-21 17:12:27 -080068
69/* same pin map as above, 1=positive 0=negative */
70#define GPIO_INT_POS_0 GPIO1_REG(0x70)
71#define GPIO_INT_POS_1 GPIO2_REG(0x58)
72#define GPIO_INT_POS_2 GPIO1_REG(0x74)
73#define GPIO_INT_POS_3 GPIO1_REG(0x78)
74#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
Shashank Mittal39763072011-04-08 17:45:50 -070075#define GPIO_INT_POS_5 GPIO1_REG(0xBC)
Shashank Mittal246f8d02011-01-21 17:12:27 -080076
77/* same pin map as above, interrupt enable */
78#define GPIO_INT_EN_0 GPIO1_REG(0x80)
79#define GPIO_INT_EN_1 GPIO2_REG(0x60)
80#define GPIO_INT_EN_2 GPIO1_REG(0x84)
81#define GPIO_INT_EN_3 GPIO1_REG(0x88)
82#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
Shashank Mittal39763072011-04-08 17:45:50 -070083#define GPIO_INT_EN_5 GPIO1_REG(0xB8)
Shashank Mittal246f8d02011-01-21 17:12:27 -080084
85/* same pin map as above, write 1 to clear interrupt */
86#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
87#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
88#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
89#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
90#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
Shashank Mittal39763072011-04-08 17:45:50 -070091#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4)
Shashank Mittal246f8d02011-01-21 17:12:27 -080092
93/* same pin map as above, 1=interrupt pending */
94#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
95#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
96#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
97#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
98#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
Shashank Mittal39763072011-04-08 17:45:50 -070099#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0)
Shashank Mittal246f8d02011-01-21 17:12:27 -0800100
101typedef struct gpioregs gpioregs;
102
103struct gpioregs
104{
105 unsigned out;
106 unsigned in;
107 unsigned int_status;
108 unsigned int_clear;
109 unsigned int_en;
110 unsigned int_edge;
111 unsigned int_pos;
112 unsigned oe;
113};
114
115static gpioregs GPIO_REGS[] = {
116 {
117 .out = GPIO_OUT_0,
118 .in = GPIO_IN_0,
119 .int_status = GPIO_INT_STATUS_0,
120 .int_clear = GPIO_INT_CLEAR_0,
121 .int_en = GPIO_INT_EN_0,
122 .int_edge = GPIO_INT_EDGE_0,
123 .int_pos = GPIO_INT_POS_0,
124 .oe = GPIO_OE_0,
125 },
126 {
127 .out = GPIO_OUT_1,
128 .in = GPIO_IN_1,
129 .int_status = GPIO_INT_STATUS_1,
130 .int_clear = GPIO_INT_CLEAR_1,
131 .int_en = GPIO_INT_EN_1,
132 .int_edge = GPIO_INT_EDGE_1,
133 .int_pos = GPIO_INT_POS_1,
134 .oe = GPIO_OE_1,
135 },
136 {
137 .out = GPIO_OUT_2,
138 .in = GPIO_IN_2,
139 .int_status = GPIO_INT_STATUS_2,
140 .int_clear = GPIO_INT_CLEAR_2,
141 .int_en = GPIO_INT_EN_2,
142 .int_edge = GPIO_INT_EDGE_2,
143 .int_pos = GPIO_INT_POS_2,
144 .oe = GPIO_OE_2,
145 },
146 {
147 .out = GPIO_OUT_3,
148 .in = GPIO_IN_3,
149 .int_status = GPIO_INT_STATUS_3,
150 .int_clear = GPIO_INT_CLEAR_3,
151 .int_en = GPIO_INT_EN_3,
152 .int_edge = GPIO_INT_EDGE_3,
153 .int_pos = GPIO_INT_POS_3,
154 .oe = GPIO_OE_3,
155 },
156 {
157 .out = GPIO_OUT_4,
158 .in = GPIO_IN_4,
159 .int_status = GPIO_INT_STATUS_4,
160 .int_clear = GPIO_INT_CLEAR_4,
161 .int_en = GPIO_INT_EN_4,
162 .int_edge = GPIO_INT_EDGE_4,
163 .int_pos = GPIO_INT_POS_4,
164 .oe = GPIO_OE_4,
165 },
Shashank Mittal39763072011-04-08 17:45:50 -0700166 {
167 .out = GPIO_OUT_5,
168 .in = GPIO_IN_5,
169 .int_status = GPIO_INT_STATUS_5,
170 .int_clear = GPIO_INT_CLEAR_5,
171 .int_en = GPIO_INT_EN_5,
172 .int_edge = GPIO_INT_EDGE_5,
173 .int_pos = GPIO_INT_POS_5,
174 .oe = GPIO_OE_5,
175 },
Shashank Mittal246f8d02011-01-21 17:12:27 -0800176};
177
178static gpioregs *find_gpio(unsigned n, unsigned *bit)
179{
Shashank Mittal39763072011-04-08 17:45:50 -0700180 if(n > 132)
Shashank Mittal246f8d02011-01-21 17:12:27 -0800181 return 0;
Shashank Mittal39763072011-04-08 17:45:50 -0700182 if(n > 106) {
183 *bit = 1 << (n - 107);
184 return GPIO_REGS + 5;
185 }
Shashank Mittal246f8d02011-01-21 17:12:27 -0800186 if(n > 94) {
187 *bit = 1 << (n - 95);
188 return GPIO_REGS + 4;
189 }
190 if(n > 67) {
191 *bit = 1 << (n - 68);
192 return GPIO_REGS + 3;
193 }
194 if(n > 42) {
195 *bit = 1 << (n - 43);
196 return GPIO_REGS + 2;
197 }
198 if(n > 15) {
199 *bit = 1 << (n - 16);
200 return GPIO_REGS + 1;
201 }
202 *bit = 1 << n;
203 return GPIO_REGS + 0;
204}
205
206int gpio_config(unsigned n, unsigned flags)
207{
208 gpioregs *r;
209 unsigned b;
210 unsigned v;
211
212 if ((r = find_gpio(n, &b)) == 0)
213 return -1;
214
215 v = readl(r->oe);
216 if (flags & GPIO_OUTPUT) {
217 writel(v | b, r->oe);
218 } else {
219 writel(v & (~b), r->oe);
220 }
221 return 0;
222}
223
224void gpio_set(unsigned n, unsigned on)
225{
226 gpioregs *r;
227 unsigned b;
228 unsigned v;
229
230 if((r = find_gpio(n, &b)) == 0)
231 return;
232
233 v = readl(r->out);
234 if(on) {
235 writel(v | b, r->out);
236 } else {
237 writel(v & (~b), r->out);
238 }
239}
240
241int gpio_get(unsigned n)
242{
243 gpioregs *r;
244 unsigned b;
245
246 if((r = find_gpio(n, &b)) == 0) return 0;
247
248 return (readl(r->in) & b) ? 1 : 0;
249}
250