Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 2 | * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions |
| 6 | * are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in |
| 11 | * the documentation and/or other materials provided with the |
| 12 | * distribution. |
| 13 | * * Neither the name of Google, Inc. nor the names of its contributors |
| 14 | * may be used to endorse or promote products derived from this |
| 15 | * software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 20 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 21 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 23 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 24 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 25 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 27 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | */ |
| 30 | .globl SET_SA |
| 31 | SET_SA: |
| 32 | //; routine complete |
| 33 | B _cpu_early_init_complete |
| 34 | .ltorg |
| 35 | |
| 36 | .globl __cpu_early_init |
| 37 | __cpu_early_init: |
| 38 | //; Zero out r0 for use throughout this code. All other GPRs |
| 39 | //; (r1-r3) are set throughout this code to help establish |
| 40 | //; a consistent startup state for any code that follows. |
| 41 | //; Users should add code at the end of this routine to establish |
| 42 | //; their own stack address (r13), add translation page tables, enable |
| 43 | //; the caches, etc. |
| 44 | MOV r0, #0x0 |
| 45 | |
| 46 | |
| 47 | //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA |
| 48 | //; API to dynamically configure cache for slow/nominal/fast parts |
| 49 | |
| 50 | |
| 51 | //; Initialize ASID to zero |
| 52 | MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0 |
| 53 | |
| 54 | //; ICIALL to invalidate entire I-Cache |
| 55 | MCR p15, 0, r0, c7, c5, 0 //; ICIALLU |
| 56 | |
| 57 | //; Initialize ADFSR to zero |
| 58 | MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0 |
| 59 | |
| 60 | //; Ensure the MCR's above have completed their operation before continuing |
| 61 | DSB |
| 62 | ISB |
| 63 | |
| 64 | //;------------------------------------------------------------------- |
| 65 | //; There are a number of registers that must be set prior to enabling |
| 66 | //; the MMU. The DCAR is one of these registers. We are setting |
| 67 | //; it to zero (no access) to easily detect improper setup in subsequent |
| 68 | //; code sequences |
| 69 | //;------------------------------------------------------------------- |
| 70 | //; Setup DACR (Domain Access Control Register) to zero |
| 71 | MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0 |
| 72 | |
| 73 | //;Make sure TLBLKCR is complete before continuing |
| 74 | ISB |
| 75 | |
| 76 | //; Invalidate the UTLB |
| 77 | MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL |
| 78 | |
| 79 | //; Make sure UTLB request has been presented to macro before continuing |
| 80 | ISB |
| 81 | |
| 82 | SYSI2: |
| 83 | //; Enable Z bit to enable branch prediction (default is off) |
| 84 | MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2 |
| 85 | ORR r2, r2, #0x00000800 |
| 86 | MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2 |
| 87 | |
| 88 | //; Make sure Link stack is initialized with branch and links to sequential addresses |
| 89 | //; This aids in creating a predictable startup environment |
| 90 | BL SEQ1 |
| 91 | SEQ1: BL SEQ2 |
| 92 | SEQ2: BL SEQ3 |
| 93 | SEQ3: BL SEQ4 |
| 94 | SEQ4: BL SEQ5 |
| 95 | SEQ5: BL SEQ6 |
| 96 | SEQ6: BL SEQ7 |
| 97 | SEQ7: BL SEQ8 |
| 98 | SEQ8: |
| 99 | |
| 100 | ISB |
| 101 | |
| 102 | //; Initialize the Watchpoint Control Registers to zero (optional) |
| 103 | //;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0 |
| 104 | //;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0 |
| 105 | |
| 106 | |
| 107 | //;---------------------------------------------------------------------- |
| 108 | //; The saved Program Status Registers (SPSRs) should be setup |
| 109 | //; prior to any automatic mode switches. The following |
| 110 | //; code sets these registers up to a known state. Users will need to |
| 111 | //; customize these settings to meet their needs. |
| 112 | //;---------------------------------------------------------------------- |
| 113 | MOV r2, #0x1f |
| 114 | MOV r1, #0xd7 //;ABT mode |
| 115 | msr cpsr_c, r1 //;ABT mode |
| 116 | msr spsr_cxfs, r2 //;clear the spsr |
| 117 | MOV r1, #0xdb //;UND mode |
| 118 | msr cpsr_c, r1 //;UND mode |
| 119 | msr spsr_cxfs, r2 //;clear the spsr |
| 120 | MOV r1, #0xd1 //;FIQ mode |
| 121 | msr cpsr_c, r1 //;FIQ mode |
| 122 | msr spsr_cxfs, r2 //;clear the spsr |
| 123 | MOV r1, #0xd2 //;IRQ mode |
| 124 | msr cpsr_c, r1 //;IRQ mode |
| 125 | msr spsr_cxfs, r2 //;clear the spsr |
| 126 | MOV r1, #0xd6 //;Monitor mode |
| 127 | msr cpsr_c, r1 //;Monitor mode |
| 128 | msr spsr_cxfs, r2 //;clear the spsr |
| 129 | MOV r1, #0xd3 //;SVC mode |
| 130 | msr cpsr_c, r1 //;SVC mode |
| 131 | msr spsr_cxfs, r2 //;clear the spsr |
| 132 | |
| 133 | |
| 134 | //;---------------------------------------------------------------------- |
| 135 | //; Enabling Error reporting is something users may want to do at |
| 136 | //; some other point in time. We have chosen some default settings |
| 137 | //; that should be reviewed. Most of these registers come up in an |
| 138 | //; unpredictable state after reset. |
| 139 | //;---------------------------------------------------------------------- |
| 140 | //;Start of error and control setting |
| 141 | |
| 142 | |
| 143 | //; Set ACTLR (reset unpredictable) |
| 144 | //; Set AVIVT control, error reporting, etc. |
| 145 | //; MOV r3, #0x07 |
| 146 | //; Enable I and D cache parity |
| 147 | //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$) |
| 148 | //;ACTLR[5:4] = 2'h3 - enable parity |
| 149 | //;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled). |
| 150 | //;Value to be written #0xC0037 |
| 151 | // MOVW r3, #0x0037 |
| 152 | //; .word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support |
| 153 | // MOVT r3, #0x000C |
| 154 | //; .word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support |
| 155 | //; MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3 |
| 156 | |
| 157 | //;End of error and control setting |
| 158 | |
| 159 | /* |
| 160 | #ifdef APPSBL_ETM_ENABLE |
| 161 | ;---------------------------------------------------------------------- |
| 162 | ; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug |
| 163 | ;---------------------------------------------------------------------- |
| 164 | |
| 165 | ; enable ETM clock if disabled |
| 166 | MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1 |
| 167 | ORR r1, r1, #0x00000008 |
| 168 | MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1 |
| 169 | ISB |
| 170 | |
| 171 | ; set trigger event to counter1 being zero |
| 172 | MOV r3, #0x00000040 |
| 173 | MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3 |
| 174 | |
| 175 | ; clear ETMSR |
| 176 | MOV r2, #0x00000000 |
| 177 | MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2 |
| 178 | |
| 179 | ; clear trace enable single address comparator usage |
| 180 | MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2 |
| 181 | |
| 182 | ; set trace enable to always |
| 183 | MOV r2, #0x0000006F |
| 184 | MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2 |
| 185 | |
| 186 | ; clear trace enable address range comparator usage and exclude nothing |
| 187 | MOV r2, #0x01000000 |
| 188 | MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2 |
| 189 | |
| 190 | ; set view data to always |
| 191 | MOV r2, #0x0000006F |
| 192 | MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2 |
| 193 | |
| 194 | ; clear view data single address comparator usage |
| 195 | MOV r2, #0x00000000 |
| 196 | MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2 |
| 197 | |
| 198 | ; clear view data address range comparator usage and exclude nothing |
| 199 | MOV r2, #0x00010000 |
| 200 | MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2 |
| 201 | |
| 202 | ; set counter1 to 194 |
| 203 | MOV r2, #0x000000C2 |
| 204 | MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2 |
| 205 | |
| 206 | ; set counter1 to never reload |
| 207 | MOV r2, #0x0000406F |
| 208 | MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2 |
| 209 | |
| 210 | ; set counter1 to decrement every cycle |
| 211 | MOV r2, #0x0000006F |
| 212 | MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2 |
| 213 | |
| 214 | ; Set trace synchronization frequency 1024 bytes |
| 215 | MOV r2, #0x00000400 |
| 216 | MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2 |
| 217 | |
| 218 | ; Program etm control register |
| 219 | ; - Set the CPU to ETM clock ratio to 1:1 |
| 220 | ; - Set the ETM to perform data address tracing |
| 221 | MOV r2, #0x00002008 |
| 222 | MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2 |
| 223 | ISB |
| 224 | #endif *//* APPSBL_ETM_ENABLE */ |
| 225 | |
| 226 | /* |
| 227 | #ifdef APPSBL_VFP_ENABLE |
| 228 | ;---------------------------------------------------------------------- |
| 229 | ; Perform the following operations if you intend to make use of |
| 230 | ; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID |
| 231 | ; indicating the VFP unit is present (i.e.Cortex-A8). . |
| 232 | ; Some tools will require full double precision floating point support |
| 233 | ; which will become available in Scorpion pass 2 |
| 234 | ;---------------------------------------------------------------------- |
| 235 | ; allow full access to CP 10 and 11 space for VFP/NEON use |
| 236 | MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register |
| 237 | ORR r1, r1, #0x00F00000 ; enable full access for p10,11 |
| 238 | MCR p15, 0, r1, c1, c0, 2 ; Write CPACR |
| 239 | |
| 240 | ;make sure the CPACR is complete before continuing |
| 241 | ISB |
| 242 | |
| 243 | ; Enable VFP itself (certain OSes may want to dynamically set/clear |
| 244 | ; the enable bit based on the application being executed |
| 245 | MOV r1, #0x40000000 |
| 246 | FMXR FPEXC, r1 |
| 247 | #endif *//* APPSBL_VFP_ENABLE */ |
| 248 | |
| 249 | /* we have no stack, so just tail-call into the SET_SA routine... */ |
| 250 | |
| 251 | B SET_SA |
| 252 | .ltorg |