Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | /* This file implements the UDC (usb device controller) layer to be used with |
| 30 | * the new dwc controller. |
| 31 | * It exposes APIs to initialize UDC (and thus usb) and perform data transfer |
| 32 | * over usb. |
| 33 | */ |
| 34 | |
| 35 | #include <reg.h> |
| 36 | #include <debug.h> |
| 37 | #include <string.h> |
| 38 | #include <malloc.h> |
| 39 | #include <stdlib.h> |
| 40 | #include <arch/defines.h> |
| 41 | #include <dev/udc.h> |
| 42 | #include <platform/iomap.h> |
| 43 | #include <usb30_dwc.h> |
| 44 | #include <usb30_wrapper.h> |
| 45 | #include <usb30_udc.h> |
| 46 | |
| 47 | //#define DEBUG_USB |
| 48 | |
| 49 | #ifdef DEBUG_USB |
| 50 | #define DBG(...) dprintf(ALWAYS, __VA_ARGS__) |
| 51 | #else |
| 52 | #define DBG(...) |
| 53 | #endif |
| 54 | |
| 55 | #define ERR(...) dprintf(ALWAYS, __VA_ARGS__) |
| 56 | |
| 57 | /* control data transfer is max 512 bytes */ |
| 58 | #define UDC_CONTROL_RX_BUF_SIZE 512 |
| 59 | #define UDC_CONTROL_TX_BUF_SIZE 512 |
| 60 | |
| 61 | /* Buffer used by dwc driver to process events. |
| 62 | * Must be multiple of 4: snps 6.2.7.2. |
| 63 | */ |
| 64 | #define UDC_DWC_EVENT_BUF_SIZE 4096 |
| 65 | |
| 66 | /* macro to parse setup request */ |
| 67 | #define SETUP(type,request) (((type) << 8) | (request)) |
| 68 | |
| 69 | /* macro to generate bit representation of an EP */ |
| 70 | #define EPT_TX(n) (1 << ((n) + 16)) |
| 71 | #define EPT_RX(n) (1 << (n)) |
| 72 | |
| 73 | /* Local functions */ |
| 74 | static struct udc_descriptor *udc_descriptor_alloc(uint32_t type, |
| 75 | uint32_t num, |
| 76 | uint32_t len, |
| 77 | udc_desc_spec_t spec); |
| 78 | static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str); |
| 79 | |
| 80 | static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc); |
| 81 | static void udc_register_language_desc(udc_t *udc); |
| 82 | static void udc_register_bos_desc(udc_t *udc); |
| 83 | static void udc_register_device_desc_usb_20(udc_t *udc, struct udc_device *dev_info); |
| 84 | static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info); |
| 85 | static void udc_register_config_desc_usb20(udc_t *udc, struct udc_gadget *gadget); |
| 86 | static void udc_register_config_desc_usb30(udc_t *udc, struct udc_gadget *gadget); |
| 87 | |
| 88 | static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data); |
| 89 | static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data); |
| 90 | |
| 91 | static void udc_dwc_notify(void *context, dwc_notify_event_t event); |
| 92 | static int udc_handle_setup(void *context, uint8_t *data); |
| 93 | |
| 94 | /* TODO: This must be the only global var in this file, for now. |
| 95 | * Ideally, all APIs should be sending |
| 96 | * this to us and this ptr should be kept outside of this code. |
| 97 | * This needs change in the common udc APIs and thus keeping it here until that |
| 98 | * is done. |
| 99 | */ |
| 100 | static udc_t *udc_dev = NULL; |
| 101 | |
| 102 | |
| 103 | /* TODO: need to find right place for the tcsr functions. */ |
| 104 | |
| 105 | /* UTMI MUX configuration to connect PHY to SNPS controller: |
| 106 | * Configure primary HS phy mux to use UTMI interface |
| 107 | * (connected to usb30 controller). |
| 108 | */ |
| 109 | void tcsr_hs_phy_mux_configure(void) |
| 110 | { |
| 111 | uint32_t reg; |
| 112 | |
| 113 | reg = readl(USB2_PHY_SEL); |
| 114 | |
| 115 | writel(reg | 0x1, USB2_PHY_SEL); |
| 116 | } |
| 117 | |
| 118 | void tcsr_hs_phy_mux_de_configure(void) |
| 119 | { |
| 120 | writel(0x0, USB2_PHY_SEL); |
| 121 | } |
| 122 | |
| 123 | |
| 124 | /* Initialize usb wrapper and dwc h/w blocks. */ |
| 125 | static void usb30_init(void) |
| 126 | { |
| 127 | usb_wrapper_dev_t* wrapper; |
| 128 | usb_wrapper_config_t wrapper_config; |
| 129 | |
| 130 | dwc_dev_t *dwc; |
| 131 | dwc_config_t dwc_config; |
| 132 | |
| 133 | /* initialize the usb wrapper h/w block */ |
| 134 | wrapper_config.qscratch_base = (void*) MSM_USB30_QSCRATCH_BASE; |
| 135 | |
| 136 | wrapper = usb_wrapper_init(&wrapper_config); |
| 137 | ASSERT(wrapper); |
| 138 | |
| 139 | /* save the wrapper ptr */ |
| 140 | udc_dev->wrapper_dev = wrapper; |
| 141 | |
| 142 | /* initialize the dwc device block */ |
| 143 | dwc_config.base = (void*) MSM_USB30_BASE; |
| 144 | |
| 145 | /* buffer must be aligned to buf size. snps 8.2.2 */ |
| 146 | dwc_config.event_buf = memalign(lcm(CACHE_LINE, UDC_DWC_EVENT_BUF_SIZE), |
| 147 | ROUNDUP(UDC_DWC_EVENT_BUF_SIZE, CACHE_LINE)); |
| 148 | ASSERT(dwc_config.event_buf); |
| 149 | |
| 150 | dwc_config.event_buf_size = UDC_DWC_EVENT_BUF_SIZE; |
| 151 | |
| 152 | /* notify handler */ |
| 153 | dwc_config.notify_context = udc_dev; |
| 154 | dwc_config.notify = udc_dwc_notify; |
| 155 | |
| 156 | /* setup handler */ |
| 157 | dwc_config.setup_context = udc_dev; |
| 158 | dwc_config.setup_handler = udc_handle_setup; |
| 159 | |
| 160 | dwc = dwc_init(&dwc_config); |
| 161 | ASSERT(dwc); |
| 162 | |
| 163 | /* save the dwc dev ptr */ |
| 164 | udc_dev->dwc = dwc; |
| 165 | |
| 166 | |
| 167 | /* USB3.0 core and phy initialization as described in HPG */ |
| 168 | |
| 169 | /* section 4.4.1 Control sequence */ |
| 170 | usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS); |
| 171 | |
| 172 | /* section 4.4.1: use config 0 - all of RAM1 */ |
| 173 | usb_wrapper_ram_configure(wrapper); |
| 174 | |
| 175 | /* section 4.4.2: Initialization and configuration sequences */ |
| 176 | |
| 177 | /* 1. UTMI Mux configuration */ |
| 178 | tcsr_hs_phy_mux_configure(); |
| 179 | |
| 180 | /* 2. Put controller in reset */ |
| 181 | dwc_reset(dwc, 1); |
| 182 | |
| 183 | /* PHY reset (steps 3 - 7) must be done while dwc is in reset condition */ |
| 184 | |
| 185 | /* 3. Reset SS PHY */ |
| 186 | usb_wrapper_ss_phy_reset(wrapper); |
| 187 | |
| 188 | /* HS PHY is reset as part of soft reset. No need for explicit reset. */ |
| 189 | |
| 190 | /* 4. SS phy config */ |
| 191 | usb_wrapper_ss_phy_configure(wrapper); |
| 192 | |
| 193 | /* 5. HS phy init */ |
| 194 | usb_wrapper_hs_phy_init(wrapper); |
| 195 | |
| 196 | /* 5.d */ |
| 197 | dwc_usb2_phy_soft_reset(dwc); |
| 198 | |
| 199 | /* 6. hs phy config */ |
| 200 | usb_wrapper_hs_phy_configure(wrapper); |
| 201 | |
| 202 | /* 7. Reset PHY digital interface */ |
| 203 | dwc_phy_digital_reset(dwc); |
| 204 | |
| 205 | /* 8. Bring dwc controller out of reset */ |
| 206 | dwc_reset(dwc, 0); |
| 207 | |
| 208 | /* 9. */ |
| 209 | usb_wrapper_ss_phy_electrical_config(wrapper); |
| 210 | |
| 211 | /* 10. */ |
| 212 | usb_wrapper_workaround_10(wrapper); |
| 213 | |
| 214 | /* 11. */ |
| 215 | usb_wrapper_workaround_11(wrapper); |
| 216 | |
| 217 | /* 12. */ |
| 218 | dwc_ss_phy_workaround_12(dwc); |
| 219 | |
| 220 | /* 13. */ |
| 221 | usb_wrapper_workaround_13(wrapper); |
| 222 | |
| 223 | /* 14. needed only for host mode. ignored. */ |
| 224 | |
| 225 | /* 15 - 20 */ |
| 226 | dwc_device_init(dwc); |
| 227 | } |
| 228 | |
| 229 | /* udc_init: creates and registers various usb descriptor */ |
| 230 | int udc_init(struct udc_device *dev_info) |
| 231 | { |
| 232 | /* create and initialize udc instance */ |
| 233 | udc_dev = (udc_t*) malloc(sizeof(udc_t)); |
| 234 | ASSERT(udc_dev); |
| 235 | |
| 236 | /* initialize everything to 0 */ |
| 237 | memset(udc_dev, 0 , sizeof(udc_t)); |
| 238 | |
| 239 | /* malloc control data buffers */ |
| 240 | udc_dev->ctrl_rx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_RX_BUF_SIZE, CACHE_LINE)); |
| 241 | ASSERT(udc_dev->ctrl_rx_buf); |
| 242 | |
| 243 | udc_dev->ctrl_tx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_TX_BUF_SIZE, CACHE_LINE)); |
| 244 | ASSERT(udc_dev->ctrl_tx_buf); |
| 245 | |
| 246 | /* initialize string id */ |
| 247 | udc_dev->next_string_id = 1; |
| 248 | |
| 249 | /* Initialize ept data */ |
| 250 | /* alloc table to assume EP0 In/OUT are already allocated.*/ |
| 251 | udc_dev->ept_alloc_table = EPT_TX(0) | EPT_RX(0); |
| 252 | udc_dev->ept_list = NULL; |
| 253 | |
| 254 | usb30_init(); |
| 255 | |
| 256 | /* register descriptors */ |
| 257 | udc_register_language_desc(udc_dev); |
| 258 | udc_register_device_desc_usb_20(udc_dev, dev_info); |
| 259 | udc_register_device_desc_usb_30(udc_dev, dev_info); |
| 260 | udc_register_bos_desc(udc_dev); |
| 261 | |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | /* application registers its gadget by calling this func. |
| 266 | * gadget == interface descriptor |
| 267 | */ |
| 268 | int udc_register_gadget(struct udc_gadget *gadget) |
| 269 | { |
| 270 | ASSERT(gadget); |
| 271 | |
| 272 | /* check if already registered */ |
| 273 | if (udc_dev->gadget) |
| 274 | { |
| 275 | ERR("\nonly one gadget supported\n"); |
| 276 | return -1; |
| 277 | } |
| 278 | |
| 279 | /* create our configuration descriptors based on this gadget data */ |
| 280 | udc_register_config_desc_usb20(udc_dev, gadget); |
| 281 | udc_register_config_desc_usb30(udc_dev, gadget); |
| 282 | |
| 283 | /* save the gadget */ |
| 284 | udc_dev->gadget = gadget; |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | /* udc_start: */ |
| 290 | int udc_start(void) |
| 291 | { |
| 292 | /* 19. run |
| 293 | * enable device to receive SOF packets and |
| 294 | * respond to control transfers on EP0 and generate events. |
| 295 | */ |
| 296 | dwc_device_run(udc_dev->dwc, 1); |
| 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | /* Control data rx callback. Called by DWC layer when it receives control |
| 302 | * data from host. |
| 303 | */ |
| 304 | void udc_control_rx_callback(void *context, unsigned actual, int status) |
| 305 | { |
| 306 | udc_t *udc = (udc_t *) context; |
| 307 | |
| 308 | /* Force reload of buffer update by controller from memory */ |
| 309 | arch_invalidate_cache_range((addr_t) udc->ctrl_rx_buf, actual); |
| 310 | |
| 311 | /* TODO: for now, there is only one 3-stage write during 3.0 enumeration |
| 312 | * (SET_SEL), which causes this callback. Ideally, set_periodic() must |
| 313 | * be based on which control rx just happened. |
| 314 | * Also, the value of 0x65 should depend on the data received for SET_SEL. |
| 315 | * For now, this value works just fine. |
| 316 | */ |
| 317 | dwc_device_set_periodic_param(udc->dwc, 0x65); |
| 318 | } |
| 319 | |
| 320 | /* lookup request name for debug purposes */ |
| 321 | static const char *reqname(uint32_t r) |
| 322 | { |
| 323 | switch (r) { |
| 324 | case GET_STATUS: |
| 325 | return "GET_STATUS"; |
| 326 | case CLEAR_FEATURE: |
| 327 | return "CLEAR_FEATURE"; |
| 328 | case SET_FEATURE: |
| 329 | return "SET_FEATURE"; |
| 330 | case SET_ADDRESS: |
| 331 | return "SET_ADDRESS"; |
| 332 | case GET_DESCRIPTOR: |
| 333 | return "GET_DESCRIPTOR"; |
| 334 | case SET_DESCRIPTOR: |
| 335 | return "SET_DESCRIPTOR"; |
| 336 | case GET_CONFIGURATION: |
| 337 | return "GET_CONFIGURATION"; |
| 338 | case SET_CONFIGURATION: |
| 339 | return "SET_CONFIGURATION"; |
| 340 | case GET_INTERFACE: |
| 341 | return "GET_INTERFACE"; |
| 342 | case SET_INTERFACE: |
| 343 | return "SET_INTERFACE"; |
| 344 | case SET_SEL: |
| 345 | return "SET_SEL"; |
| 346 | default: |
| 347 | return "*UNKNOWN*"; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | /* callback function called by DWC layer when a setup packed is received. |
| 352 | * the return value tells dwc layer whether this setup pkt results in |
| 353 | * a 2-stage or a 3-stage control transfer or stall. |
| 354 | */ |
| 355 | static int udc_handle_setup(void *context, uint8_t *data) |
| 356 | { |
| 357 | udc_t *udc = (udc_t *) context; |
| 358 | uint32_t len; |
| 359 | |
| 360 | ASSERT(udc); |
| 361 | |
| 362 | dwc_dev_t *dwc = udc->dwc; |
| 363 | ASSERT(dwc); |
| 364 | |
| 365 | struct setup_packet s = *((struct setup_packet*) data); |
| 366 | |
| 367 | DBG("\n SETUP request: \n type = 0x%x \n request = 0x%x \n value = 0x%x" |
| 368 | " \n index = 0x%x \n length = 0x%x\n", |
| 369 | s.type, s.request, s.value, s.index, s.length); |
| 370 | |
| 371 | switch (SETUP(s.type, s.request)) |
| 372 | { |
| 373 | case SETUP(DEVICE_READ, GET_STATUS): |
| 374 | { |
| 375 | DBG("\n DEVICE_READ : GET_STATUS: value = %d index = %d" |
| 376 | " length = %d", s.value, s.index, s.length); |
| 377 | |
| 378 | if (s.length == 2) { |
| 379 | |
| 380 | uint16_t zero = 0; |
| 381 | len = 2; |
| 382 | |
| 383 | /* copy to tx buffer */ |
| 384 | memcpy(udc->ctrl_tx_buf, &zero, len); |
| 385 | |
| 386 | /* flush buffer to main memory before queueing the request */ |
| 387 | arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len); |
| 388 | |
| 389 | dwc_transfer_request(udc->dwc, |
| 390 | 0, |
| 391 | DWC_EP_DIRECTION_IN, |
| 392 | udc->ctrl_tx_buf, |
| 393 | len, |
| 394 | NULL, |
| 395 | NULL); |
| 396 | |
| 397 | return DWC_SETUP_3_STAGE; |
| 398 | } |
| 399 | } |
| 400 | break; |
| 401 | case SETUP(DEVICE_READ, GET_DESCRIPTOR): |
| 402 | { |
| 403 | DBG("\n DEVICE_READ : GET_DESCRIPTOR: value = %d", s.value); |
| 404 | |
| 405 | /* setup usb ep0-IN to send our device descriptor */ |
| 406 | struct udc_descriptor *desc; |
| 407 | |
| 408 | for (desc = udc->desc_list; desc; desc = desc->next) |
| 409 | { |
| 410 | /* tag must match the value AND |
| 411 | * if speed is SS, desc must comply with 30 spec OR |
| 412 | * if speed is not SS, desc must comply with 20 spec. |
| 413 | */ |
| 414 | if ((desc->tag == s.value) && |
| 415 | (((udc->speed == UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_30)) || |
| 416 | ((udc->speed != UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_20))) |
| 417 | ) |
| 418 | { |
| 419 | if (desc->len > s.length) |
| 420 | len = s.length; |
| 421 | else |
| 422 | len = desc->len; |
| 423 | |
| 424 | /* copy to tx buffer */ |
| 425 | memcpy(udc->ctrl_tx_buf, desc->data, len); |
| 426 | |
| 427 | /* flush buffer to main memory before queueing the request */ |
| 428 | arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len); |
| 429 | |
| 430 | dwc_transfer_request(udc->dwc, |
| 431 | 0, |
| 432 | DWC_EP_DIRECTION_IN, |
| 433 | udc->ctrl_tx_buf, |
| 434 | len, |
| 435 | NULL, |
| 436 | NULL); |
| 437 | |
| 438 | return DWC_SETUP_3_STAGE; |
| 439 | } |
| 440 | } |
| 441 | DBG("\n Did not find matching descriptor: = 0x%x", s.value); |
| 442 | } |
| 443 | break; |
| 444 | case SETUP(DEVICE_READ, GET_CONFIGURATION): |
| 445 | { |
| 446 | DBG("\n DEVICE_READ : GET_CONFIGURATION"); |
| 447 | |
| 448 | if ((s.value == 0) && (s.index == 0) && (s.length == 1)) { |
| 449 | |
| 450 | len = 1; |
| 451 | |
| 452 | /* copy to tx buffer */ |
| 453 | memcpy(udc->ctrl_tx_buf, &udc->config_selected, len); |
| 454 | |
| 455 | /* flush buffer to main memory before queueing the request */ |
| 456 | arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len); |
| 457 | |
| 458 | dwc_transfer_request(udc->dwc, |
| 459 | 0, |
| 460 | DWC_EP_DIRECTION_IN, |
| 461 | udc->ctrl_tx_buf, |
| 462 | len, |
| 463 | NULL, |
| 464 | NULL); |
| 465 | |
| 466 | return DWC_SETUP_3_STAGE; |
| 467 | } |
| 468 | else |
| 469 | { |
| 470 | ASSERT(0); |
| 471 | } |
| 472 | } |
| 473 | break; |
| 474 | case SETUP(DEVICE_WRITE, SET_CONFIGURATION): |
| 475 | { |
| 476 | DBG("\n DEVICE_WRITE : SET_CONFIGURATION"); |
| 477 | |
| 478 | /* select configuration 1 */ |
| 479 | if (s.value == 1) { |
| 480 | struct udc_endpoint *ept; |
| 481 | /* enable endpoints */ |
| 482 | for (ept = udc->ept_list; ept; ept = ept->next) { |
| 483 | if (ept->num == 0) |
| 484 | continue; |
| 485 | else |
| 486 | { |
| 487 | /* add this ep to dwc ep list */ |
| 488 | dwc_ep_t ep; |
| 489 | |
| 490 | ep.number = ept->num; |
| 491 | ep.dir = ept->in; |
| 492 | ep.type = EP_TYPE_BULK; /* the only one supported */ |
| 493 | ep.max_pkt_size = ept->maxpkt; |
| 494 | ep.burst_size = ept->maxburst; |
| 495 | ep.zlp = 0; /* TODO: zlp could be made part of ept */ |
| 496 | ep.trb_count = ept->trb_count; |
| 497 | ep.trb = ept->trb; |
| 498 | |
| 499 | dwc_device_add_ep(dwc, ep); |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | /* now that we have saved the non-control EP details, set config */ |
| 504 | dwc_device_set_configuration(dwc); |
| 505 | |
| 506 | /* inform client that we are configured. */ |
| 507 | udc->gadget->notify(udc_dev->gadget, UDC_EVENT_ONLINE); |
| 508 | |
| 509 | udc->config_selected = 1; |
| 510 | |
| 511 | return DWC_SETUP_2_STAGE; |
| 512 | } |
| 513 | else if (s.value == 0) |
| 514 | { |
| 515 | /* 0 == de-configure. */ |
| 516 | udc->config_selected = 0; |
| 517 | DBG("\n\n CONFIG = 0 !!!!!!!!!\n\n"); |
| 518 | return DWC_SETUP_2_STAGE; |
| 519 | /* TODO: do proper handling for de-config */ |
| 520 | } |
| 521 | else |
| 522 | { |
| 523 | ERR("\n CONFIG = %d not supported\n", s.value); |
| 524 | ASSERT(0); |
| 525 | } |
| 526 | } |
| 527 | break; |
| 528 | case SETUP(DEVICE_WRITE, SET_ADDRESS): |
| 529 | { |
| 530 | DBG("\n DEVICE_WRITE : SET_ADDRESS"); |
| 531 | |
| 532 | dwc_device_set_addr(dwc, s.value); |
| 533 | return DWC_SETUP_2_STAGE; |
| 534 | } |
| 535 | break; |
| 536 | case SETUP(INTERFACE_WRITE, SET_INTERFACE): |
| 537 | { |
| 538 | DBG("\n DEVICE_WRITE : SET_INTERFACE"); |
| 539 | /* if we ack this everything hangs */ |
| 540 | /* per spec, STALL is valid if there is not alt func */ |
| 541 | goto stall; |
| 542 | } |
| 543 | break; |
| 544 | case SETUP(DEVICE_WRITE, SET_FEATURE): |
| 545 | { |
| 546 | DBG("\n DEVICE_WRITE : SET_FEATURE"); |
| 547 | goto stall; |
| 548 | } |
| 549 | break; |
| 550 | case SETUP(DEVICE_WRITE, CLEAR_FEATURE): |
| 551 | { |
| 552 | DBG("\n DEVICE_WRITE : CLEAR_FEATURE"); |
| 553 | goto stall; |
| 554 | } |
| 555 | break; |
| 556 | case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE): |
| 557 | { |
| 558 | DBG("\n DEVICE_WRITE : CLEAR_FEATURE"); |
| 559 | goto stall; |
| 560 | } |
| 561 | break; |
| 562 | case SETUP(DEVICE_WRITE, SET_SEL): |
| 563 | { |
| 564 | DBG("\n DEVICE_WRITE : SET_SEL"); |
| 565 | |
| 566 | /* this is 3-stage write. need to receive data of s.length size. */ |
| 567 | if (s.length > 0) { |
| 568 | dwc_transfer_request(udc->dwc, |
| 569 | 0, |
| 570 | DWC_EP_DIRECTION_OUT, |
| 571 | udc->ctrl_rx_buf, |
| 572 | UDC_CONTROL_RX_BUF_SIZE, |
| 573 | udc_control_rx_callback, |
| 574 | (void *) udc); |
| 575 | return DWC_SETUP_3_STAGE; |
| 576 | } |
| 577 | else |
| 578 | { |
| 579 | /* length must be non-zero */ |
| 580 | ASSERT(0); |
| 581 | } |
| 582 | } |
| 583 | break; |
| 584 | |
| 585 | default: |
| 586 | ERR("\n Unknown setup req.\n type = 0x%x value = %d index = %d" |
| 587 | " length = %d\n", s.type, s.value, s.index, s.length); |
| 588 | ASSERT(0); |
| 589 | } |
| 590 | |
| 591 | stall: |
| 592 | ERR("\nSTALL. Unsupported setup req: %s %d %d %d %d %d\n", |
| 593 | reqname(s.request), s.type, s.request, s.value, s.index, s.length); |
| 594 | |
| 595 | return DWC_SETUP_ERROR; |
| 596 | } |
| 597 | |
| 598 | /* Callback function called by DWC layer when a request to transfer data |
| 599 | * on non-control EP is completed. |
| 600 | */ |
| 601 | void udc_request_complete(void *context, uint32_t actual, int status) |
| 602 | { |
| 603 | struct udc_request *req = ((udc_t *) context)->queued_req; |
| 604 | |
| 605 | DBG("\n UDC: udc_request_callback: xferred %d bytes status = %d\n", |
| 606 | actual, status); |
| 607 | |
| 608 | /* clear the queued request. */ |
| 609 | ((udc_t *) context)->queued_req = NULL; |
| 610 | |
| 611 | if (req->complete) |
| 612 | { |
| 613 | req->complete(req, actual, status); |
| 614 | } |
| 615 | |
| 616 | DBG("\n UDC: udc_request_callback: done fastboot callback\n"); |
| 617 | } |
| 618 | |
| 619 | /* App interface to queue in data transfer requests for control and data ep */ |
| 620 | int udc_request_queue(struct udc_endpoint *ept, struct udc_request *req) |
| 621 | { |
| 622 | int ret; |
| 623 | dwc_dev_t *dwc_dev = udc_dev->dwc; |
| 624 | |
| 625 | /* ensure device is initialized before queuing request */ |
| 626 | ASSERT(dwc_dev); |
| 627 | |
| 628 | /* if device is not configured, return error */ |
| 629 | if(udc_dev->config_selected == 0) |
| 630 | { |
| 631 | return -1; |
| 632 | } |
| 633 | |
| 634 | /* only one request at a time is supported. |
| 635 | * check if a request is already queued. |
| 636 | */ |
| 637 | if(udc_dev->queued_req) |
| 638 | { |
| 639 | return -1; |
| 640 | } |
| 641 | |
| 642 | DBG("\n udc_request_queue: entry: ep_usb_num = %d", ept->num); |
| 643 | |
| 644 | /* save the queued request. */ |
| 645 | udc_dev->queued_req = req; |
| 646 | |
| 647 | ret = dwc_transfer_request(dwc_dev, |
| 648 | ept->num, |
| 649 | ept->in ? DWC_EP_DIRECTION_IN : DWC_EP_DIRECTION_OUT, |
| 650 | req->buf, |
| 651 | req->length, |
| 652 | udc_request_complete, |
| 653 | (void *) udc_dev); |
| 654 | |
| 655 | DBG("\n udc_request_queue: exit: ep_usb_num = %d", ept->num); |
| 656 | |
| 657 | return ret; |
| 658 | } |
| 659 | |
| 660 | /* callback function called by dwc layer if any dwc event occurs */ |
| 661 | void udc_dwc_notify(void *context, dwc_notify_event_t event) |
| 662 | { |
| 663 | udc_t *udc = (udc_t *) context; |
| 664 | |
| 665 | switch (event) |
| 666 | { |
| 667 | case DWC_NOTIFY_EVENT_CONNECTED_LS: |
| 668 | udc->speed = UDC_SPEED_LS; |
| 669 | break; |
| 670 | case DWC_NOTIFY_EVENT_CONNECTED_FS: |
| 671 | udc->speed = UDC_SPEED_FS; |
| 672 | break; |
| 673 | case DWC_NOTIFY_EVENT_CONNECTED_HS: |
| 674 | udc->speed = UDC_SPEED_HS; |
| 675 | break; |
| 676 | case DWC_NOTIFY_EVENT_CONNECTED_SS: |
| 677 | udc->speed = UDC_SPEED_SS; |
| 678 | break; |
| 679 | case DWC_NOTIFY_EVENT_DISCONNECTED: |
| 680 | case DWC_NOTIFY_EVENT_OFFLINE: |
| 681 | udc->config_selected = 0; |
| 682 | if (udc->gadget && udc->gadget->notify) |
| 683 | udc->gadget->notify(udc->gadget, UDC_EVENT_OFFLINE); |
| 684 | break; |
| 685 | default: |
| 686 | ASSERT(0); |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | |
| 691 | /******************* Function related to descriptor allocation etc.************/ |
| 692 | |
| 693 | static struct udc_endpoint *_udc_endpoint_alloc(uint8_t num, |
| 694 | uint8_t in, |
| 695 | uint16_t max_pkt) |
| 696 | { |
| 697 | struct udc_endpoint *ept; |
| 698 | udc_t *udc = udc_dev; |
| 699 | |
| 700 | ept = malloc(sizeof(*ept)); |
| 701 | ASSERT(ept); |
| 702 | |
| 703 | ept->maxpkt = max_pkt; |
| 704 | ept->num = num; |
| 705 | ept->in = !!in; |
| 706 | ept->maxburst = 4; /* no performance improvement is seen beyond burst size of 4 */ |
| 707 | ept->trb_count = 66; /* each trb can transfer (16MB - 1). 65 for 1GB transfer + 1 for roundup/zero length pkt. */ |
| 708 | ept->trb = memalign(lcm(CACHE_LINE, 16), ROUNDUP(ept->trb_count*sizeof(dwc_trb_t), CACHE_LINE)); /* TRB must be aligned to 16 */ |
| 709 | ASSERT(ept->trb); |
| 710 | |
| 711 | /* push it on top of ept_list */ |
| 712 | ept->next = udc->ept_list; |
| 713 | udc->ept_list = ept; |
| 714 | |
| 715 | return ept; |
| 716 | } |
| 717 | |
| 718 | /* Called to create non-control in/out End Point structures by the APP */ |
| 719 | struct udc_endpoint *udc_endpoint_alloc(unsigned type, unsigned maxpkt) |
| 720 | { |
| 721 | struct udc_endpoint *ept; |
| 722 | uint8_t in; |
| 723 | uint8_t n; |
| 724 | udc_t *udc = udc_dev; |
| 725 | |
| 726 | if (type == UDC_TYPE_BULK_IN) { |
| 727 | in = 1; |
| 728 | } else if (type == UDC_TYPE_BULK_OUT) { |
| 729 | in = 0; |
| 730 | } else { |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | for (n = 1; n < 16; n++) { |
| 735 | uint32_t bit = in ? EPT_TX(n) : EPT_RX(n); |
| 736 | if (udc->ept_alloc_table & bit) |
| 737 | continue; |
| 738 | ept = _udc_endpoint_alloc(n, in, maxpkt); |
| 739 | if (ept) |
| 740 | udc->ept_alloc_table |= bit; |
| 741 | return ept; |
| 742 | } |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | |
| 747 | /* create config + interface + ep desc for 2.0 */ |
| 748 | static void udc_register_config_desc_usb20(udc_t *udc, |
| 749 | struct udc_gadget *gadget) |
| 750 | { |
| 751 | uint8_t *data; |
| 752 | uint16_t size; |
| 753 | struct udc_descriptor *desc; |
| 754 | |
| 755 | ASSERT(udc); |
| 756 | ASSERT(gadget); |
| 757 | |
| 758 | /* create our configuration descriptor */ |
| 759 | |
| 760 | /* size is the total size of (config + interface + all EPs) descriptor */ |
| 761 | size = UDC_DESC_SIZE_CONFIGURATION + |
| 762 | UDC_DESC_SIZE_INTERFACE + |
| 763 | (gadget->ifc_endpoints*UDC_DESC_SIZE_ENDPOINT); |
| 764 | |
| 765 | desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_20); |
| 766 | |
| 767 | data = desc->data; |
| 768 | |
| 769 | /* Config desc */ |
| 770 | data[0] = 0x09; |
| 771 | data[1] = TYPE_CONFIGURATION; |
| 772 | data[2] = size; |
| 773 | data[3] = size >> 8; |
| 774 | data[4] = 0x01; /* number of interfaces */ |
| 775 | data[5] = 0x01; /* configuration value */ |
| 776 | data[6] = 0x00; /* configuration string */ |
| 777 | data[7] = 0xC0; /* attributes: reserved and self-powered set */ |
| 778 | data[8] = 0x00; /* max power: 0ma since we are self powered */ |
| 779 | data += 9; |
| 780 | |
| 781 | /* Interface desc */ |
| 782 | data[0] = 0x09; |
| 783 | data[1] = TYPE_INTERFACE; |
| 784 | data[2] = 0x00; /* ifc number */ |
| 785 | data[3] = 0x00; /* alt number */ |
| 786 | data[4] = gadget->ifc_endpoints; |
| 787 | data[5] = gadget->ifc_class; |
| 788 | data[6] = gadget->ifc_subclass; |
| 789 | data[7] = gadget->ifc_protocol; |
| 790 | data[8] = udc_string_desc_alloc(udc, gadget->ifc_string); |
| 791 | data += 9; |
| 792 | |
| 793 | for (uint8_t n = 0; n < gadget->ifc_endpoints; n++) { |
| 794 | udc_ept_desc_fill(gadget->ept[n], data); |
| 795 | data += UDC_DESC_SIZE_ENDPOINT; |
| 796 | } |
| 797 | |
| 798 | udc_descriptor_register(udc, desc); |
| 799 | } |
| 800 | |
| 801 | /* create config + interface + ep desc for 3.0 */ |
| 802 | static void udc_register_config_desc_usb30(udc_t *udc, |
| 803 | struct udc_gadget *gadget) |
| 804 | { |
| 805 | uint8_t *data; |
| 806 | uint16_t size; |
| 807 | struct udc_descriptor *desc; |
| 808 | |
| 809 | ASSERT(udc); |
| 810 | ASSERT(gadget); |
| 811 | |
| 812 | /* create our configuration descriptor */ |
| 813 | |
| 814 | /* size is the total size of (config + interface + all EPs) descriptor */ |
| 815 | size = UDC_DESC_SIZE_CONFIGURATION + |
| 816 | UDC_DESC_SIZE_INTERFACE + |
| 817 | (gadget->ifc_endpoints*(UDC_DESC_SIZE_ENDPOINT + UDC_DESC_SIZE_ENDPOINT_COMP)); |
| 818 | |
| 819 | desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_30); |
| 820 | |
| 821 | data = desc->data; |
| 822 | |
| 823 | /* Config desc */ |
| 824 | data[0] = 0x09; |
| 825 | data[1] = TYPE_CONFIGURATION; |
| 826 | data[2] = size; |
| 827 | data[3] = size >> 8; |
| 828 | data[4] = 0x01; /* number of interfaces */ |
| 829 | data[5] = 0x01; /* configuration value */ |
| 830 | data[6] = 0x00; /* configuration string */ |
| 831 | data[7] = 0xC0; /* attributes: reserved and self-powered set */ |
| 832 | data[8] = 0x00; /* max power: 0ma since we are self powered */ |
| 833 | data += 9; |
| 834 | |
| 835 | /* Interface desc */ |
| 836 | data[0] = 0x09; |
| 837 | data[1] = TYPE_INTERFACE; |
| 838 | data[2] = 0x00; /* ifc number */ |
| 839 | data[3] = 0x00; /* alt number */ |
| 840 | data[4] = gadget->ifc_endpoints; |
| 841 | data[5] = gadget->ifc_class; |
| 842 | data[6] = gadget->ifc_subclass; |
| 843 | data[7] = gadget->ifc_protocol; |
| 844 | data[8] = udc_string_desc_alloc(udc, gadget->ifc_string); |
| 845 | data += 9; |
| 846 | |
| 847 | for (uint8_t n = 0; n < gadget->ifc_endpoints; n++) |
| 848 | { |
| 849 | /* fill EP desc */ |
| 850 | udc_ept_desc_fill(gadget->ept[n], data); |
| 851 | data += UDC_DESC_SIZE_ENDPOINT; |
| 852 | |
| 853 | /* fill EP companion desc */ |
| 854 | udc_ept_comp_desc_fill(gadget->ept[n], data); |
| 855 | data += UDC_DESC_SIZE_ENDPOINT_COMP; |
| 856 | } |
| 857 | |
| 858 | udc_descriptor_register(udc, desc); |
| 859 | } |
| 860 | |
| 861 | |
| 862 | static void udc_register_device_desc_usb_20(udc_t *udc, |
| 863 | struct udc_device *dev_info) |
| 864 | { |
| 865 | uint8_t *data; |
| 866 | struct udc_descriptor *desc; |
| 867 | |
| 868 | /* create our device descriptor */ |
| 869 | desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_20); |
| 870 | data = desc->data; |
| 871 | |
| 872 | /* data 0 and 1 is filled by descriptor alloc routine. |
| 873 | * fill in the remaining entries. |
| 874 | */ |
| 875 | data[2] = 0x00; /* usb spec minor rev */ |
| 876 | data[3] = 0x02; /* usb spec major rev */ |
| 877 | data[4] = 0x00; /* class */ |
| 878 | data[5] = 0x00; /* subclass */ |
| 879 | data[6] = 0x00; /* protocol */ |
| 880 | data[7] = 0x40; /* max packet size on ept 0 */ |
| 881 | |
| 882 | memcpy(data + 8, &dev_info->vendor_id, sizeof(short)); |
| 883 | memcpy(data + 10, &dev_info->product_id, sizeof(short)); |
| 884 | memcpy(data + 12, &dev_info->version_id, sizeof(short)); |
| 885 | |
| 886 | data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer); |
| 887 | data[15] = udc_string_desc_alloc(udc, dev_info->product); |
| 888 | data[16] = udc_string_desc_alloc(udc, dev_info->serialno); |
| 889 | data[17] = 1; /* number of configurations */ |
| 890 | |
| 891 | udc_descriptor_register(udc, desc); |
| 892 | } |
| 893 | |
| 894 | static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info) |
| 895 | { |
| 896 | uint8_t *data; |
| 897 | struct udc_descriptor *desc; |
| 898 | |
| 899 | /* create our device descriptor */ |
| 900 | desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_30); |
| 901 | data = desc->data; |
| 902 | |
| 903 | /* data 0 and 1 is filled by descriptor alloc routine. |
| 904 | * fill in the remaining entries. |
| 905 | */ |
| 906 | data[2] = 0x00; /* usb spec minor rev */ |
| 907 | data[3] = 0x03; /* usb spec major rev */ |
| 908 | data[4] = 0x00; /* class */ |
| 909 | data[5] = 0x00; /* subclass */ |
| 910 | data[6] = 0x00; /* protocol */ |
| 911 | data[7] = 0x09; /* max packet size on ept 0 */ |
| 912 | memcpy(data + 8, &dev_info->vendor_id, sizeof(short)); |
| 913 | memcpy(data + 10, &dev_info->product_id, sizeof(short)); |
| 914 | memcpy(data + 12, &dev_info->version_id, sizeof(short)); |
| 915 | data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer); |
| 916 | data[15] = udc_string_desc_alloc(udc, dev_info->product); |
| 917 | data[16] = udc_string_desc_alloc(udc, dev_info->serialno); |
| 918 | data[17] = 1; /* number of configurations */ |
| 919 | |
| 920 | udc_descriptor_register(udc, desc); |
| 921 | } |
| 922 | |
| 923 | static void udc_register_bos_desc(udc_t *udc) |
| 924 | { |
| 925 | uint8_t *data; |
| 926 | struct udc_descriptor *desc; |
| 927 | |
| 928 | /* create our device descriptor */ |
| 929 | desc = udc_descriptor_alloc(TYPE_BOS, 0, 15, UDC_DESC_SPEC_30); /* 15 is total length of bos + other descriptors inside it */ |
| 930 | data = desc->data; |
| 931 | |
| 932 | /* data 0 and 1 is filled by descriptor alloc routine. |
| 933 | * fill in the remaining entries. |
| 934 | */ |
| 935 | data[0] = 0x05; /* BOS desc len */ |
| 936 | data[1] = TYPE_BOS; /* BOS desc type */ |
| 937 | data[2] = 0x0F; /* total len of bos desc and its sub desc */ |
| 938 | data[3] = 0x00; /* total len of bos desc and its sub desc */ |
| 939 | data[4] = 0x01; /* num of sub desc inside bos */ |
| 940 | |
| 941 | data[5] = 0x0A; /* desc len */ |
| 942 | data[6] = 0x10; /* Device Capability desc */ |
| 943 | data[7] = 0x03; /* 3 == SuperSpeed capable */ |
| 944 | data[8] = 0x00; /* Attribute: latency tolerance msg: No */ |
| 945 | data[9] = 0x0F; /* Supported Speeds (bit mask): LS, FS, HS, SS */ |
| 946 | data[10] = 0x00; /* Reserved part of supported wSupportedSpeeds */ |
| 947 | data[11] = 0x01; /* lowest supported speed with full functionality: FS */ |
| 948 | data[12] = 0x00; /* U1 device exit latency */ |
| 949 | data[13] = 0x00; /* U2 device exit latency (lsb) */ |
| 950 | data[14] = 0x00; /* U2 device exit latency (msb) */ |
| 951 | |
| 952 | udc_descriptor_register(udc, desc); |
| 953 | } |
| 954 | |
| 955 | static void udc_register_language_desc(udc_t *udc) |
| 956 | { |
| 957 | /* create and register a language table descriptor */ |
| 958 | /* language 0x0409 is US English */ |
| 959 | struct udc_descriptor *desc = udc_descriptor_alloc(TYPE_STRING, |
| 960 | 0, |
| 961 | 4, |
| 962 | UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30); |
| 963 | desc->data[2] = 0x09; |
| 964 | desc->data[3] = 0x04; |
| 965 | udc_descriptor_register(udc, desc); |
| 966 | } |
| 967 | |
| 968 | static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data) |
| 969 | { |
| 970 | data[0] = 7; |
| 971 | data[1] = TYPE_ENDPOINT; |
| 972 | data[2] = ept->num | (ept->in ? 0x80 : 0x00); |
| 973 | data[3] = 0x02; /* bulk -- the only kind we support */ |
| 974 | data[4] = ept->maxpkt; |
| 975 | data[5] = ept->maxpkt >> 8; |
| 976 | data[6] = 0; /* bInterval: must be 0 for bulk. */ |
| 977 | } |
| 978 | |
| 979 | static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data) |
| 980 | { |
| 981 | data[0] = 6; /* bLength */ |
| 982 | data[1] = TYPE_SS_EP_COMP; /* ep type */ |
| 983 | data[2] = ept->maxburst; /* maxBurst */ |
| 984 | data[3] = 0x0; /* maxStreams */ |
| 985 | data[4] = 0x0; /* wBytesPerInterval */ |
| 986 | data[5] = 0x0; /* wBytesPerInterval */ |
| 987 | } |
| 988 | |
| 989 | static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str) |
| 990 | { |
| 991 | uint32_t len; |
| 992 | struct udc_descriptor *desc; |
| 993 | uint8_t *data; |
| 994 | |
| 995 | if (udc->next_string_id > 255) |
| 996 | return 0; |
| 997 | |
| 998 | if (!str) |
| 999 | return 0; |
| 1000 | |
| 1001 | len = strlen(str); |
| 1002 | desc = udc_descriptor_alloc(TYPE_STRING, |
| 1003 | udc->next_string_id, |
| 1004 | len * 2 + 2, |
| 1005 | UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30); |
| 1006 | if (!desc) |
| 1007 | return 0; |
| 1008 | udc->next_string_id++; |
| 1009 | |
| 1010 | /* expand ascii string to utf16 */ |
| 1011 | data = desc->data + 2; |
| 1012 | while (len-- > 0) { |
| 1013 | *data++ = *str++; |
| 1014 | *data++ = 0; |
| 1015 | } |
| 1016 | |
| 1017 | udc_descriptor_register(udc, desc); |
| 1018 | return desc->tag & 0xff; |
| 1019 | } |
| 1020 | |
| 1021 | |
| 1022 | static struct udc_descriptor *udc_descriptor_alloc(uint32_t type, |
| 1023 | uint32_t num, |
| 1024 | uint32_t len, |
| 1025 | udc_desc_spec_t spec) |
| 1026 | { |
| 1027 | struct udc_descriptor *desc; |
| 1028 | if ((len > 255) || (len < 2) || (num > 255) || (type > 255)) |
| 1029 | return 0; |
| 1030 | |
| 1031 | if (!(desc = malloc(sizeof(struct udc_descriptor) + len))) |
| 1032 | return 0; |
| 1033 | |
| 1034 | desc->next = 0; |
| 1035 | desc->tag = (type << 8) | num; |
| 1036 | desc->len = len; |
| 1037 | desc->spec = spec; |
| 1038 | |
| 1039 | /* descriptor data */ |
| 1040 | desc->data[0] = len; |
| 1041 | desc->data[1] = type; |
| 1042 | |
| 1043 | return desc; |
| 1044 | } |
| 1045 | |
| 1046 | static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc) |
| 1047 | { |
| 1048 | desc->next = udc->desc_list; |
| 1049 | udc->desc_list = desc; |
| 1050 | } |
| 1051 | |
| 1052 | |
| 1053 | struct udc_request *udc_request_alloc(void) |
| 1054 | { |
| 1055 | struct udc_request *req; |
| 1056 | |
| 1057 | req = malloc(sizeof(*req)); |
| 1058 | ASSERT(req); |
| 1059 | |
| 1060 | req->buf = 0; |
| 1061 | req->length = 0; |
| 1062 | req->complete = NULL; |
| 1063 | req->context = 0; |
| 1064 | |
| 1065 | return req; |
| 1066 | } |
| 1067 | |
| 1068 | void udc_request_free(struct udc_request *req) |
| 1069 | { |
| 1070 | free(req); |
| 1071 | } |
| 1072 | |
| 1073 | void udc_endpoint_free(struct udc_endpoint *ept) |
| 1074 | { |
| 1075 | /* TODO */ |
| 1076 | } |
| 1077 | |
| 1078 | int udc_stop(void) |
| 1079 | { |
| 1080 | dwc_device_run(udc_dev->dwc, 0); |
| 1081 | |
| 1082 | return 0; |
| 1083 | } |