Channagoud Kadabi | 3f42853 | 2014-01-28 21:33:34 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <platform/iomap.h> |
| 30 | #include <platform/irqs.h> |
| 31 | #include <platform/interrupts.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <kernel/event.h> |
| 34 | #include <target.h> |
| 35 | #include <string.h> |
| 36 | #include <stdlib.h> |
| 37 | #include <bits.h> |
| 38 | #include <debug.h> |
| 39 | #include <sdhci.h> |
Channagoud Kadabi | 3f42853 | 2014-01-28 21:33:34 -0800 | [diff] [blame^] | 40 | #include <sdhci_msm.h> |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 41 | |
| 42 | /* |
Channagoud Kadabi | 7ad70ea | 2013-08-08 13:51:04 -0700 | [diff] [blame] | 43 | * Function: sdhci reset |
| 44 | * Arg : Host structure & mask to write to reset register |
| 45 | * Return : None |
| 46 | * Flow: : Reset the host controller |
| 47 | */ |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 48 | void sdhci_reset(struct sdhci_host *host, uint8_t mask) |
Channagoud Kadabi | 7ad70ea | 2013-08-08 13:51:04 -0700 | [diff] [blame] | 49 | { |
| 50 | uint32_t reg; |
| 51 | uint32_t timeout = SDHCI_RESET_MAX_TIMEOUT; |
| 52 | |
| 53 | REG_WRITE8(host, mask, SDHCI_RESET_REG); |
| 54 | |
| 55 | /* Wait for the reset to complete */ |
| 56 | do { |
| 57 | reg = REG_READ8(host, SDHCI_RESET_REG); |
| 58 | reg &= mask; |
| 59 | |
| 60 | if (!reg) |
| 61 | break; |
| 62 | if (!timeout) |
| 63 | { |
| 64 | dprintf(CRITICAL, "Error: sdhci reset failed for: %x\n", mask); |
| 65 | break; |
| 66 | } |
| 67 | |
| 68 | timeout--; |
| 69 | mdelay(1); |
| 70 | |
| 71 | } while(1); |
| 72 | } |
| 73 | |
| 74 | /* |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 75 | * Function: sdhci error status enable |
| 76 | * Arg : Host structure |
| 77 | * Return : None |
| 78 | * Flow: : Enable command error status |
| 79 | */ |
| 80 | static void sdhci_error_status_enable(struct sdhci_host *host) |
| 81 | { |
| 82 | /* Enable all interrupt status */ |
| 83 | REG_WRITE16(host, SDHCI_NRML_INT_STS_EN, SDHCI_NRML_INT_STS_EN_REG); |
| 84 | REG_WRITE16(host, SDHCI_ERR_INT_STS_EN, SDHCI_ERR_INT_STS_EN_REG); |
| 85 | /* Enable all interrupt signal */ |
| 86 | REG_WRITE16(host, SDHCI_NRML_INT_SIG_EN, SDHCI_NRML_INT_SIG_EN_REG); |
| 87 | REG_WRITE16(host, SDHCI_ERR_INT_SIG_EN, SDHCI_ERR_INT_SIG_EN_REG); |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * Function: sdhci clock supply |
| 92 | * Arg : Host structure |
| 93 | * Return : 0 on Success, 1 on Failure |
| 94 | * Flow: : 1. Calculate the clock divider |
| 95 | * 2. Set the clock divider |
| 96 | * 3. Check if clock stable |
| 97 | * 4. Enable Clock |
| 98 | */ |
| 99 | uint32_t sdhci_clk_supply(struct sdhci_host *host, uint32_t clk) |
| 100 | { |
| 101 | uint32_t div = 0; |
| 102 | uint32_t freq = 0; |
| 103 | uint16_t clk_val = 0; |
| 104 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 105 | if (clk >= host->caps.base_clk_rate) |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 106 | goto clk_ctrl; |
| 107 | |
| 108 | /* As per the sd spec div should be a multiplier of 2 */ |
| 109 | for (div = 2; div < SDHCI_CLK_MAX_DIV; div += 2) { |
| 110 | freq = host->caps.base_clk_rate / div; |
| 111 | if (freq <= clk) |
| 112 | break; |
| 113 | } |
| 114 | |
| 115 | div >>= 1; |
| 116 | |
| 117 | clk_ctrl: |
| 118 | /* As per the sdhci spec 3.0, bits 6-7 of the clock |
| 119 | * control registers will be mapped to bit 8-9, to |
| 120 | * support a 10 bit divider value. |
| 121 | * This is needed when the divider value overflows |
| 122 | * the 8 bit range. |
| 123 | */ |
| 124 | clk_val = ((div & SDHCI_SDCLK_FREQ_MASK) << SDHCI_SDCLK_FREQ_SEL); |
| 125 | clk_val |= ((div & SDHC_SDCLK_UP_BIT_MASK) >> SDHCI_SDCLK_FREQ_SEL) |
| 126 | << SDHCI_SDCLK_UP_BIT_SEL; |
| 127 | |
| 128 | clk_val |= SDHCI_INT_CLK_EN; |
| 129 | REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); |
| 130 | |
| 131 | /* Check for clock stable */ |
| 132 | while (!(REG_READ16(host, SDHCI_CLK_CTRL_REG) & SDHCI_CLK_STABLE)); |
| 133 | |
| 134 | /* Now clock is stable, enable it */ |
| 135 | clk_val = REG_READ16(host, SDHCI_CLK_CTRL_REG); |
| 136 | clk_val |= SDHCI_CLK_EN; |
| 137 | REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); |
| 138 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 139 | host->cur_clk_rate = clk; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | /* |
| 145 | * Function: sdhci stop sdcc clock |
| 146 | * Arg : Host structure |
| 147 | * Return : 0 on Success, 1 on Failure |
| 148 | * Flow: : 1. Stop the clock |
| 149 | */ |
| 150 | static uint32_t sdhci_stop_sdcc_clk(struct sdhci_host *host) |
| 151 | { |
| 152 | uint32_t reg; |
| 153 | |
| 154 | reg = REG_READ32(host, SDHCI_PRESENT_STATE_REG); |
| 155 | |
| 156 | if (reg & (SDHCI_CMD_ACT | SDHCI_DAT_ACT)) { |
| 157 | dprintf(CRITICAL, "Error: SDCC command & data line are active\n"); |
| 158 | return 1; |
| 159 | } |
| 160 | |
| 161 | REG_WRITE16(host, SDHCI_CLK_DIS, SDHCI_CLK_CTRL_REG); |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * Function: sdhci change frequency |
| 168 | * Arg : Host structure & clock value |
| 169 | * Return : 0 on Success, 1 on Failure |
| 170 | * Flow: : 1. Stop the clock |
| 171 | * 2. Star the clock with new frequency |
| 172 | */ |
| 173 | static uint32_t sdhci_change_freq_clk(struct sdhci_host *host, uint32_t clk) |
| 174 | { |
| 175 | if (sdhci_stop_sdcc_clk(host)) { |
| 176 | dprintf(CRITICAL, "Error: Card is busy, cannot change frequency\n"); |
| 177 | return 1; |
| 178 | } |
| 179 | |
| 180 | if (sdhci_clk_supply(host, clk)) { |
| 181 | dprintf(CRITICAL, "Error: cannot change frequency\n"); |
| 182 | return 1; |
| 183 | } |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Function: sdhci set bus power |
| 190 | * Arg : Host structure |
| 191 | * Return : None |
| 192 | * Flow: : 1. Set the voltage |
| 193 | * 2. Set the sd power control register |
| 194 | */ |
| 195 | static void sdhci_set_bus_power_on(struct sdhci_host *host) |
| 196 | { |
| 197 | uint8_t voltage; |
| 198 | |
| 199 | voltage = host->caps.voltage; |
| 200 | |
| 201 | voltage <<= SDHCI_BUS_VOL_SEL; |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 202 | REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 203 | |
| 204 | voltage |= SDHCI_BUS_PWR_EN; |
| 205 | |
| 206 | REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); |
| 207 | |
| 208 | } |
| 209 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 210 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 211 | /* |
| 212 | * Function: sdhci set SDR mode |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 213 | * Arg : Host structure, UHS mode |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 214 | * Return : None |
| 215 | * Flow: : 1. Disable the clock |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 216 | * 2. Enable UHS mode |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 217 | * 3. Enable the clock |
| 218 | * Details : SDR50/SDR104 mode is nothing but HS200 |
| 219 | * mode SDCC spec refers to it as SDR mode |
| 220 | * & emmc spec refers as HS200 mode. |
| 221 | */ |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 222 | void sdhci_set_uhs_mode(struct sdhci_host *host, uint32_t mode) |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 223 | { |
| 224 | uint16_t clk; |
| 225 | uint16_t ctrl = 0; |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 226 | uint32_t clk_val = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 227 | |
| 228 | /* Disable the clock */ |
| 229 | clk = REG_READ16(host, SDHCI_CLK_CTRL_REG); |
| 230 | clk &= ~SDHCI_CLK_EN; |
| 231 | REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG); |
| 232 | |
| 233 | ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 234 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 235 | ctrl &= ~SDHCI_UHS_MODE_MASK; |
| 236 | |
| 237 | /* Enable SDR50/SDR104/DDR50 mode */ |
| 238 | switch (mode) |
| 239 | { |
| 240 | case SDHCI_SDR104_MODE: |
| 241 | ctrl |= SDHCI_SDR104_MODE_EN; |
| 242 | clk_val = SDHCI_CLK_200MHZ; |
| 243 | break; |
| 244 | case SDHCI_SDR50_MODE: |
| 245 | ctrl |= SDHCI_SDR50_MODE_EN; |
| 246 | clk_val = SDHCI_CLK_100MHZ; |
| 247 | break; |
| 248 | case SDHCI_DDR50_MODE: |
| 249 | ctrl |= SDHCI_DDR50_MODE_EN; |
| 250 | clk_val = SDHCI_CLK_50MHZ; |
| 251 | break; |
| 252 | case SDHCI_SDR25_MODE: |
| 253 | ctrl |= SDHCI_SDR25_MODE_EN; |
| 254 | clk_val = SDHCI_CLK_50MHZ; |
| 255 | break; |
| 256 | case SDHCI_SDR12_MODE_EN: |
| 257 | ctrl |= SDHCI_SDR12_MODE_EN; |
| 258 | clk_val = SDHCI_CLK_25MHZ; |
| 259 | break; |
| 260 | default: |
| 261 | dprintf(CRITICAL, "Error: Invalid UHS mode: %x\n", mode); |
| 262 | ASSERT(0); |
| 263 | }; |
| 264 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 265 | REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG); |
| 266 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 267 | /* |
| 268 | * SDHC spec does not have matching UHS mode |
| 269 | * So we use Vendor specific registers to enable |
| 270 | * HS400 mode |
| 271 | */ |
| 272 | sdhci_msm_set_mci_clk(host); |
| 273 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 274 | /* Run the clock back */ |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 275 | sdhci_clk_supply(host, clk_val); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | /* |
| 279 | * Function: sdhci set adma mode |
| 280 | * Arg : Host structure |
| 281 | * Return : None |
| 282 | * Flow: : Set adma mode |
| 283 | */ |
| 284 | static void sdhci_set_adma_mode(struct sdhci_host *host) |
| 285 | { |
| 286 | /* Select 32 Bit ADMA2 type */ |
| 287 | REG_WRITE8(host, SDHCI_ADMA_32BIT, SDHCI_HOST_CTRL1_REG); |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * Function: sdhci set bus width |
| 292 | * Arg : Host & width |
| 293 | * Return : 0 on Sucess, 1 on Failure |
| 294 | * Flow: : Set the bus width for controller |
| 295 | */ |
| 296 | uint8_t sdhci_set_bus_width(struct sdhci_host *host, uint16_t width) |
| 297 | { |
| 298 | uint16_t reg = 0; |
| 299 | |
| 300 | reg = REG_READ8(host, SDHCI_HOST_CTRL1_REG); |
| 301 | |
| 302 | switch(width) { |
| 303 | case DATA_BUS_WIDTH_8BIT: |
| 304 | width = SDHCI_BUS_WITDH_8BIT; |
| 305 | break; |
| 306 | case DATA_BUS_WIDTH_4BIT: |
| 307 | width = SDHCI_BUS_WITDH_4BIT; |
| 308 | break; |
| 309 | case DATA_BUS_WIDTH_1BIT: |
| 310 | width = SDHCI_BUS_WITDH_1BIT; |
| 311 | break; |
| 312 | default: |
| 313 | dprintf(CRITICAL, "Bus width is invalid: %u\n", width); |
| 314 | return 1; |
| 315 | } |
| 316 | |
| 317 | REG_WRITE8(host, (reg | width), SDHCI_HOST_CTRL1_REG); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * Function: sdhci command err status |
| 324 | * Arg : Host structure |
| 325 | * Return : 0 on Sucess, 1 on Failure |
| 326 | * Flow: : Look for error status |
| 327 | */ |
| 328 | static uint8_t sdhci_cmd_err_status(struct sdhci_host *host) |
| 329 | { |
| 330 | uint32_t err; |
| 331 | |
| 332 | err = REG_READ16(host, SDHCI_ERR_INT_STS_REG); |
| 333 | |
| 334 | if (err & SDHCI_CMD_TIMEOUT_MASK) { |
| 335 | dprintf(CRITICAL, "Error: Command timeout error\n"); |
| 336 | return 1; |
| 337 | } else if (err & SDHCI_CMD_CRC_MASK) { |
| 338 | dprintf(CRITICAL, "Error: Command CRC error\n"); |
| 339 | return 1; |
| 340 | } else if (err & SDHCI_CMD_END_BIT_MASK) { |
| 341 | dprintf(CRITICAL, "Error: CMD end bit error\n"); |
| 342 | return 1; |
| 343 | } else if (err & SDHCI_CMD_IDX_MASK) { |
| 344 | dprintf(CRITICAL, "Error: Command Index error\n"); |
| 345 | return 1; |
| 346 | } else if (err & SDHCI_DAT_TIMEOUT_MASK) { |
| 347 | dprintf(CRITICAL, "Error: DATA time out error\n"); |
| 348 | return 1; |
| 349 | } else if (err & SDHCI_DAT_CRC_MASK) { |
| 350 | dprintf(CRITICAL, "Error: DATA CRC error\n"); |
| 351 | return 1; |
| 352 | } else if (err & SDHCI_DAT_END_BIT_MASK) { |
| 353 | dprintf(CRITICAL, "Error: DATA end bit error\n"); |
| 354 | return 1; |
| 355 | } else if (err & SDHCI_CUR_LIM_MASK) { |
| 356 | dprintf(CRITICAL, "Error: Current limit error\n"); |
| 357 | return 1; |
| 358 | } else if (err & SDHCI_AUTO_CMD12_MASK) { |
| 359 | dprintf(CRITICAL, "Error: Auto CMD12 error\n"); |
| 360 | return 1; |
| 361 | } else if (err & SDHCI_ADMA_MASK) { |
| 362 | dprintf(CRITICAL, "Error: ADMA error\n"); |
| 363 | return 1; |
| 364 | } |
| 365 | |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * Function: sdhci command complete |
| 371 | * Arg : Host & command structure |
| 372 | * Return : 0 on Sucess, 1 on Failure |
| 373 | * Flow: : 1. Check for command complete |
| 374 | * 2. Check for transfer complete |
| 375 | * 3. Get the command response |
| 376 | * 4. Check for errors |
| 377 | */ |
| 378 | static uint8_t sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd) |
| 379 | { |
| 380 | uint8_t i; |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 381 | uint8_t ret = 0; |
| 382 | uint8_t need_reset = 0; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 383 | uint32_t retry = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 384 | uint32_t int_status; |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 385 | uint32_t trans_complete = 0; |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 386 | uint32_t err_status; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 387 | |
| 388 | do { |
| 389 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
| 390 | int_status &= SDHCI_INT_STS_CMD_COMPLETE; |
| 391 | |
| 392 | if (int_status == SDHCI_INT_STS_CMD_COMPLETE) |
| 393 | break; |
| 394 | |
| 395 | retry++; |
| 396 | udelay(500); |
| 397 | if (retry == SDHCI_MAX_CMD_RETRY) { |
| 398 | dprintf(CRITICAL, "Error: Command never completed\n"); |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 399 | ret = 1; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 400 | goto err; |
| 401 | } |
| 402 | } while(1); |
| 403 | |
| 404 | /* Command is complete, clear the interrupt bit */ |
| 405 | REG_WRITE16(host, SDHCI_INT_STS_CMD_COMPLETE, SDHCI_NRML_INT_STS_REG); |
| 406 | |
| 407 | /* Copy the command response, |
| 408 | * The valid bits for R2 response are 0-119, & but the actual response |
| 409 | * is stored in bits 8-128. We need to move 8 bits of MSB of each |
| 410 | * response to register 8 bits of LSB of next response register. |
| 411 | * As: |
| 412 | * MSB 8 bits of RESP0 --> LSB 8 bits of RESP1 |
| 413 | * MSB 8 bits of RESP1 --> LSB 8 bits of RESP2 |
| 414 | * MSB 8 bits of RESP2 --> LSB 8 bits of RESP3 |
| 415 | */ |
| 416 | if (cmd->resp_type == SDHCI_CMD_RESP_R2) { |
| 417 | for (i = 0; i < 4; i++) { |
| 418 | cmd->resp[i] = REG_READ32(host, SDHCI_RESP_REG + (i * 4)); |
| 419 | cmd->resp[i] <<= SDHCI_RESP_LSHIFT; |
| 420 | |
| 421 | if (i != 0) |
| 422 | cmd->resp[i] |= (REG_READ32(host, SDHCI_RESP_REG + ((i-1) * 4)) >> SDHCI_RESP_RSHIFT); |
| 423 | } |
| 424 | } else |
| 425 | cmd->resp[0] = REG_READ32(host, SDHCI_RESP_REG); |
| 426 | |
| 427 | retry = 0; |
| 428 | |
| 429 | /* |
| 430 | * Clear the transfer complete interrupt |
| 431 | */ |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 432 | if (cmd->data_present || cmd->resp_type == SDHCI_CMD_RESP_R1B) { |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 433 | do { |
| 434 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
| 435 | int_status &= SDHCI_INT_STS_TRANS_COMPLETE; |
| 436 | |
| 437 | if (int_status & SDHCI_INT_STS_TRANS_COMPLETE) |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 438 | { |
| 439 | trans_complete = 1; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 440 | break; |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 441 | } |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 442 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 443 | /* |
| 444 | * If we are in tuning then we need to wait until Data timeout , Data end |
| 445 | * or Data CRC error |
| 446 | */ |
| 447 | if (host->tuning_in_progress) |
| 448 | { |
| 449 | err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG); |
| 450 | if ((err_status & SDHCI_DAT_TIMEOUT_MASK) || (err_status & SDHCI_DAT_CRC_MASK)) |
| 451 | { |
| 452 | sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA)); |
| 453 | return 0; |
| 454 | } |
| 455 | } |
| 456 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 457 | retry++; |
| 458 | udelay(1000); |
| 459 | if (retry == SDHCI_MAX_TRANS_RETRY) { |
| 460 | dprintf(CRITICAL, "Error: Transfer never completed\n"); |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 461 | ret = 1; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 462 | goto err; |
| 463 | } |
| 464 | } while(1); |
| 465 | |
| 466 | /* Transfer is complete, clear the interrupt bit */ |
| 467 | REG_WRITE16(host, SDHCI_INT_STS_TRANS_COMPLETE, SDHCI_NRML_INT_STS_REG); |
| 468 | } |
| 469 | |
| 470 | err: |
| 471 | /* Look for errors */ |
| 472 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 473 | |
| 474 | if (int_status & SDHCI_ERR_INT_STAT_MASK) |
| 475 | { |
| 476 | /* |
| 477 | * As per SDHC spec transfer complete has higher priority than data timeout |
| 478 | * If both transfer complete & data timeout are set then we should ignore |
| 479 | * data timeout error. |
| 480 | * --------------------------------------------------------------------------- |
| 481 | * | Transfer complete | Data timeout error | Meaning of the Status | |
| 482 | * |--------------------------------------------------------------------------| |
| 483 | * | 0 | 0 | Interrupted by another factor | |
| 484 | * |--------------------------------------------------------------------------| |
| 485 | * | 0 | 1 | Time out occured during transfer| |
| 486 | * |--------------------------------------------------------------------------| |
| 487 | * | 1 | Don't Care | Command execution complete | |
| 488 | * -------------------------------------------------------------------------- |
| 489 | */ |
| 490 | if ((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK) && trans_complete) |
| 491 | { |
| 492 | ret = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 493 | } |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 494 | else if (sdhci_cmd_err_status(host)) |
| 495 | { |
| 496 | dprintf(CRITICAL, "Error: Command completed with errors\n"); |
| 497 | ret = 1; |
| 498 | } |
| 499 | /* Reset Command & Dat lines on error */ |
| 500 | need_reset = 1; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | /* Reset data & command line */ |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 504 | if (cmd->data_present || need_reset) |
Channagoud Kadabi | 7ad70ea | 2013-08-08 13:51:04 -0700 | [diff] [blame] | 505 | sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA)); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 506 | |
Channagoud Kadabi | 39bc2ba | 2013-09-19 13:19:49 -0700 | [diff] [blame] | 507 | return ret; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | /* |
| 511 | * Function: sdhci prep desc table |
| 512 | * Arg : Pointer data & length |
| 513 | * Return : Pointer to desc table |
| 514 | * Flow: : Prepare the adma table as per the sd spec v 3.0 |
| 515 | */ |
| 516 | static struct desc_entry *sdhci_prep_desc_table(void *data, uint32_t len) |
| 517 | { |
| 518 | struct desc_entry *sg_list; |
| 519 | uint32_t sg_len = 0; |
| 520 | uint32_t remain = 0; |
| 521 | uint32_t i; |
| 522 | uint32_t table_len = 0; |
| 523 | |
| 524 | if (len <= SDHCI_ADMA_DESC_LINE_SZ) { |
| 525 | /* Allocate only one descriptor */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 526 | sg_list = (struct desc_entry *) memalign(lcm(4, CACHE_LINE), ROUNDUP(sizeof(struct desc_entry), CACHE_LINE)); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 527 | |
| 528 | if (!sg_list) { |
| 529 | dprintf(CRITICAL, "Error allocating memory\n"); |
| 530 | ASSERT(0); |
| 531 | } |
| 532 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 533 | sg_list[0].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 534 | sg_list[0].len = (len < SDHCI_ADMA_DESC_LINE_SZ) ? len : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 535 | sg_list[0].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA |
| 536 | | SDHCI_ADMA_TRANS_END; |
| 537 | |
| 538 | arch_clean_invalidate_cache_range((addr_t)sg_list, sizeof(struct desc_entry)); |
| 539 | } else { |
| 540 | /* Calculate the number of entries in desc table */ |
| 541 | sg_len = len / SDHCI_ADMA_DESC_LINE_SZ; |
| 542 | remain = len - (sg_len * SDHCI_ADMA_DESC_LINE_SZ); |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 543 | |
| 544 | /* Allocate sg_len + 1 entries if there are remaining bytes at the end */ |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 545 | if (remain) |
| 546 | sg_len++; |
| 547 | |
| 548 | table_len = (sg_len * sizeof(struct desc_entry)); |
| 549 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 550 | sg_list = (struct desc_entry *) memalign(lcm(4, CACHE_LINE), ROUNDUP(table_len, CACHE_LINE)); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 551 | |
| 552 | if (!sg_list) { |
| 553 | dprintf(CRITICAL, "Error allocating memory\n"); |
| 554 | ASSERT(0); |
| 555 | } |
| 556 | |
| 557 | memset((void *) sg_list, 0, table_len); |
| 558 | |
| 559 | /* |
| 560 | * Prepare sglist in the format: |
| 561 | * ___________________________________________________ |
| 562 | * |Transfer Len | Transfer ATTR | Data Address | |
| 563 | * | (16 bit) | (16 bit) | (32 bit) | |
| 564 | * |_____________|_______________|_____________________| |
| 565 | */ |
| 566 | for (i = 0; i < (sg_len - 1); i++) { |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 567 | sg_list[i].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 568 | /* |
| 569 | * Length attribute is 16 bit value & max transfer size for one |
| 570 | * descriptor line is 65536 bytes, As per SD Spec3.0 'len = 0' |
| 571 | * implies 65536 bytes. Truncate the length to limit to 16 bit |
| 572 | * range. |
| 573 | */ |
| 574 | sg_list[i].len = (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 575 | sg_list[i].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA; |
| 576 | data += SDHCI_ADMA_DESC_LINE_SZ; |
| 577 | len -= SDHCI_ADMA_DESC_LINE_SZ; |
| 578 | } |
| 579 | |
| 580 | /* Fill the last entry of the table with Valid & End |
| 581 | * attributes |
| 582 | */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 583 | sg_list[sg_len - 1].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 584 | sg_list[sg_len - 1].len = (len < SDHCI_ADMA_DESC_LINE_SZ) ? len : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 585 | sg_list[sg_len - 1].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA | |
| 586 | SDHCI_ADMA_TRANS_END; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | arch_clean_invalidate_cache_range((addr_t)sg_list, table_len); |
| 590 | |
| 591 | return sg_list; |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * Function: sdhci adma transfer |
| 596 | * Arg : Host structure & command stucture |
| 597 | * Return : Pointer to desc table |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 598 | * Flow : 1. Prepare descriptor table |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 599 | * 2. Write adma register |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 600 | * 3. Write block size & block count register |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 601 | */ |
| 602 | static struct desc_entry *sdhci_adma_transfer(struct sdhci_host *host, |
| 603 | struct mmc_command *cmd) |
| 604 | { |
| 605 | uint32_t num_blks = 0; |
| 606 | uint32_t sz; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 607 | void *data; |
| 608 | struct desc_entry *adma_addr; |
| 609 | |
| 610 | |
| 611 | num_blks = cmd->data.num_blocks; |
| 612 | data = cmd->data.data_ptr; |
| 613 | |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 614 | /* |
| 615 | * Some commands send data on DAT lines which is less |
| 616 | * than SDHCI_MMC_BLK_SZ, in that case trying to read |
| 617 | * more than the data sent by the card results in data |
| 618 | * CRC errors. To avoid such errors allow data to pass |
| 619 | * the required block size, if the block size is not |
| 620 | * passed use the default value |
| 621 | */ |
| 622 | if (cmd->data.blk_sz) |
| 623 | sz = num_blks * cmd->data.blk_sz; |
| 624 | else |
| 625 | sz = num_blks * SDHCI_MMC_BLK_SZ; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 626 | |
| 627 | /* Prepare adma descriptor table */ |
| 628 | adma_addr = sdhci_prep_desc_table(data, sz); |
| 629 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 630 | /* Write adma address to adma register */ |
| 631 | REG_WRITE32(host, (uint32_t) adma_addr, SDHCI_ADM_ADDR_REG); |
| 632 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 633 | /* Write the block size */ |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 634 | if (cmd->data.blk_sz) |
| 635 | REG_WRITE16(host, cmd->data.blk_sz, SDHCI_BLKSZ_REG); |
| 636 | else |
| 637 | REG_WRITE16(host, SDHCI_MMC_BLK_SZ, SDHCI_BLKSZ_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 638 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 639 | /* |
| 640 | * Set block count in block count register |
| 641 | */ |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 642 | REG_WRITE16(host, num_blks, SDHCI_BLK_CNT_REG); |
| 643 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 644 | return adma_addr; |
| 645 | } |
| 646 | |
| 647 | /* |
| 648 | * Function: sdhci send command |
| 649 | * Arg : Host structure & command stucture |
| 650 | * Return : 0 on Success, 1 on Failure |
| 651 | * Flow: : 1. Prepare the command register |
| 652 | * 2. If data is present, prepare adma table |
| 653 | * 3. Run the command |
| 654 | * 4. Check for command results & take action |
| 655 | */ |
| 656 | uint32_t sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
| 657 | { |
| 658 | uint8_t retry = 0; |
| 659 | uint32_t resp_type = 0; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 660 | uint16_t trans_mode = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 661 | uint16_t present_state; |
| 662 | uint32_t flags; |
| 663 | struct desc_entry *sg_list = NULL; |
| 664 | |
| 665 | if (cmd->data_present) |
| 666 | ASSERT(cmd->data.data_ptr); |
| 667 | |
| 668 | /* |
| 669 | * Assert if the data buffer is not aligned to cache |
| 670 | * line size for read operations. |
| 671 | * For write operations this function assumes that |
| 672 | * the cache is already flushed by the caller. As |
| 673 | * the data buffer we receive for write operation |
| 674 | * may not be aligned to cache boundary due to |
| 675 | * certain image formats like sparse image. |
| 676 | */ |
| 677 | if (cmd->trans_mode == SDHCI_READ_MODE) |
| 678 | ASSERT(IS_CACHE_LINE_ALIGNED(cmd->data.data_ptr)); |
| 679 | |
| 680 | do { |
| 681 | present_state = REG_READ32(host, SDHCI_PRESENT_STATE_REG); |
| 682 | /* check if CMD & DAT lines are free */ |
| 683 | present_state &= SDHCI_STATE_CMD_DAT_MASK; |
| 684 | |
| 685 | if (!present_state) |
| 686 | break; |
| 687 | udelay(1000); |
| 688 | retry++; |
| 689 | if (retry == 10) { |
| 690 | dprintf(CRITICAL, "Error: CMD or DAT lines were never freed\n"); |
| 691 | return 1; |
| 692 | } |
| 693 | } while(1); |
| 694 | |
| 695 | switch(cmd->resp_type) { |
| 696 | case SDHCI_CMD_RESP_R1: |
| 697 | case SDHCI_CMD_RESP_R3: |
| 698 | case SDHCI_CMD_RESP_R6: |
| 699 | case SDHCI_CMD_RESP_R7: |
| 700 | /* Response of length 48 have 32 bits |
| 701 | * of response data stored in RESP0[0:31] |
| 702 | */ |
| 703 | resp_type = SDHCI_CMD_RESP_48; |
| 704 | break; |
| 705 | |
| 706 | case SDHCI_CMD_RESP_R2: |
| 707 | /* Response of length 136 have 120 bits |
| 708 | * of response data stored in RESP0[0:119] |
| 709 | */ |
| 710 | resp_type = SDHCI_CMD_RESP_136; |
| 711 | break; |
| 712 | |
| 713 | case SDHCI_CMD_RESP_R1B: |
| 714 | /* Response of length 48 have 32 bits |
| 715 | * of response data stored in RESP0[0:31] |
| 716 | * & set CARD_BUSY status if card is busy |
| 717 | */ |
| 718 | resp_type = SDHCI_CMD_RESP_48_BUSY; |
| 719 | break; |
| 720 | |
| 721 | case SDHCI_CMD_RESP_NONE: |
| 722 | resp_type = SDHCI_CMD_RESP_NONE; |
| 723 | break; |
| 724 | |
| 725 | default: |
| 726 | dprintf(CRITICAL, "Invalid response type for the command\n"); |
| 727 | return 1; |
| 728 | }; |
| 729 | |
| 730 | flags = (resp_type << SDHCI_CMD_RESP_TYPE_SEL_BIT); |
| 731 | flags |= (cmd->data_present << SDHCI_CMD_DATA_PRESENT_BIT); |
| 732 | flags |= (cmd->cmd_type << SDHCI_CMD_CMD_TYPE_BIT); |
| 733 | |
| 734 | /* Set the timeout value */ |
| 735 | REG_WRITE8(host, SDHCI_CMD_TIMEOUT, SDHCI_TIMEOUT_REG); |
| 736 | |
| 737 | /* Check if data needs to be processed */ |
| 738 | if (cmd->data_present) |
| 739 | sg_list = sdhci_adma_transfer(host, cmd); |
| 740 | |
| 741 | /* Write the argument 1 */ |
| 742 | REG_WRITE32(host, cmd->argument, SDHCI_ARGUMENT_REG); |
| 743 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 744 | /* Set the Transfer mode */ |
| 745 | if (cmd->data_present) |
| 746 | { |
| 747 | /* Enable DMA */ |
| 748 | trans_mode |= SDHCI_DMA_EN; |
| 749 | |
| 750 | if (cmd->trans_mode == SDHCI_MMC_READ) |
| 751 | trans_mode |= SDHCI_READ_MODE; |
| 752 | |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 753 | /* Enable auto cmd23 or cmd12 for multi block transfer |
| 754 | * based on what command card supports |
| 755 | */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 756 | if (cmd->data.num_blocks > 1) { |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 757 | if (cmd->cmd23_support) { |
| 758 | trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD23_EN | SDHCI_BLK_CNT_EN; |
| 759 | REG_WRITE32(host, cmd->data.num_blocks, SDHCI_ARG2_REG); |
| 760 | } |
| 761 | else |
| 762 | trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD12_EN | SDHCI_BLK_CNT_EN; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 763 | } |
| 764 | } |
| 765 | |
| 766 | /* Write to transfer mode register */ |
| 767 | REG_WRITE16(host, trans_mode, SDHCI_TRANS_MODE_REG); |
| 768 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 769 | /* Write the command register */ |
| 770 | REG_WRITE16(host, SDHCI_PREP_CMD(cmd->cmd_index, flags), SDHCI_CMD_REG); |
| 771 | |
| 772 | /* Command complete sequence */ |
| 773 | if (sdhci_cmd_complete(host, cmd)) |
| 774 | return 1; |
| 775 | |
| 776 | /* Invalidate the cache only for read operations */ |
| 777 | if (cmd->trans_mode == SDHCI_MMC_READ) |
| 778 | arch_invalidate_cache_range((addr_t)cmd->data.data_ptr, (cmd->data.num_blocks * SDHCI_MMC_BLK_SZ)); |
| 779 | |
| 780 | /* Free the scatter/gather list */ |
| 781 | if (sg_list) |
| 782 | free(sg_list); |
| 783 | |
| 784 | return 0; |
| 785 | } |
| 786 | |
| 787 | /* |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 788 | * Function: sdhci init |
| 789 | * Arg : Host structure |
| 790 | * Return : None |
| 791 | * Flow: : 1. Reset the controller |
| 792 | * 2. Read the capabilities register & populate the host |
| 793 | * controller capabilities for use by other functions |
| 794 | * 3. Enable the power control |
| 795 | * 4. Set initial bus width |
| 796 | * 5. Set Adma mode |
| 797 | * 6. Enable the error status |
| 798 | */ |
| 799 | void sdhci_init(struct sdhci_host *host) |
| 800 | { |
| 801 | uint32_t caps[2]; |
Channagoud Kadabi | 3f42853 | 2014-01-28 21:33:34 -0800 | [diff] [blame^] | 802 | uint8_t sdcc_version = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 803 | |
| 804 | /* Read the capabilities register & store the info */ |
| 805 | caps[0] = REG_READ32(host, SDHCI_CAPS_REG1); |
| 806 | caps[1] = REG_READ32(host, SDHCI_CAPS_REG2); |
| 807 | |
| 808 | host->caps.base_clk_rate = (caps[0] & SDHCI_CLK_RATE_MASK) >> SDHCI_CLK_RATE_BIT; |
| 809 | host->caps.base_clk_rate *= 1000000; |
| 810 | |
| 811 | /* Get the max block length for mmc */ |
| 812 | host->caps.max_blk_len = (caps[0] & SDHCI_BLK_LEN_MASK) >> SDHCI_BLK_LEN_BIT; |
| 813 | |
| 814 | /* 8 bit Bus width */ |
| 815 | if (caps[0] & SDHCI_8BIT_WIDTH_MASK) |
| 816 | host->caps.bus_width_8bit = 1; |
| 817 | |
| 818 | /* Adma support */ |
| 819 | if (caps[0] & SDHCI_BLK_ADMA_MASK) |
| 820 | host->caps.adma_support = 1; |
| 821 | |
| 822 | /* Supported voltage */ |
| 823 | if (caps[0] & SDHCI_3_3_VOL_MASK) |
| 824 | host->caps.voltage = SDHCI_VOL_3_3; |
| 825 | else if (caps[0] & SDHCI_3_0_VOL_MASK) |
| 826 | host->caps.voltage = SDHCI_VOL_3_0; |
| 827 | else if (caps[0] & SDHCI_1_8_VOL_MASK) |
| 828 | host->caps.voltage = SDHCI_VOL_1_8; |
| 829 | |
| 830 | /* DDR mode support */ |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 831 | host->caps.ddr_support = (caps[1] & SDHCI_DDR50_MODE_MASK) ? 1 : 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 832 | |
| 833 | /* SDR50 mode support */ |
| 834 | host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0; |
| 835 | |
Channagoud Kadabi | cfeee4d | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 836 | /* SDR104 mode support */ |
| 837 | host->caps.sdr104_support = (caps[1] & SDHCI_SDR104_MODE_MASK) ? 1 : 0; |
| 838 | |
Channagoud Kadabi | 3f42853 | 2014-01-28 21:33:34 -0800 | [diff] [blame^] | 839 | /* HS400 mode support: |
| 840 | * The last four bits of MCI_VERSION indicate the SDCC major version |
| 841 | * Version 0 --> SDCC4 core |
| 842 | * Version >= 1 --> SDCC5 or above core |
| 843 | */ |
| 844 | sdcc_version = ((readl(host->msm_host->pwrctl_base + MCI_VERSION)) & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT; |
| 845 | host->caps.hs400_support = (sdcc_version >= 1) ? 1 : 0; |
| 846 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 847 | /* Set bus power on */ |
| 848 | sdhci_set_bus_power_on(host); |
| 849 | |
| 850 | /* Wait for power interrupt to be handled */ |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 851 | event_wait(host->sdhc_event); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 852 | |
| 853 | /* Set bus width */ |
| 854 | sdhci_set_bus_width(host, SDHCI_BUS_WITDH_1BIT); |
| 855 | |
| 856 | /* Set Adma mode */ |
| 857 | sdhci_set_adma_mode(host); |
| 858 | |
| 859 | /* |
| 860 | * Enable error status |
| 861 | */ |
| 862 | sdhci_error_status_enable(host); |
| 863 | } |