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shuoy336dd012013-07-18 19:38:56 +08001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#include <stdint.h>
31#include <msm_panel.h>
32#include <mipi_dsi.h>
33#include <sys/types.h>
34#include <err.h>
35#include <reg.h>
36#include <debug.h>
37#include <target/display.h>
38#include <platform/iomap.h>
39
40#define WVGA_MIPI_FB_WIDTH 480
41#define WVGA_MIPI_FB_HEIGHT 800
42
43#define HX8379A_PANEL_FRAME_RATE 60
44#define HX8379A_PANEL_NUM_OF_LANES 2
45#define HX8379A_PANEL_LANE_SWAP 1
46#define HX8379A_PANEL_T_CLK_PRE 0x41b
47#define HX8379A_PANEL_T_CLK_POST 0x0
48#define HX8379A_PANEL_BPP 24
49#define HX8379A_PANEL_CLK_RATE 499000000
50
Shuo Yan46423452013-08-13 10:25:00 +080051#define MIPI_HSYNC_PULSE_WIDTH 40
52#define MIPI_HSYNC_BACK_PORCH_DCLK 100
53#define MIPI_HSYNC_FRONT_PORCH_DCLK 70
54#define MIPI_VSYNC_PULSE_WIDTH 4
55#define MIPI_VSYNC_BACK_PORCH_LINES 6
56#define MIPI_VSYNC_FRONT_PORCH_LINES 6
shuoy336dd012013-07-18 19:38:56 +080057
58static char disp_on0[8] = {
59 0x04, 0x00, 0x39, 0xC0,
60 0xB9, 0xFF, 0x83, 0x79
61};
Shuo Yan46423452013-08-13 10:25:00 +080062static char disp_on1[8] = {
63 0x03, 0x00, 0x39, 0xC0,
64 0xBA, 0x51, 0x93, 0xFF
shuoy336dd012013-07-18 19:38:56 +080065};
Shuo Yan46423452013-08-13 10:25:00 +080066static char disp_on2[24] = {
shuoy336dd012013-07-18 19:38:56 +080067 0x14, 0x00, 0x39, 0xC0,
68 0xB1, 0x00, 0x50, 0x44,
69 0xEA, 0x8D, 0x08, 0x11,
70 0x11, 0x11, 0x27, 0x2F,
71 0x9A, 0x1A, 0x42, 0x0B,
72 0x6E, 0xF1, 0x00, 0xE6
73};
Shuo Yan46423452013-08-13 10:25:00 +080074static char disp_on3[20] = {
shuoy336dd012013-07-18 19:38:56 +080075 0x0E, 0x00, 0x39, 0xC0,
76 0xB2, 0x00, 0x00, 0x3C,
77 0x08, 0x04, 0x19, 0x22,
78 0x00, 0xFF, 0x08, 0x04,
79 0x19, 0x20, 0xFF, 0xFF
80};
Shuo Yan46423452013-08-13 10:25:00 +080081static char disp_on4[36] = {
shuoy336dd012013-07-18 19:38:56 +080082 0x20, 0x00, 0x39, 0xC0,
83 0xB4, 0x82, 0x08, 0x00,
84 0x32, 0x10, 0x03, 0x32,
85 0x13, 0x70, 0x32, 0x10,
86 0x08, 0x37, 0x01, 0x28,
Shuo Yan46423452013-08-13 10:25:00 +080087 0x07, 0x37, 0x08, 0x3C,
88 0x08, 0x44, 0x44, 0x08,
shuoy336dd012013-07-18 19:38:56 +080089 0x00, 0x40, 0x08, 0x28,
90 0x08, 0x30, 0x30, 0x04
91};
Shuo Yan46423452013-08-13 10:25:00 +080092static char disp_on5[52] = {
shuoy336dd012013-07-18 19:38:56 +080093 0x30, 0x00, 0x39, 0xC0,
94 0xD5, 0x00, 0x00, 0x0A,
95 0x00, 0x01, 0x05, 0x00,
96 0x03, 0x00, 0x88, 0x88,
97 0x88, 0x88, 0x23, 0x01,
98 0x67, 0x45, 0x02, 0x13,
99 0x88, 0x88, 0x88, 0x88,
100 0x88, 0x88, 0x88, 0x88,
101 0x88, 0x88, 0x54, 0x76,
102 0x10, 0x32, 0x31, 0x20,
103 0x88, 0x88, 0x88, 0x88,
104 0x88, 0x88, 0x00, 0x00,
105 0x00, 0x00, 0x00, 0x00
106};
Shuo Yan46423452013-08-13 10:25:00 +0800107static char disp_on6[40] = {
shuoy336dd012013-07-18 19:38:56 +0800108 0x24, 0x00, 0x39, 0xC0,
109 0xE0, 0x79, 0x05, 0x0F,
110 0x14, 0x26, 0x29, 0x3F,
Shuo Yan46423452013-08-13 10:25:00 +0800111 0x2B, 0x44, 0x04, 0x0E,
shuoy336dd012013-07-18 19:38:56 +0800112 0x12, 0x15, 0x18, 0x16,
Shuo Yan46423452013-08-13 10:25:00 +0800113 0x16, 0x12, 0x15, 0x05,
shuoy336dd012013-07-18 19:38:56 +0800114 0x0F, 0x14, 0x26, 0x29,
Shuo Yan46423452013-08-13 10:25:00 +0800115 0x3F, 0x2B, 0x44, 0x04,
shuoy336dd012013-07-18 19:38:56 +0800116 0x0E, 0x12, 0x15, 0x18,
Shuo Yan46423452013-08-13 10:25:00 +0800117 0x16, 0x16, 0x12, 0x15
shuoy336dd012013-07-18 19:38:56 +0800118};
Shuo Yan46423452013-08-13 10:25:00 +0800119static char disp_on7[4] = {
shuoy336dd012013-07-18 19:38:56 +0800120 0xCC, 0x02, 0x23, 0x80,
121};
Shuo Yan46423452013-08-13 10:25:00 +0800122static char disp_on8[12] = {
shuoy336dd012013-07-18 19:38:56 +0800123 0x05, 0x00, 0x39, 0xC0,
124 0xB6, 0x00, 0x9C, 0x00,
125 0x9C, 0xFF, 0xFF, 0xFF
126};
Shuo Yan46423452013-08-13 10:25:00 +0800127static char disp_on9[4] = {
shuoy336dd012013-07-18 19:38:56 +0800128 0x11, 0x00, 0x05, 0x80
129};
Shuo Yan46423452013-08-13 10:25:00 +0800130static char disp_on10[4] = {
shuoy336dd012013-07-18 19:38:56 +0800131 0x29, 0x00, 0x05, 0x80
132};
133
134static struct mipi_dsi_cmd hx8379a_wvga_panel_video_mode_cmds[] = {
135 {sizeof(disp_on0), (char *)disp_on0},
136 {sizeof(disp_on1), (char *)disp_on1},
137 {sizeof(disp_on2), (char *)disp_on2},
138 {sizeof(disp_on3), (char *)disp_on3},
139 {sizeof(disp_on4), (char *)disp_on4},
140 {sizeof(disp_on5), (char *)disp_on5},
141 {sizeof(disp_on6), (char *)disp_on6},
142 {sizeof(disp_on7), (char *)disp_on7},
143 {sizeof(disp_on8), (char *)disp_on8},
144 {sizeof(disp_on9), (char *)disp_on9},
145 {sizeof(disp_on10), (char *)disp_on10},
shuoy336dd012013-07-18 19:38:56 +0800146};
147
148int mipi_hx8379a_video_wvga_config(void *pdata)
149{
150 int ret = NO_ERROR;
151 /* 2 Lanes -- Enables Data Lane0, 1 */
152 unsigned char lane_en = 3;
153 unsigned long low_pwr_stop_mode = 0;
154
155 /* Needed or else will have blank line at top of display */
156 unsigned char eof_bllp_pwr = 0x9;
157
158 unsigned char interleav = 0;
159 struct lcdc_panel_info *lcdc = NULL;
160 struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
161
162 if (pinfo == NULL)
163 return ERR_INVALID_ARGS;
164
165 lcdc = &(pinfo->lcdc);
166 if (lcdc == NULL)
167 return ERR_INVALID_ARGS;
168
169 ret = mdss_dsi_video_mode_config((pinfo->xres),
170 (pinfo->yres),
171 (pinfo->xres),
172 (pinfo->yres),
173 (lcdc->h_front_porch),
Shuo Yan46423452013-08-13 10:25:00 +0800174 (lcdc->h_back_porch + lcdc->h_pulse_width),
shuoy336dd012013-07-18 19:38:56 +0800175 (lcdc->v_front_porch),
Shuo Yan46423452013-08-13 10:25:00 +0800176 (lcdc->v_back_porch + lcdc->v_pulse_width),
shuoy336dd012013-07-18 19:38:56 +0800177 (lcdc->h_pulse_width),
178 (lcdc->v_pulse_width),
179 pinfo->mipi.dst_format,
180 pinfo->mipi.traffic_mode,
181 lane_en,
182 low_pwr_stop_mode,
183 eof_bllp_pwr,
184 interleav,
185 MIPI_DSI0_BASE);
186 return ret;
187}
188
189int mipi_hx8379a_video_wvga_on()
190{
191 int ret = NO_ERROR;
192 return ret;
193}
194
195int mipi_hx8379a_video_wvga_off()
196{
197 int ret = NO_ERROR;
198 return ret;
199}
200
201static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
202 /* regulator */
203 {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
204 /* timing */
Shuo Yan46423452013-08-13 10:25:00 +0800205 {0x75, 0x1A, 0x11, 0x00, 0x3D, 0x45,
206 0x15, 0x1D, 0x1C, 0x03, 0x04, 0x00},
shuoy336dd012013-07-18 19:38:56 +0800207 /* phy ctrl */
208 {0x7f, 0x00, 0x00, 0x00},
209 /* strength */
210 {0xff, 0x06},
211 /* bist */
212 {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
213 /* lane config */
214 { 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
215 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
216 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
217 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
218 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
219};
220
221void mipi_hx8379a_video_wvga_init(struct msm_panel_info *pinfo)
222{
223 if (!pinfo)
224 return;
225
226 pinfo->xres = WVGA_MIPI_FB_WIDTH;
227 pinfo->yres = WVGA_MIPI_FB_HEIGHT;
228 pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
229 pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
230 pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
231 pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
232 pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
233 pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
234 pinfo->mipi.num_of_lanes = HX8379A_PANEL_NUM_OF_LANES;
235 pinfo->mipi.frame_rate = HX8379A_PANEL_FRAME_RATE;
236
237 pinfo->type = MIPI_VIDEO_PANEL;
238 pinfo->wait_cycle = 0;
239 pinfo->bpp = HX8379A_PANEL_BPP;
240 pinfo->clk_rate = HX8379A_PANEL_CLK_RATE;
241
242 pinfo->mipi.mode = DSI_VIDEO_MODE;
243 pinfo->mipi.traffic_mode = 2;
244 pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
245 pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
246 pinfo->mipi.tx_eot_append = TRUE;
247
248 pinfo->mipi.lane_swap = HX8379A_PANEL_LANE_SWAP;
249 pinfo->mipi.t_clk_post = HX8379A_PANEL_T_CLK_POST;
250 pinfo->mipi.t_clk_pre = HX8379A_PANEL_T_CLK_PRE;
251 pinfo->mipi.panel_cmds = hx8379a_wvga_panel_video_mode_cmds;
252 pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(hx8379a_wvga_panel_video_mode_cmds);
253
254 pinfo->on = mipi_hx8379a_video_wvga_on;
255 pinfo->off = mipi_hx8379a_video_wvga_off;
256 pinfo->config = mipi_hx8379a_video_wvga_config;
257
258 return;
259};