Deepa Dinamani | eb18237 | 2013-02-04 15:53:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define mmpll0_mm_source_val 1 |
| 44 | #define mmpll1_mm_source_val 2 |
| 45 | #define mmpll3_mm_source_val 3 |
| 46 | #define gpll0_mm_source_val 5 |
| 47 | |
| 48 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 49 | |
| 50 | |
| 51 | /* Clock Operations */ |
| 52 | static struct clk_ops clk_ops_branch = |
| 53 | { |
| 54 | .enable = clock_lib2_branch_clk_enable, |
| 55 | .disable = clock_lib2_branch_clk_disable, |
| 56 | .set_rate = clock_lib2_branch_set_rate, |
| 57 | }; |
| 58 | |
| 59 | static struct clk_ops clk_ops_rcg_mnd = |
| 60 | { |
| 61 | .enable = clock_lib2_rcg_enable, |
| 62 | .set_rate = clock_lib2_rcg_set_rate, |
| 63 | }; |
| 64 | |
| 65 | static struct clk_ops clk_ops_rcg = |
| 66 | { |
| 67 | .enable = clock_lib2_rcg_enable, |
| 68 | .set_rate = clock_lib2_rcg_set_rate, |
| 69 | }; |
| 70 | |
| 71 | static struct clk_ops clk_ops_cxo = |
| 72 | { |
| 73 | .enable = cxo_clk_enable, |
| 74 | .disable = cxo_clk_disable, |
| 75 | }; |
| 76 | |
| 77 | static struct clk_ops clk_ops_pll_vote = |
| 78 | { |
| 79 | .enable = pll_vote_clk_enable, |
| 80 | .disable = pll_vote_clk_disable, |
| 81 | .auto_off = pll_vote_clk_disable, |
| 82 | .is_enabled = pll_vote_clk_is_enabled, |
| 83 | }; |
| 84 | |
| 85 | static struct clk_ops clk_ops_vote = |
| 86 | { |
| 87 | .enable = clock_lib2_vote_clk_enable, |
| 88 | .disable = clock_lib2_vote_clk_disable, |
| 89 | }; |
| 90 | |
| 91 | /* Clock Sources */ |
| 92 | static struct fixed_clk cxo_clk_src = |
| 93 | { |
| 94 | .c = { |
| 95 | .rate = 19200000, |
| 96 | .dbg_name = "cxo_clk_src", |
| 97 | .ops = &clk_ops_cxo, |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | static struct pll_vote_clk gpll0_clk_src = |
| 102 | { |
| 103 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 104 | .en_mask = BIT(0), |
| 105 | .status_reg = (void *) GPLL0_STATUS, |
| 106 | .status_mask = BIT(17), |
| 107 | .parent = &cxo_clk_src.c, |
| 108 | |
| 109 | .c = { |
| 110 | .rate = 600000000, |
| 111 | .dbg_name = "gpll0_clk_src", |
| 112 | .ops = &clk_ops_pll_vote, |
| 113 | }, |
| 114 | }; |
| 115 | |
| 116 | /* SDCC Clocks */ |
| 117 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 118 | { |
| 119 | F( 144000, cxo, 16, 3, 25), |
| 120 | F( 400000, cxo, 12, 1, 4), |
| 121 | F( 20000000, gpll0, 15, 1, 2), |
| 122 | F( 25000000, gpll0, 12, 1, 2), |
| 123 | F( 50000000, gpll0, 12, 0, 0), |
| 124 | F(100000000, gpll0, 6, 0, 0), |
| 125 | F(200000000, gpll0, 3, 0, 0), |
| 126 | F_END |
| 127 | }; |
| 128 | |
| 129 | static struct rcg_clk sdcc1_apps_clk_src = |
| 130 | { |
| 131 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 132 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 133 | .m_reg = (uint32_t *) SDCC1_M, |
| 134 | .n_reg = (uint32_t *) SDCC1_N, |
| 135 | .d_reg = (uint32_t *) SDCC1_D, |
| 136 | |
| 137 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 138 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 139 | .current_freq = &rcg_dummy_freq, |
| 140 | |
| 141 | .c = { |
| 142 | .dbg_name = "sdc1_clk", |
| 143 | .ops = &clk_ops_rcg_mnd, |
| 144 | }, |
| 145 | }; |
| 146 | |
| 147 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 148 | { |
| 149 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 150 | .parent = &sdcc1_apps_clk_src.c, |
| 151 | |
| 152 | .c = { |
| 153 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 154 | .ops = &clk_ops_branch, |
| 155 | }, |
| 156 | }; |
| 157 | |
| 158 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 159 | { |
| 160 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 161 | .has_sibling = 1, |
| 162 | |
| 163 | .c = { |
| 164 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 165 | .ops = &clk_ops_branch, |
| 166 | }, |
| 167 | }; |
| 168 | |
| 169 | /* UART Clocks */ |
| 170 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 171 | { |
| 172 | F( 3686400, gpll0, 1, 96, 15625), |
| 173 | F( 7372800, gpll0, 1, 192, 15625), |
| 174 | F(14745600, gpll0, 1, 384, 15625), |
| 175 | F(16000000, gpll0, 5, 2, 15), |
| 176 | F(19200000, cxo, 1, 0, 0), |
| 177 | F(24000000, gpll0, 5, 1, 5), |
| 178 | F(32000000, gpll0, 1, 4, 75), |
| 179 | F(40000000, gpll0, 15, 0, 0), |
| 180 | F(46400000, gpll0, 1, 29, 375), |
| 181 | F(48000000, gpll0, 12.5, 0, 0), |
| 182 | F(51200000, gpll0, 1, 32, 375), |
| 183 | F(56000000, gpll0, 1, 7, 75), |
| 184 | F(58982400, gpll0, 1, 1536, 15625), |
| 185 | F(60000000, gpll0, 10, 0, 0), |
| 186 | F_END |
| 187 | }; |
| 188 | |
| 189 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
| 190 | { |
| 191 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 192 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 193 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 194 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 195 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
| 196 | |
| 197 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 198 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 199 | .current_freq = &rcg_dummy_freq, |
| 200 | |
| 201 | .c = { |
| 202 | .dbg_name = "blsp1_uart3_apps_clk", |
| 203 | .ops = &clk_ops_rcg_mnd, |
| 204 | }, |
| 205 | }; |
| 206 | |
| 207 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
| 208 | { |
| 209 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 210 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 211 | |
| 212 | .c = { |
| 213 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 214 | .ops = &clk_ops_branch, |
| 215 | }, |
| 216 | }; |
| 217 | |
| 218 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 219 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 220 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 221 | .en_mask = BIT(17), |
| 222 | |
| 223 | .c = { |
| 224 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 225 | .ops = &clk_ops_vote, |
| 226 | }, |
| 227 | }; |
| 228 | |
| 229 | /* USB Clocks */ |
| 230 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 231 | { |
| 232 | F(75000000, gpll0, 8, 0, 0), |
| 233 | F_END |
| 234 | }; |
| 235 | |
| 236 | static struct rcg_clk usb_hs_system_clk_src = |
| 237 | { |
| 238 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 239 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 240 | |
| 241 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 242 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 243 | .current_freq = &rcg_dummy_freq, |
| 244 | |
| 245 | .c = { |
| 246 | .dbg_name = "usb_hs_system_clk", |
| 247 | .ops = &clk_ops_rcg, |
| 248 | }, |
| 249 | }; |
| 250 | |
| 251 | static struct branch_clk gcc_usb_hs_system_clk = |
| 252 | { |
| 253 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 254 | .parent = &usb_hs_system_clk_src.c, |
| 255 | |
| 256 | .c = { |
| 257 | .dbg_name = "gcc_usb_hs_system_clk", |
| 258 | .ops = &clk_ops_branch, |
| 259 | }, |
| 260 | }; |
| 261 | |
| 262 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 263 | { |
| 264 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 265 | .has_sibling = 1, |
| 266 | |
| 267 | .c = { |
| 268 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 269 | .ops = &clk_ops_branch, |
| 270 | }, |
| 271 | }; |
| 272 | |
| 273 | /* Clock lookup table */ |
| 274 | static struct clk_lookup msm_clocks_8226[] = |
| 275 | { |
| 276 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 277 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 278 | |
| 279 | CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c), |
| 280 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
| 281 | |
| 282 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 283 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 284 | }; |
| 285 | |
| 286 | void platform_clock_init(void) |
| 287 | { |
| 288 | clk_init(msm_clocks_8226, ARRAY_SIZE(msm_clocks_8226)); |
| 289 | } |