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gerrit-public.fairphone.software / kernel / lk / 4e5f9f7d977efaf0716f134cc38e0565ceab315e / . / target / msm7630_surf / panel.c
blob: 1683a78e6fd63066e4182d85d81ba772dd1ca8a1 [file] [log] [blame]
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]1/*
2 * Copyright (c) 2007, Google Inc.
3 * All rights reserved.
4 *
5 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Code Aurora nor
17 * the names of its contributors may be used to endorse or promote
18 * products derived from this software without specific prior written
19 * permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
28 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
Chandan Uddaraju8adde5a2009-11-17 11:31:28 -0800[diff] [blame]34
35#include <debug.h>
36#include <dev/gpio.h>
37#include <kernel/thread.h>
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]38#include <gpio_hw.h>
39
40#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
41
42#if DISPLAY_TYPE_MDDI
Chandan Uddaraju8adde5a2009-11-17 11:31:28 -0800[diff] [blame]43#include <platform/mddi.h>
44
45#define MDDI_CLIENT_CORE_BASE 0x108000
46#define LCD_CONTROL_BLOCK_BASE 0x110000
47#define SPI_BLOCK_BASE 0x120000
48#define I2C_BLOCK_BASE 0x130000
49#define PWM_BLOCK_BASE 0x140000
50#define GPIO_BLOCK_BASE 0x150000
51#define SYSTEM_BLOCK1_BASE 0x160000
52#define SYSTEM_BLOCK2_BASE 0x170000
53
54
55#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
56#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
57#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
58#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
59#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
60#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
61#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
62#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
63#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
64#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
65#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
66#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
67#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
68#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
69#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
70#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
71#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
72#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
73#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
74#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
75#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
76#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
77
78
79#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
80#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
81#define START (LCD_CONTROL_BLOCK_BASE|0x08)
82#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
83#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
84#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
85#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
86#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
87#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
88#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
89#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
90
91#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
92#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
93#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
94#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
95#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
96#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
97#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
98#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
99#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
100#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
101#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
102#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
103#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
104#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
105#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
106#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
107#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
108#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
109#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
110#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
111#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
112#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
113#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
114#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
115
116#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
117
118#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
119#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
120#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
121
122
123#define SSICTL (SPI_BLOCK_BASE|0x00)
124#define SSITIME (SPI_BLOCK_BASE|0x04)
125#define SSITX (SPI_BLOCK_BASE|0x08)
126#define SSIRX (SPI_BLOCK_BASE|0x0C)
127#define SSIINTC (SPI_BLOCK_BASE|0x10)
128#define SSIINTS (SPI_BLOCK_BASE|0x14)
129#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
130#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
131#define SSIID (SPI_BLOCK_BASE|0x20)
132
133
134#define I2CSETUP (I2C_BLOCK_BASE|0x00)
135#define I2CCTRL (I2C_BLOCK_BASE|0x04)
136
137
138#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
139#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
140#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
141#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
142#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
143#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
144#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
145#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
146#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
147#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
148#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
149#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
150#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
151#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
152#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
153#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
154#define TIMERITCR (PWM_BLOCK_BASE|0x60)
155#define TIMERITOP (PWM_BLOCK_BASE|0x64)
156#define PWMCR (PWM_BLOCK_BASE|0x68)
157#define PWMID (PWM_BLOCK_BASE|0x6C)
158#define PWMMON (PWM_BLOCK_BASE|0x70)
159
160
161#define GPIODATA (GPIO_BLOCK_BASE|0x00)
162#define GPIODIR (GPIO_BLOCK_BASE|0x04)
163#define GPIOIS (GPIO_BLOCK_BASE|0x08)
164#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
165#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
166#define GPIOIE (GPIO_BLOCK_BASE|0x14)
167#define GPIORIS (GPIO_BLOCK_BASE|0x18)
168#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
169#define GPIOIC (GPIO_BLOCK_BASE|0x20)
170#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
171#define GPIOPC (GPIO_BLOCK_BASE|0x28)
172
173#define GPIOID (GPIO_BLOCK_BASE|0x30)
174
175
176#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
177#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
178#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
179#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
180#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
181
182struct init_table {
183 unsigned int reg;
184 unsigned int val;
185};
186
187static struct init_table toshiba_480x640_init_table[] = {
188 { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
189 { DPSET1, 0x00000113 }, // # MDC.DPSET1
190 { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
191 { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
192 { 0, 14 }, // wait_ms(14);
193 { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
194 { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
195 { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
196 { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
197 { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
198 { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
199 { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
200 { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
201 { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
202 { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
203 { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
204 { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
205 { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
206 { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
207 { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
208 { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
209 //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
210#if 0
211 { PWM0OFF, 0x00001387 }, // SURF 100% backlight
212 { PWM0OFF, 0x00000000 }, // FFA 100% backlight
213#endif
214 { PWM0OFF, 0x000009C3 }, // 50% BL
215 { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
216 { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
217 //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
218 { PWM1OFF, 0x00001387 },
219 { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
220 { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
221 { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
222 { 0, 1 }, // wait_ms(1);
223 { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
224 { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
225 { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
226
227 { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
228 { 0, 1 }, // wait_ms(1);
229 { SSITX, 0x00000000 }, // # SPI.SSITX
230 { 0, 1 }, // wait_ms(1);
231 { SSITX, 0x00000000 }, // # SPI.SSITX
232 { 0, 1 }, // wait_ms(1);
233 { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
234 { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
235 { SSITX, 0x00080036 }, // # Command setting of SPI block
236 { SSITX, 0x00000100 }, // # Memory access control
237 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
238 { SSITX, 0x000800BB }, // # Command setting of SPI block
239 { SSITX, 0x00000100 }, // # Display mode setup(2)
240 { SSITX, 0x0008003A }, // # Command setting of SPI block
241 { SSITX, 0x00000160 }, // # RGB Interface data format
242 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
243 { SSITX, 0x000800BF }, // # Command setting of SPI block
244 { SSITX, 0x00000100 }, // # Drivnig method
245 { SSITX, 0x000800B1 }, // # Command setting of SPI block
246 { SSITX, 0x0000015D }, // # Booster operation setup
247 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
248 { SSITX, 0x000800B2 }, // # Command setting of SPI block
249 { SSITX, 0x00000133 }, // # Booster mode setup
250 { SSITX, 0x000800B3 }, // # Command setting of SPI block
251 { SSITX, 0x00000122 }, // # Booster frequencies setup
252 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
253 { SSITX, 0x000800B4 }, // # Command setting of SPI block
254 { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
255 { SSITX, 0x000800B5 }, // # Command setting of SPI block
256 { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
257 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
258 { SSITX, 0x000800B6 }, // # Command setting of SPI block
259 { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
260 { SSITX, 0x000800B7 }, // # Command setting of SPI block
261 { SSITX, 0x00000103 }, // # Configure an external display signal
262 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
263 { SSITX, 0x000800B9 }, // # Command setting of SPI block
264 { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
265 { SSITX, 0x000800BD }, // # Command setting of SPI block
266 { SSITX, 0x00000102 }, // # ASW signal control
267 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
268 { SSITX, 0x000800BE }, // # Command setting of SPI block
269 { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
270 { SSITX, 0x000800C0 }, // # Command setting of SPI block
271 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
272 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
273 { SSITX, 0x000800C1 }, // # Command setting of SPI block
274 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
275 { SSITX, 0x000800C2 }, // # Command setting of SPI block
276 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
277 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
278 { SSITX, 0x000800C3 }, // # Command setting of SPI block
279 { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
280 { SSITX, 0x0000010A }, //
281 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
282 { SSITX, 0x000800C4 }, // # Command setting of SPI block
283 { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
284 { SSITX, 0x00000160 }, //
285 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
286 { SSITX, 0x000800C5 }, // # Command setting of SPI block
287 { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
288 { SSITX, 0x00000160 }, //
289 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
290 { SSITX, 0x000800C6 }, // # Command setting of SPI block
291 { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
292 { SSITX, 0x00000160 }, //
293 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
294 { SSITX, 0x000800C7 }, // # Command setting of SPI block
295 { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
296 { SSITX, 0x00000143 }, //
297 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
298 { SSITX, 0x000800C8 }, // # Command setting of SPI block
299 { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
300 { SSITX, 0x000800C9 }, // # Command setting of SPI block
301 { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
302 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
303 { SSITX, 0x000800CA }, // # Command setting of SPI block
304 { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
305 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
306 { SSITX, 0x000800EC }, // # Command setting of SPI block
307 { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
308 { SSITX, 0x00000118 }, //
309 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
310 { SSITX, 0x000800CF }, // # Command setting of SPI block
311 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
312 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
313 { SSITX, 0x000800D0 }, // # Command setting of SPI block
314 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
315 { SSITX, 0x00000104 }, //
316 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
317 { SSITX, 0x000800D1 }, // # Command setting of SPI block
318 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
319 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
320 { SSITX, 0x000800D2 }, // # Command setting of SPI block
321 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
322 { SSITX, 0x0000013A }, //
323 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
324 { SSITX, 0x000800D3 }, // # Command setting of SPI block
325 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
326 { SSITX, 0x0000013A }, //
327 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
328 { SSITX, 0x000800D4 }, // # Command setting of SPI block
329 { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
330 { SSITX, 0x0000016E }, //
331 { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
332 { SSITX, 0x000800D5 }, // # Command setting of SPI block
333 { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
334 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
335 { SSITX, 0x000800ED }, // # Command setting of SPI block
336 { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
337 { SSITX, 0x0000010A }, //
338 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
339 { SSITX, 0x000800D6 }, // # Command setting of SPI block
340 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
341 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
342 { SSITX, 0x000800D7 }, // # Command setting of SPI block
343 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
344 { SSITX, 0x0000010A }, //
345 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
346 { SSITX, 0x000800D8 }, // # Command setting of SPI block
347 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
348 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
349 { SSITX, 0x000800D9 }, // # Command setting of SPI block
350 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
351 { SSITX, 0x00000114 }, //
352 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
353 { SSITX, 0x000800DE }, // # Command setting of SPI block
354 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
355 { SSITX, 0x00000114 }, //
356 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
357 { SSITX, 0x000800DF }, // # Command setting of SPI block
358 { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
359 { SSITX, 0x0000013F }, //
360 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
361 { SSITX, 0x000800E0 }, // # Command setting of SPI block
362 { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
363 { SSITX, 0x000800E2 }, // # Command setting of SPI block
364 { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
365 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
366 { SSITX, 0x000800E3 }, // # Command setting of SPI block
367 { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
368 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
369 { SSITX, 0x000800E4 }, // # Command setting of SPI block
370 { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
371 { SSITX, 0x00000103 }, //
372 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
373 { SSITX, 0x000800E5 }, // # Command setting of SPI block
374 { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
375 { SSITX, 0x00000104 }, //
376 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
377 { SSITX, 0x000800E6 }, // # Command setting of SPI block
378 { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
379 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
380 { SSITX, 0x000800E7 }, // # Command setting of SPI block
381 { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
382 { SSITX, 0x0000010A }, //
383 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
384 { SSITX, 0x000800E8 }, // # Command setting of SPI block
385 { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
386
387
388 { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
389 { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
390 { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
391 { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
392 { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
393 { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
394 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
395 { ASY_DATB, 0x00000001 }, // # Oscillator start
396 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
397 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
398 { 0, 10 }, // wait_ms(10);
399 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
400 { ASY_DATB, 0x80000000 }, //
401 { ASY_DATC, 0x80000000 }, //
402 { ASY_DATD, 0x80000000 }, //
403 { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
404 { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
405 { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
406 { ASY_DATB, 0x00004005 }, // # LCD driver control
407 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
408 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
409 { 0, 20 }, // wait_ms(20);
410 { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
411 { ASY_DATB, 0x00000000 }, // # LTPS I/F control
412 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
413 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
414
415 { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
416 { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
417
418 /******************************/
419
420 { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
421 { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
422
423 { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
424 { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
425 { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
426 { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
427 { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
428 { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
429 { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
430 { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
431 { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
432 { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
433 { HSW, 0x00000003 }, // LCD.HSW
434 { HDE_START, 0x00000007 }, // LCD.HDE_START
435 { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
436 { VCYCLE, 0x00000285 }, // LCD.VCYCLE
437 { VSW, 0x00000001 }, // LCD.VSW
438 { VDE_START, 0x00000003 }, // LCD.VDE_START
439 { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
440
441 { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
442
443 { 0, 10 }, // wait_ms( 10 );
444 { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
445 { SSITX, 0x00000180 }, // Display data setup
446 { SSITX, 0x0008003B }, // Command setting of SPI block
447 { SSITX, 0x00000100 }, // Quad Data configuration - VGA
448 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
449 { SSITX, 0x000800B0 }, // Command setting of SPI block
450 { SSITX, 0x00000116 }, // Power supply ON/OFF control
451 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
452 { SSITX, 0x000800B8 }, // Command setting of SPI block
453 { SSITX, 0x000801FF }, // Output control
454 { SSITX, 0x000001F5 },
455 { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
456 { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
457 { SSITX, 0x00000029 }, // Display on (Command only)
458
459 { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
460
461 { 0, 0 }
462};
463
464static void _panel_init(struct init_table *init_table)
465{
466 unsigned n;
467
468 dprintf(INFO, "panel_init()\n");
469
470 n = 0;
471 while (init_table[n].reg != 0 || init_table[n].val != 0) {
472 if (init_table[n].reg != 0)
473 mddi_remote_write(init_table[n].val, init_table[n].reg);
474 else
475 thread_sleep(init_table[n].val);//mdelay(init_table[n].val);
476 n++;
477 }
478
479 dprintf(INFO, "panel_init() done\n");
480}
481
482void panel_init(struct mddi_client_caps *client_caps)
483{
484 switch(client_caps->manufacturer_name) {
485 case 0xd263: // Toshiba
486 dprintf(INFO, "Found Toshiba panel\n");
487 _panel_init(toshiba_480x640_init_table);
488 break;
489 case 0x4474: //??
490 if (client_caps->product_code == 0xc065)
491 dprintf(INFO, "Found WVGA panel\n");
492 break;
493 }
494}
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]495#endif //mddi
Chandan Uddaraju8adde5a2009-11-17 11:31:28 -0800[diff] [blame]496
497void panel_poweron(void)
498{
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]499#if DISPLAY_TYPE_MDDI
Chandan Uddaraju8adde5a2009-11-17 11:31:28 -0800[diff] [blame]500 gpio_set(88, 0);
501 gpio_config(88, GPIO_OUTPUT);
502 thread_sleep(1); //udelay(10);
503 gpio_set(88, 1);
504 thread_sleep(10); //mdelay(10);
505
506 //mdelay(1000); // uncomment for second stage boot
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]507#elif DISPLAY_TYPE_LCDC
508 panel_backlight(1);
509 lcdc_on();
510#endif
Chandan Uddaraju8adde5a2009-11-17 11:31:28 -0800[diff] [blame]511}
512
513void panel_backlight(int on)
Shashank Mittal37040832010-08-24 15:57:57 -0700[diff] [blame]514{
515 unsigned char reg_data = 0xA0;
516 if(on)
517 pmic_write(0x132, reg_data);
518 else
519 pmic_write(0x132, 0);
520}
521
522static unsigned wega_reset_gpio =
523GPIO_CFG(180, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA);
524
525#define LDO12_CNTRL 0x015
526#define LDO15_CNTRL 0x089
527#define LDO16_CNTRL 0x08A
528#define LDO20_CNTRL 0x11F // PM8058 only
529#define LDO_LOCAL_EN_BMSK 0x80
530
531static int display_common_power(int on)
532{
533 int rc = 0, flag_on = !!on;
534 static int display_common_power_save_on;
535 unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8;
536 if (display_common_power_save_on == flag_on)
537 return 0;
538
539 display_common_power_save_on = flag_on;
540
541 if (on) {
542 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
543 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE);
544 if (rc) {
545 return rc;
546 }
547
548 gpio_set(180, 0); /* bring reset line low to hold reset*/
549 }
550
551 // Set power for WEGA chip.
552 // Set LD020 to 1.5V
553 pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK);
554 mdelay(5);
555
556 // Set LD012 to 1.8V
557 pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK);
558 mdelay(5);
559
560 // Set LD016 to 2.6V
561 pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK);
562 mdelay(5);
563
564 // Set LD015 to 3.0V
565 pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK);
566 mdelay(5);
567
568 gpio_set(180, 1); /* bring reset line high */
569 mdelay(10); /* 10 msec before IO can be accessed */
570 if (rc) {
571 return rc;
572 }
573
574 return rc;
575}
576
577#if DISPLAY_TYPE_LCDC
578static struct msm_gpio lcd_panel_gpios[] = {
579 { GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" },
580 { GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" },
581 { GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" },
582 { GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" }
583};
584
585int lcdc_toshiba_panel_power(int on)
586{
587 int rc, i;
588 struct msm_gpio *gp;
589
590 rc = display_common_power(on);
591 if (rc < 0) {
592 return rc;
593 }
594
595 if (on) {
596 rc = platform_gpios_enable(lcd_panel_gpios,
597 ARRAY_SIZE(lcd_panel_gpios));
598 if(rc)
599 {
600 return rc;
601 }
602 } else { /* off */
603 gp = lcd_panel_gpios;
604 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
605 /* ouput low */
606 gpio_set(GPIO_PIN(gp->gpio_cfg), 0);
607 gp++;
608 }
609 }
610
611 return rc;
612}
613
614#define SPI_SCLK 45
615#define SPI_CS 46
616#define SPI_MOSI 47
617#define SPI_MISO 48
618
619static void toshiba_spi_write_byte(char dc, unsigned char data)
620{
621 unsigned bit;
622 int bnum;
623
624 gpio_set(SPI_SCLK, 0); /* clk low */
625 /* dc: 0 for command, 1 for parameter */
626 gpio_set(SPI_MOSI, dc);
627 mdelay(1); /* at least 20 ns */
628 gpio_set(SPI_SCLK, 1); /* clk high */
629 mdelay(1); /* at least 20 ns */
630 bnum = 8; /* 8 data bits */
631 bit = 0x80;
632 while (bnum) {
633 gpio_set(SPI_SCLK, 0); /* clk low */
634 if (data & bit)
635 gpio_set(SPI_MOSI, 1);
636 else
637 gpio_set(SPI_MOSI, 0);
638 mdelay(1);
639 gpio_set(SPI_SCLK, 1); /* clk high */
640 mdelay(1);
641 bit >>= 1;
642 bnum--;
643 }
644}
645
646static int toshiba_spi_write (char cmd, unsigned data, int num)
647{
648 char *bp;
649 gpio_set(SPI_CS, 1); /* cs high */
650
651 /* command byte first */
652 toshiba_spi_write_byte(0, cmd);
653
654 /* followed by parameter bytes */
655 if (num) {
656 bp = (char *)&data;;
657 bp += (num - 1);
658 while (num) {
659 toshiba_spi_write_byte(1, *bp);
660 num--;
661 bp--;
662 }
663 }
664 gpio_set(SPI_CS, 0); /* cs low */
665 mdelay(1);
666 return 0;
667}
668
669
670void lcdc_disp_on (void)
671{
672 gpio_set(SPI_CS, 0); /* low */
673 gpio_set(SPI_SCLK, 1); /* high */
674 gpio_set(SPI_MOSI, 0);
675 gpio_set(SPI_MISO, 0);
676
677 if (1) {
678 toshiba_spi_write(0, 0, 0);
679 mdelay(7);
680 toshiba_spi_write(0, 0, 0);
681 mdelay(7);
682 toshiba_spi_write(0, 0, 0);
683 mdelay(7);
684 toshiba_spi_write(0xba, 0x11, 1);
685 toshiba_spi_write(0x36, 0x00, 1);
686 mdelay(1);
687 toshiba_spi_write(0x3a, 0x60, 1);
688 toshiba_spi_write(0xb1, 0x5d, 1);
689 mdelay(1);
690 toshiba_spi_write(0xb2, 0x33, 1);
691 toshiba_spi_write(0xb3, 0x22, 1);
692 mdelay(1);
693 toshiba_spi_write(0xb4, 0x02, 1);
694 toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
695 mdelay(1);
696 toshiba_spi_write(0xb6, 0x27, 1);
697 toshiba_spi_write(0xb7, 0x03, 1);
698 mdelay(1);
699 toshiba_spi_write(0xb9, 0x24, 1);
700 toshiba_spi_write(0xbd, 0xa1, 1);
701 mdelay(1);
702 toshiba_spi_write(0xbb, 0x00, 1);
703 toshiba_spi_write(0xbf, 0x01, 1);
704 mdelay(1);
705 toshiba_spi_write(0xbe, 0x00, 1);
706 toshiba_spi_write(0xc0, 0x11, 1);
707 mdelay(1);
708 toshiba_spi_write(0xc1, 0x11, 1);
709 toshiba_spi_write(0xc2, 0x11, 1);
710 mdelay(1);
711 toshiba_spi_write(0xc3, 0x3232, 2);
712 mdelay(1);
713 toshiba_spi_write(0xc4, 0x3232, 2);
714 mdelay(1);
715 toshiba_spi_write(0xc5, 0x3232, 2);
716 mdelay(1);
717 toshiba_spi_write(0xc6, 0x3232, 2);
718 mdelay(1);
719 toshiba_spi_write(0xc7, 0x6445, 2);
720 mdelay(1);
721 toshiba_spi_write(0xc8, 0x44, 1);
722 toshiba_spi_write(0xc9, 0x52, 1);
723 mdelay(1);
724 toshiba_spi_write(0xca, 0x00, 1);
725 mdelay(1);
726 toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */
727 mdelay(1);
728 toshiba_spi_write(0xcf, 0x01, 1);
729 mdelay(1);
730 toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */
731 mdelay(1);
732 toshiba_spi_write(0xd1, 0x01, 1);
733 mdelay(1);
734 toshiba_spi_write(0xd2, 0x0028, 2);
735 mdelay(1);
736 toshiba_spi_write(0xd3, 0x0028, 2);
737 mdelay(1);
738 toshiba_spi_write(0xd4, 0x26a4, 2);
739 mdelay(1);
740 toshiba_spi_write(0xd5, 0x20, 1);
741 mdelay(1);
742 toshiba_spi_write(0xef, 0x3200, 2);
743 mdelay(32);
744 toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */
745 toshiba_spi_write(0x3b, 0x00, 1);
746 mdelay(1);
747 toshiba_spi_write(0xb0, 0x16, 1);
748 mdelay(1);
749 toshiba_spi_write(0xb8, 0xfff5, 2);
750 mdelay(1);
751 toshiba_spi_write(0x11, 0, 0);
752 mdelay(5);
753 toshiba_spi_write(0x29, 0, 0);
754 mdelay(5);
755 }
756}
757
758void lcdc_on(void)
759{
760 lcdc_clock_init(27648000);
761 lcdc_toshiba_panel_power(1);
762 lcdc_disp_on();
763}
764
765#endif