vijay kumar | ca1672a | 2015-04-09 16:45:40 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | #include <err.h> |
| 29 | #include <assert.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <clock.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform.h> |
| 37 | |
| 38 | void hsusb_clock_init(void) |
| 39 | { |
vijay kumar | 20627da | 2015-10-01 13:28:58 +0530 | [diff] [blame] | 40 | int ret; |
| 41 | struct clk *iclk, *cclk; |
vijay kumar | ca1672a | 2015-04-09 16:45:40 +0530 | [diff] [blame] | 42 | |
vijay kumar | 20627da | 2015-10-01 13:28:58 +0530 | [diff] [blame] | 43 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 44 | if(ret) |
| 45 | { |
| 46 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 47 | ASSERT(0); |
| 48 | } |
| 49 | |
| 50 | ret = clk_get_set_enable("usb_core_clk", 133330000, 1); |
| 51 | if(ret) |
| 52 | { |
| 53 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 54 | ASSERT(0); |
| 55 | } |
| 56 | |
| 57 | mdelay(20); |
| 58 | |
| 59 | iclk = clk_get("usb_iface_clk"); |
| 60 | cclk = clk_get("usb_core_clk"); |
| 61 | |
| 62 | clk_disable(iclk); |
| 63 | clk_disable(cclk); |
| 64 | |
| 65 | mdelay(20); |
| 66 | |
| 67 | /* Start the block reset for usb */ |
| 68 | writel(1, USB_HS_BCR); |
| 69 | |
| 70 | mdelay(20); |
| 71 | |
| 72 | /* Take usb block out of reset */ |
| 73 | writel(0, USB_HS_BCR); |
| 74 | |
| 75 | mdelay(20); |
| 76 | |
| 77 | ret = clk_enable(iclk); |
| 78 | |
| 79 | if(ret) |
| 80 | { |
| 81 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 82 | ASSERT(0); |
| 83 | } |
| 84 | |
| 85 | ret = clk_enable(cclk); |
| 86 | |
| 87 | if(ret) |
| 88 | { |
| 89 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 90 | ASSERT(0); |
| 91 | } |
vijay kumar | ca1672a | 2015-04-09 16:45:40 +0530 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /* Configure UART clock based on the UART block id*/ |
| 95 | void clock_config_uart_dm(uint8_t id) |
| 96 | { |
vijay kumar | 20627da | 2015-10-01 13:28:58 +0530 | [diff] [blame] | 97 | int ret; |
| 98 | char iclk[64]; |
| 99 | char cclk[64]; |
vijay kumar | ca1672a | 2015-04-09 16:45:40 +0530 | [diff] [blame] | 100 | |
vijay kumar | 20627da | 2015-10-01 13:28:58 +0530 | [diff] [blame] | 101 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 102 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
| 103 | |
| 104 | ret = clk_get_set_enable(iclk, 0, 1); |
| 105 | if(ret) |
| 106 | { |
| 107 | dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret); |
| 108 | ASSERT(0); |
| 109 | } |
| 110 | |
| 111 | ret = clk_get_set_enable(cclk, 7372800, 1); |
| 112 | if(ret) |
| 113 | { |
| 114 | dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret); |
| 115 | ASSERT(0); |
| 116 | } |
vijay kumar | ca1672a | 2015-04-09 16:45:40 +0530 | [diff] [blame] | 117 | } |
vijay kumar | 70dbe3e | 2015-11-20 13:07:30 +0530 | [diff] [blame] | 118 | |
| 119 | void clock_ce_enable(uint8_t instance) |
| 120 | { |
| 121 | int ret; |
| 122 | char clk_name[64]; |
| 123 | |
| 124 | snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance); |
| 125 | ret = clk_get_set_enable(clk_name, 160000000, 1); |
| 126 | if(ret) |
| 127 | { |
| 128 | dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret); |
| 129 | ASSERT(0); |
| 130 | } |
| 131 | |
| 132 | snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance); |
| 133 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 134 | if(ret) |
| 135 | { |
| 136 | dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret); |
| 137 | ASSERT(0); |
| 138 | } |
| 139 | |
| 140 | snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance); |
| 141 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 142 | if(ret) |
| 143 | { |
| 144 | dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret); |
| 145 | ASSERT(0); |
| 146 | } |
| 147 | |
| 148 | snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance); |
| 149 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 150 | if(ret) |
| 151 | { |
| 152 | dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret); |
| 153 | ASSERT(0); |
| 154 | } |
| 155 | |
| 156 | /* Wait for 48 * #pipes cycles. |
| 157 | * This is necessary as immediately after an access control reset (boot up) |
| 158 | * or a debug re-enable, the Crypto core sequentially clears its internal |
| 159 | * pipe key storage memory. If pipe key initialization writes are attempted |
| 160 | * during this time, they may be overwritten by the internal clearing logic. |
| 161 | */ |
| 162 | udelay(1); |
| 163 | } |
| 164 | void clock_ce_disable(uint8_t instance) |
| 165 | { |
| 166 | struct clk *ahb_clk; |
| 167 | struct clk *cclk; |
| 168 | struct clk *axi_clk; |
| 169 | struct clk *src_clk; |
| 170 | char clk_name[64]; |
| 171 | |
| 172 | snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance); |
| 173 | src_clk = clk_get(clk_name); |
| 174 | |
| 175 | snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance); |
| 176 | ahb_clk = clk_get(clk_name); |
| 177 | |
| 178 | snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance); |
| 179 | axi_clk = clk_get(clk_name); |
| 180 | |
| 181 | snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance); |
| 182 | cclk = clk_get(clk_name); |
| 183 | |
| 184 | clk_disable(ahb_clk); |
| 185 | clk_disable(axi_clk); |
| 186 | clk_disable(cclk); |
| 187 | clk_disable(src_clk); |
| 188 | |
| 189 | /* Some delay for the clocks to stabalize. */ |
| 190 | udelay(1); |
| 191 | } |
| 192 | /* Function to asynchronously reset CE. |
| 193 | * Function assumes that all the CE clocks are off. |
| 194 | */ |
| 195 | static void ce_async_reset(uint8_t instance) |
| 196 | { |
| 197 | /* Start the block reset for CE */ |
| 198 | writel(1, GCC_CRYPTO_BCR); |
| 199 | |
| 200 | udelay(2); |
| 201 | |
| 202 | /* Take CE block out of reset */ |
| 203 | writel(0, GCC_CRYPTO_BCR); |
| 204 | |
| 205 | udelay(2); |
| 206 | } |
| 207 | |
| 208 | void clock_config_ce(uint8_t instance) |
| 209 | { |
| 210 | /* Need to enable the clock before disabling since the clk_disable() |
| 211 | * has a check to default to nop when the clk_enable() is not called |
| 212 | * on that particular clock. |
| 213 | */ |
| 214 | clock_ce_enable(instance); |
| 215 | |
| 216 | clock_ce_disable(instance); |
| 217 | |
| 218 | ce_async_reset(instance); |
| 219 | |
| 220 | clock_ce_enable(instance); |
| 221 | } |