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Channagoud Kadabif8ad8e72015-01-06 15:10:13 -08001/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <platform/irqs.h>
32#include <platform/gpio.h>
33#include <reg.h>
34#include <target.h>
35#include <platform.h>
36#include <dload_util.h>
37#include <uart_dm.h>
38#include <mmc.h>
39#include <spmi.h>
40#include <board.h>
41#include <smem.h>
42#include <baseband.h>
43#include <dev/keys.h>
44#include <pm8x41.h>
45#include <crypto5_wrapper.h>
46#include <clock.h>
47#include <partition_parser.h>
48#include <scm.h>
49#include <platform/clock.h>
50#include <platform/gpio.h>
51#include <platform/timer.h>
52#include <stdlib.h>
53#include <ufs.h>
54#include <boot_device.h>
55#include <qmp_phy.h>
Channagoud Kadabi7d308202014-12-22 12:07:04 -080056#include <sdhci_msm.h>
57#include <qusb2_phy.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070058
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -080059#define CE_INSTANCE 1
60#define CE_EE 1
61#define CE_FIFO_SIZE 64
62#define CE_READ_PIPE 3
63#define CE_WRITE_PIPE 2
64#define CE_READ_PIPE_LOCK_GRP 0
65#define CE_WRITE_PIPE_LOCK_GRP 0
66#define CE_ARRAY_SIZE 20
67
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070068#define PMIC_ARB_CHANNEL_NUM 0
69#define PMIC_ARB_OWNER_ID 0
70
71static void set_sdc_power_ctrl(void);
72static uint32_t mmc_pwrctl_base[] =
73 { MSM_SDC1_BASE, MSM_SDC2_BASE };
74
75static uint32_t mmc_sdhci_base[] =
76 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
77
78static uint32_t mmc_sdc_pwrctl_irq[] =
79 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
80
81struct mmc_device *dev;
82struct ufs_dev ufs_device;
83
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070084void target_early_init(void)
85{
86#if WITH_DEBUG_UART
Channagoud Kadabi35503c42014-11-14 16:22:43 -080087 uart_dm_init(8, 0, BLSP2_UART1_BASE);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070088#endif
89}
90
91/* Return 1 if vol_up pressed */
92static int target_volume_up()
93{
94 uint8_t status = 0;
95 struct pm8x41_gpio gpio;
96
97 /* Configure the GPIO */
98 gpio.direction = PM_GPIO_DIR_IN;
99 gpio.function = 0;
100 gpio.pull = PM_GPIO_PULL_UP_30;
101 gpio.vin_sel = 2;
102
103 pm8x41_gpio_config(2, &gpio);
104
105 /* Wait for the pmic gpio config to take effect */
106 thread_sleep(1);
107
108 /* Get status of P_GPIO_5 */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800109 pm8x41_gpio_get(2, &status);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700110
111 return !status; /* active low */
112}
113
114/* Return 1 if vol_down pressed */
115uint32_t target_volume_down()
116{
117 return pm8x41_resin_status();
118}
119
120static void target_keystatus()
121{
122 keys_init();
123
124 if(target_volume_down())
125 keys_post_event(KEY_VOLUMEDOWN, 1);
126
127 if(target_volume_up())
128 keys_post_event(KEY_VOLUMEUP, 1);
129}
130
131void target_uninit(void)
132{
133 if (platform_boot_dev_isemmc())
134 {
135 mmc_put_card_to_sleep(dev);
136 /* Disable HC mode before jumping to kernel */
137 sdhci_mode_disable(&dev->host);
138 }
139}
140
141static void set_sdc_power_ctrl()
142{
143 /* Drive strength configs for sdc pins */
144 struct tlmm_cfgs sdc1_hdrv_cfg[] =
145 {
146 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
147 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
148 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
149 };
150
151 /* Pull configs for sdc pins */
152 struct tlmm_cfgs sdc1_pull_cfg[] =
153 {
154 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
155 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
156 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
157 };
158
159 struct tlmm_cfgs sdc1_rclk_cfg[] =
160 {
161 { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
162 };
163
164 /* Set the drive strength & pull control values */
165 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
166 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
167 tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
168}
169
170void target_sdc_init()
171{
172 struct mmc_config_data config = {0};
173
174 /* Set drive strength & pull ctrl values */
175 set_sdc_power_ctrl();
176
177 config.bus_width = DATA_BUS_WIDTH_8BIT;
178 config.max_clk_rate = MMC_CLK_192MHZ;
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800179 config.hs400_support = 1;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700180
181 /* Try slot 1*/
182 config.slot = 1;
183 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
184 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
185 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
186
187 if (!(dev = mmc_init(&config)))
188 {
189 /* Try slot 2 */
190 config.slot = 2;
191 config.max_clk_rate = MMC_CLK_200MHZ;
192 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
193 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
194 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
195
196 if (!(dev = mmc_init(&config)))
197 {
198 dprintf(CRITICAL, "mmc init failed!");
199 ASSERT(0);
200 }
201 }
202}
203
204void *target_mmc_device()
205{
206 if (platform_boot_dev_isemmc())
207 return (void *) dev;
208 else
209 return (void *) &ufs_device;
210}
211
212void target_init(void)
213{
214 dprintf(INFO, "target_init()\n");
215
216 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
217
218 target_keystatus();
219
220 if (target_use_signed_kernel())
221 target_crypto_init_params();
222
223 platform_read_boot_config();
224
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800225#ifdef MMC_SDHCI_SUPPORT
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700226 if (platform_boot_dev_isemmc())
227 {
228 target_sdc_init();
229 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800230#endif
231#ifdef UFS_SUPPORT
232 if (!platform_boot_dev_isemmc())
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700233 {
234 ufs_device.base = UFS_BASE;
235 ufs_init(&ufs_device);
236 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800237#endif
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700238
239 /* Storage initialization is complete, read the partition table info */
Channagoud Kadabi58a273b2015-02-10 12:56:22 -0800240 mmc_read_partition_table(0);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700241}
242
243unsigned board_machtype(void)
244{
245 return LINUX_MACHTYPE_UNKNOWN;
246}
247
248/* Detect the target type */
249void target_detect(struct board_data *board)
250{
251 /* This is filled from board.c */
252}
253
254/* Detect the modem type */
255void target_baseband_detect(struct board_data *board)
256{
257 uint32_t platform;
258
259 platform = board->platform;
260
261 switch(platform) {
262 case MSMTHULIUM:
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800263 if (board->platform_version == 0x10000)
264 board->baseband = BASEBAND_APQ;
265 else
266 board->baseband = BASEBAND_MSM;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700267 break;
268 default:
269 dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
270 ASSERT(0);
271 };
272}
273unsigned target_baseband()
274{
275 return board_baseband();
276}
277
278void target_serialno(unsigned char *buf)
279{
280 unsigned int serialno;
281 if (target_is_emmc_boot()) {
282 serialno = mmc_get_psn();
283 snprintf((char *)buf, 13, "%x", serialno);
284 }
285}
286
287unsigned check_reboot_mode(void)
288{
289 uint32_t restart_reason = 0;
290 uint32_t restart_reason_addr;
291
292 restart_reason_addr = RESTART_REASON_ADDR;
293
294 /* Read reboot reason and scrub it */
295 restart_reason = readl(restart_reason_addr);
296 writel(0x00, restart_reason_addr);
297
298 return restart_reason;
299}
300
301void reboot_device(unsigned reboot_reason)
302{
303 uint8_t reset_type = 0;
304
305 /* Write the reboot reason */
306 writel(reboot_reason, RESTART_REASON_ADDR);
307
308 if(reboot_reason)
309 reset_type = PON_PSHOLD_WARM_RESET;
310 else
311 reset_type = PON_PSHOLD_HARD_RESET;
312
313 pm8x41_reset_configure(reset_type);
314
315 /* Drop PS_HOLD for MSM */
316 writel(0x00, MPM2_MPM_PS_HOLD);
317
318 mdelay(5000);
319
320 dprintf(CRITICAL, "Rebooting failed\n");
321}
322
323int emmc_recovery_init(void)
324{
325 return _emmc_recovery_init();
326}
327
328void target_usb_phy_reset()
329{
Channagoud Kadabif8ad8e72015-01-06 15:10:13 -0800330#ifndef USE_HSONLY_MODE
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700331 usb30_qmp_phy_reset();
Channagoud Kadabif8ad8e72015-01-06 15:10:13 -0800332#endif
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700333 qusb2_phy_reset();
334}
335
336target_usb_iface_t* target_usb30_init()
337{
338 target_usb_iface_t *t_usb_iface;
339
340 t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
341 ASSERT(t_usb_iface);
342
Channagoud Kadabif8ad8e72015-01-06 15:10:13 -0800343#ifndef USE_HSONLY_MODE
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700344 t_usb_iface->phy_init = usb30_qmp_phy_init;
Channagoud Kadabif8ad8e72015-01-06 15:10:13 -0800345#endif
346
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700347 t_usb_iface->phy_reset = target_usb_phy_reset;
348 t_usb_iface->clock_init = clock_usb30_init;
349 t_usb_iface->vbus_override = 1;
350
351 return t_usb_iface;
352}
353
354/* identify the usb controller to be used for the target */
355const char * target_usb_controller()
356{
357 return "dwc";
358}
359
360uint32_t target_override_pll()
361{
362 return 1;
363}
364
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -0800365crypto_engine_type board_ce_type(void)
366{
367 return CRYPTO_ENGINE_TYPE_SW;
368}
369
370/* Set up params for h/w CE. */
371void target_crypto_init_params()
372{
373 struct crypto_init_params ce_params;
374
375 /* Set up base addresses and instance. */
376 ce_params.crypto_instance = CE_INSTANCE;
377 ce_params.crypto_base = MSM_CE_BASE;
378 ce_params.bam_base = MSM_CE_BAM_BASE;
379
380 /* Set up BAM config. */
381 ce_params.bam_ee = CE_EE;
382 ce_params.pipes.read_pipe = CE_READ_PIPE;
383 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
384 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
385 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
386
387 /* Assign buffer sizes. */
388 ce_params.num_ce = CE_ARRAY_SIZE;
389 ce_params.read_fifo_size = CE_FIFO_SIZE;
390 ce_params.write_fifo_size = CE_FIFO_SIZE;
391
392 /* BAM is initialized by TZ for this platform.
393 * Do not do it again as the initialization address space
394 * is locked.
395 */
396 ce_params.do_bam_init = 0;
397
398 crypto_init_params(&ce_params);
399}