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Deepa Dinamani554b0622013-05-16 15:00:30 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_APQ8084_IOMAP_H_
30#define _PLATFORM_APQ8084_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x0FA00000
33
Sundarajan Srinivasan0f21b772013-08-29 13:19:15 -070034#define SYSTEM_IMEM_BASE 0xFE800000
35
36#define MSM_IOMAP_BASE 0xF9000000
37#define MSM_IOMAP_END 0xFEFFFFFF
38
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -070039#define MSM_SHARED_IMEM_BASE 0xFE805000
40
41#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
42
Deepa Dinamani554b0622013-05-16 15:00:30 -070043#define KPSS_BASE 0xF9000000
44
45#define MSM_GIC_DIST_BASE KPSS_BASE
46#define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000)
47#define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000)
48#define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000)
49#define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000)
50#define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000)
51#define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000)
52#define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000)
53#define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE
54
55#define PERIPH_SS_BASE 0xF9800000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
59#define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000)
60#define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
61#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
62#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
63#define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000)
64#define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900)
65
66#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
67#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
68#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
69#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
70#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
71#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
72
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -070073#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
74
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -070075#define CLK_CTL_BASE 0xFC400000
76
77/* GPLL */
78#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
79#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
80#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
81
82/* UART */
83#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
84#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -070085#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
86#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
87#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
88#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
89#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
90#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
Sundarajan Srinivasan09374ed2013-06-18 13:29:32 -070091
92/* USB */
93#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
94
95#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
96#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
97#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
98#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
99
100/* SDCC */
101#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
102#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
103#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
104#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
105#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
106#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
107#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
108#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
109#define SDCC1_CDCCAL_SLEEP_CBCR (CLK_CTL_BASE + 0x4E4)
110
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700111/* USB 3.0 clocks */
112#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x0108)
113
114#define GCC_USB_30_BCR (CLK_CTL_BASE + 0x03C0)
115#define GCC_USB_30_MISC (CLK_CTL_BASE + 0x03C4)
116
117#define GCC_USB30_MASTER_CBCR (CLK_CTL_BASE + 0x03C8)
118#define GCC_USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x03CC)
119#define GCC_USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x03D0)
120
121#define GCC_USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x03D4)
122#define GCC_USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x03D8)
123#define GCC_USB30_MASTER_M (CLK_CTL_BASE + 0x03DC)
124#define GCC_USB30_MASTER_N (CLK_CTL_BASE + 0x03E0)
125#define GCC_USB30_MASTER_D (CLK_CTL_BASE + 0x03E4)
126
127#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
128#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x1E84)
Channagoud Kadabi70500ea2013-10-29 17:33:44 -0700129#define GCC_USB30_PHY_COM_BCR (CLK_CTL_BASE + 0x1E80)
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700130
131/* USB30 base */
132#define MSM_USB30_BASE 0xF9200000
133#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
134
135
Deepa Dinamani554b0622013-05-16 15:00:30 -0700136/* Addresses below this point needs to be verified.
137 * Included only for compilation purposes.
138 */
139#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
140
141#define CLK_CTL_BASE 0xFC400000
Deepa Dinamani554b0622013-05-16 15:00:30 -0700142#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
143
144#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
145
Deepa Dinamanieafb5ee2013-09-16 13:47:30 -0700146#define UFS_BASE (0xFC590000 + 0x00004000)
147
Deepa Dinamani554b0622013-05-16 15:00:30 -0700148#define SPMI_BASE 0xFC4C0000
149#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
150#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
151
152#define MSM_CE2_BAM_BASE 0xFD444000
153#define MSM_CE2_BASE 0xFD45A000
154#define USB2_PHY_SEL 0xFD4AB000
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700155#define COPSS_USB_CONTROL_WITH_JDR 0xFD4AB204
Deepa Dinamani554b0622013-05-16 15:00:30 -0700156
157#define TLMM_BASE_ADDR 0xFD510000
158#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
159#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
160
161#define MPM2_MPM_CTRL_BASE 0xFC4A1000
162#define MPM2_MPM_PS_HOLD 0xFC4AB000
163#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
164
165/* DRV strength for sdcc */
166#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
167
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700168/* SDHCI */
169#define SDCC_MCI_HC_MODE (0x00000078)
170#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
171#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
172#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
173#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
174
Sundarajan Srinivasan0f110732013-09-10 13:52:59 -0700175/* Boot config */
176#define SEC_CTRL_CORE_BASE 0xFC4B8000
177#define BOOT_CONFIG_OFFSET 0x00006034
178#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
179
Dhaval Patel4a87d522013-10-18 19:02:37 -0700180/* mdss */
181#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
182
183#define MIPI_DSI_BASE (0xFD922800)
184#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
185#define MIPI_DSI1_BASE (0xFD922E00)
186#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
187
188#define MDP_BASE (0xfd900000)
189#define REG_MDP(off) (MDP_BASE + (off))
190
191#define SOFT_RESET 0x118
192#define CLK_CTRL 0x11C
193#define TRIG_CTRL 0x084
194#define CTRL 0x004
195#define COMMAND_MODE_DMA_CTRL 0x03C
196#define ERR_INT_MASK0 0x10C
197
198#define LANE_SWAP_CTL 0x0B0
199#define TIMING_CTL 0x0C4
200
201#define VIDEO_MODE_ACTIVE_H 0x024
202#define VIDEO_MODE_ACTIVE_V 0x028
203#define VIDEO_MODE_TOTAL 0x02C
204#define VIDEO_MODE_HSYNC 0x030
205#define VIDEO_MODE_VSYNC 0x034
206#define VIDEO_MODE_VSYNC_VPOS 0x038
207
Dhaval Patel55ac0c52013-10-25 10:46:43 -0700208#define MDP_VP_0_RGB_0_BASE REG_MDP(0x2200)
209#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2600)
210#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
211#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
212
Dhaval Patel4a87d522013-10-18 19:02:37 -0700213#define DMA_CMD_OFFSET 0x048
214#define DMA_CMD_LENGTH 0x04C
215
216#define INT_CTRL 0x110
217#define CMD_MODE_DMA_SW_TRIGGER 0x090
218
219#define EOT_PACKET_CTRL 0x0C8
220#define MISR_VIDEO_CTRL 0x0A4
221#define VIDEO_MODE_CTRL 0x010
222#define HS_TIMER_CTRL 0x0BC
223
Deepa Dinamani554b0622013-05-16 15:00:30 -0700224#endif