Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #include <err.h> |
| 24 | #include <sys/types.h> |
| 25 | #include <debug.h> |
| 26 | #include <reg.h> |
| 27 | #include <kernel/thread.h> |
| 28 | #include <platform/interrupts.h> |
| 29 | #include <arch/ops.h> |
| 30 | #include <arch/arm.h> |
| 31 | #include "platform_p.h" |
| 32 | #include <platform/omap5912.h> |
| 33 | |
| 34 | struct int_handler_struct { |
| 35 | int_handler handler; |
| 36 | void *arg; |
| 37 | }; |
| 38 | |
| 39 | static struct int_handler_struct int_handler_table[INT_VECTORS]; |
| 40 | |
| 41 | static const uint32_t icBase[5] = { |
| 42 | INTCON0_BASE, INTCON1_BASE, INTCON2_BASE, INTCON3_BASE, INTCON4_BASE }; |
| 43 | |
| 44 | /* a bitmap of the level triggered interrupt vectors */ |
| 45 | static uint32_t level_trigger[5] = { |
| 46 | 0xb3fefe8f, // level 1 0-31 |
| 47 | 0xfdb3c1fd, // level 2 0-31 |
| 48 | 0xfffff7ff, // level 2 32-63 |
| 49 | 0xbfffffff, // level 2 64-95 |
| 50 | 0xffffffff // level 2 96-128 |
| 51 | }; |
| 52 | |
| 53 | static inline volatile uint32_t *ICReg(uint controller, uint reg) |
| 54 | { |
| 55 | return (volatile uint32_t *)(icBase[controller] + reg); |
| 56 | } |
| 57 | |
| 58 | static inline uint32_t readICReg(uint controller, uint reg) |
| 59 | { |
| 60 | return *ICReg(controller, reg); |
| 61 | } |
| 62 | static inline void writeICReg(uint controller, uint reg, uint val) |
| 63 | { |
| 64 | *ICReg(controller, reg) = val; |
| 65 | } |
| 66 | |
| 67 | static inline uint vectorToController(uint vector) |
| 68 | { |
| 69 | return vector / 32; |
| 70 | } |
| 71 | |
| 72 | void platform_init_interrupts(void) |
| 73 | { |
| 74 | unsigned int i; |
| 75 | |
| 76 | // mask all interrupts |
| 77 | *ICReg(0, INTCON_MIR) = 0xfffffffa; |
| 78 | *ICReg(1, INTCON_MIR) = 0xffffffff; |
| 79 | *ICReg(2, INTCON_MIR) = 0xffffffff; |
| 80 | *ICReg(3, INTCON_MIR) = 0xffffffff; |
| 81 | *ICReg(4, INTCON_MIR) = 0xffffffff; |
| 82 | |
| 83 | // set up each of the interrupts |
| 84 | for (i = 0; i < INT_VECTORS; i++) { |
| 85 | // set each vector up as high priority, IRQ, and default edge/level sensitivity |
| 86 | *ICReg(i / 32, INTCON_ILR_BASE + 4*(i%32)) = ((level_trigger[i/32] & (1<<(i%32))) ? (1<<1) : (0<<1)) | 0; |
| 87 | } |
| 88 | |
| 89 | // clear any pending interrupts |
| 90 | *ICReg(0, INTCON_ITR) = 0; |
| 91 | *ICReg(1, INTCON_ITR) = 0; |
| 92 | *ICReg(2, INTCON_ITR) = 0; |
| 93 | *ICReg(3, INTCON_ITR) = 0; |
| 94 | *ICReg(4, INTCON_ITR) = 0; |
| 95 | |
| 96 | // globally unmask interrupts |
| 97 | *ICReg(1, INTCON_CONTROL) = 3; |
| 98 | *ICReg(0, INTCON_CONTROL) = 3; |
| 99 | *ICReg(0, INTCON_GMR) = 0; |
| 100 | } |
| 101 | |
| 102 | status_t mask_interrupt(unsigned int vector, bool *oldstate) |
| 103 | { |
| 104 | if (vector >= INT_VECTORS) |
| 105 | return ERR_INVALID_ARGS; |
| 106 | |
| 107 | // dprintf("%s: vector %d\n", __PRETTY_FUNCTION__, vector); |
| 108 | |
| 109 | enter_critical_section(); |
| 110 | |
| 111 | if (oldstate) |
| 112 | *oldstate = false; |
| 113 | |
| 114 | volatile uint32_t *mir = ICReg(vectorToController(vector), INTCON_MIR); |
| 115 | *mir = *mir | (1<<(vector % 32)); |
| 116 | |
| 117 | exit_critical_section(); |
| 118 | |
| 119 | return NO_ERROR; |
| 120 | } |
| 121 | |
| 122 | status_t unmask_interrupt(unsigned int vector, bool *oldstate) |
| 123 | { |
| 124 | if (vector >= INT_VECTORS) |
| 125 | return ERR_INVALID_ARGS; |
| 126 | |
| 127 | // dprintf("%s: vector %d\n", __PRETTY_FUNCTION__, vector); |
| 128 | |
| 129 | enter_critical_section(); |
| 130 | |
| 131 | if (oldstate) |
| 132 | *oldstate = false; |
| 133 | |
| 134 | volatile uint32_t *mir = ICReg(vectorToController(vector), INTCON_MIR); |
| 135 | *mir = *mir & ~(1<<(vector % 32)); |
| 136 | |
| 137 | exit_critical_section(); |
| 138 | |
| 139 | return NO_ERROR; |
| 140 | } |
| 141 | |
| 142 | enum handler_return platform_irq(struct arm_iframe *frame) |
| 143 | { |
| 144 | // get the current vector |
| 145 | unsigned int vector; |
| 146 | |
| 147 | #if THREAD_STATS |
| 148 | thread_stats.interrupts++; |
| 149 | #endif |
| 150 | |
| 151 | // read from the first level int handler |
| 152 | vector = *ICReg(0, INTCON_SIR_IRQ); |
| 153 | |
| 154 | // see if it's coming from the second level handler |
| 155 | if (vector == 0) { |
| 156 | vector = *ICReg(1, INTCON_SIR_IRQ) + 32; |
| 157 | } |
| 158 | |
| 159 | // dprintf("platform_irq: spsr 0x%x, pc 0x%x, currthread %p, vector %d\n", frame->spsr, frame->pc, current_thread, vector); |
| 160 | |
| 161 | // deliver the interrupt |
| 162 | enum handler_return ret; |
| 163 | |
| 164 | ret = INT_NO_RESCHEDULE; |
| 165 | if (int_handler_table[vector].handler) |
| 166 | ret = int_handler_table[vector].handler(int_handler_table[vector].arg); |
| 167 | |
| 168 | // ack the interrupt |
| 169 | if (vector >= 32) { |
| 170 | // interrupt is chained, so ack the second level first, and then the first |
| 171 | *ICReg(vector / 32, INTCON_ITR) = ~(1 << (vector % 32)); |
| 172 | *ICReg(1, INTCON_CONTROL) |= 1; |
| 173 | vector = 0; // force the following code to ack the chained first level vector |
| 174 | } |
| 175 | |
| 176 | *ICReg(0, INTCON_ITR) = ~(1 << vector); |
| 177 | *ICReg(0, INTCON_CONTROL) = 1; |
| 178 | |
| 179 | return ret; |
| 180 | } |
| 181 | |
| 182 | void platform_fiq(struct arm_iframe *frame) |
| 183 | { |
| 184 | PANIC_UNIMPLEMENTED; |
| 185 | } |
| 186 | |
| 187 | void register_int_handler(unsigned int vector, int_handler handler, void *arg) |
| 188 | { |
| 189 | if (vector >= INT_VECTORS) |
| 190 | panic("register_int_handler: vector out of range %d\n", vector); |
| 191 | |
| 192 | enter_critical_section(); |
| 193 | |
| 194 | int_handler_table[vector].handler = handler; |
| 195 | int_handler_table[vector].arg = arg; |
| 196 | |
| 197 | exit_critical_section(); |
| 198 | } |
| 199 | |