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gerrit-public.fairphone.software / kernel / lk / 5fb979fe462366ffa0e509c547ed8dd776a37dbe / . / platform / msm_shared / include / mipi_dsi_autopll_thulium.h
blob: bac47765c330ea7c6b32a2219b77e4c6a8db0197 [file] [log] [blame]
Chandan Uddaraju5fb979f2016-01-29 10:02:20 -0800[diff] [blame^]1/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
Dhaval Patelffb7b592015-03-23 23:34:07 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef __MIPI_DSI_AUTOPLL_THULIUM_H
31#define __MIPI_DSI_AUTOPLL_THULIUM_H
32
33#define DSIPHY_CMN_CLK_CFG0 0x0010
34#define DSIPHY_CMN_CLK_CFG1 0x0014
35#define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018
36
37#define DSIPHY_CMN_PLL_CNTRL 0x0048
38#define DSIPHY_CMN_CTRL_0 0x001c
39#define DSIPHY_CMN_CTRL_1 0x0020
40
41#define DSIPHY_CMN_LDO_CNTRL 0x004c
42
43#define DSIPHY_PLL_IE_TRIM 0x0400
44#define DSIPHY_PLL_IP_TRIM 0x0404
45#define DSIPHY_CMN_PLL_PLL_CTRL 0x0408
46
47#define DSIPHY_PLL_IPTAT_TRIM 0x0410
48
49#define DSIPHY_PLL_CLKBUFLR_EN 0x041c
50
51#define DSIPHY_PLL_SYSCLK_EN_RESET 0x0428
52#define DSIPHY_PLL_RESETSM_CNTRL 0x042c
53#define DSIPHY_PLL_RESETSM_CNTRL2 0x0430
54#define DSIPHY_PLL_RESETSM_CNTRL3 0x0434
55#define DSIPHY_PLL_RESETSM_CNTRL4 0x0438
56#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c
57#define DSIPHY_PLL_KVCO_DIV_REF1 0x0440
58#define DSIPHY_PLL_KVCO_DIV_REF2 0x0444
59
60#define DSIPHY_PLL_KVCO_COUNT1 0x0448
61#define DSIPHY_PLL_KVCO_COUNT2 0x044c
62
63#define DSIPHY_PLL_VCO_DIV_REF1 0x046c
64#define DSIPHY_PLL_VCO_DIV_REF2 0x0470
65#define DSIPHY_PLL_VCO_COUNT1 0x0474
66#define DSIPHY_PLL_VCO_COUNT2 0x0478
67#define DSIPHY_PLL_PLLLOCK_CMP1 0x047c
68#define DSIPHY_PLL_PLLLOCK_CMP2 0x0480
69#define DSIPHY_PLL_PLLLOCK_CMP3 0x0484
70#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488
71
72#define DSIPHY_PLL_DEC_START 0x0490
73#define DSIPHY_PLL_DIV_FRAC_START1 0x04b4
74#define DSIPHY_PLL_DIV_FRAC_START2 0x04b8
75#define DSIPHY_PLL_DIV_FRAC_START3 0x04bc
76#define DSIPHY_PLL_TXCLK_EN 0x04c0
77#define DSIPHY_PLL_PLL_CRCTRL 0x04c4
78
79#define DSIPHY_PLL_RESET_SM_READY_STATUS 0x04cc
80
81#define DSIPHY_PLL_PLL_MISC1 0x04e8
82
83#define DSIPHY_PLL_CP_SET_CUR 0x04f0
84#define DSIPHY_PLL_PLL_ICPMSET 0x04f4
85#define DSIPHY_PLL_PLL_ICPCSET 0x04f8
86#define DSIPHY_PLL_PLL_ICP_SET 0x04fc
87#define DSIPHY_PLL_PLL_LPF1 0x0500
88#define DSIPHY_PLL_PLL_LPF2_POSTDIV 0x0504
89#define DSIPHY_PLL_PLL_BANDGAP 0x0508
90
91struct dsi_pll_input {
92 uint32_t fref; /* 19.2 Mhz, reference clk */
93 uint32_t fdata; /* bit clock rate */
94 uint32_t dsiclk_sel; /* 1, reg: 0x0014 */
95 uint32_t n2div; /* 1, reg: 0x0010, bit 4-7 */
96 uint32_t ssc_en; /* 1, reg: 0x0494, bit 0 */
97 uint32_t ldo_en; /* 0, reg: 0x004c, bit 0 */
98
99 /* fixed */
100 uint32_t refclk_dbler_en; /* 0, reg: 0x04c0, bit 1 */
101 uint32_t vco_measure_time; /* 5, unknown */
102 uint32_t kvco_measure_time; /* 5, unknown */
103 uint32_t bandgap_timer; /* 4, reg: 0x0430, bit 3 - 5 */
104 uint32_t pll_wakeup_timer; /* 5, reg: 0x043c, bit 0 - 2 */
105 uint32_t plllock_cnt; /* 1, reg: 0x0488, bit 1 - 2 */
106 uint32_t plllock_rng; /* 1, reg: 0x0488, bit 3 - 4 */
107 uint32_t ssc_center_spread; /* 0, reg: 0x0494, bit 1 */
108 uint32_t ssc_adj_per; /* 37, reg: 0x498, bit 0 - 9 */
109 uint32_t ssc_spread; /* 0.005 */
110 uint32_t ssc_freq; /* unknown */
111 uint32_t pll_ie_trim; /* 4, reg: 0x0400 */
112 uint32_t pll_ip_trim; /* 4, reg: 0x0404 */
113 uint32_t pll_iptat_trim; /* reg: 0x0410 */
114 uint32_t pll_cpcset_cur; /* 1, reg: 0x04f0, bit 0 - 2 */
115 uint32_t pll_cpmset_cur; /* 1, reg: 0x04f0, bit 3 - 5 */
116
117 uint32_t pll_icpmset; /* 4, reg: 0x04fc, bit 3 - 5 */
118 uint32_t pll_icpcset; /* 4, reg: 0x04fc, bit 0 - 2 */
119
120 uint32_t pll_icpmset_p; /* 0, reg: 0x04f4, bit 0 - 2 */
121 uint32_t pll_icpmset_m; /* 0, reg: 0x04f4, bit 3 - 5 */
122
123 uint32_t pll_icpcset_p; /* 0, reg: 0x04f8, bit 0 - 2 */
124 uint32_t pll_icpcset_m; /* 0, reg: 0x04f8, bit 3 - 5 */
125
126 uint32_t pll_lpf_res1; /* 3, reg: 0x0504, bit 0 - 3 */
127 uint32_t pll_lpf_cap1; /* 11, reg: 0x0500, bit 0 - 3 */
Chandan Uddaraju5fb979f2016-01-29 10:02:20 -0800[diff] [blame^]128 uint32_t pll_lpf_cap2; /* 1, reg: 0x0500, bit 4 - 7 */
Dhaval Patelffb7b592015-03-23 23:34:07 -0700[diff] [blame]129 uint32_t pll_c3ctrl; /* 2, reg: 0x04c4 */
130 uint32_t pll_r3ctrl; /* 1, reg: 0x04c4 */
131};
132
133struct dsi_pll_output {
134 uint32_t pll_txclk_en; /* reg: 0x04c0 */
135 uint32_t dec_start; /* reg: 0x0490 */
136 uint32_t div_frac_start; /* reg: 0x04b4, 0x4b8, 0x04bc */
137 uint32_t ssc_per; /* reg: 0x04a0, 0x04a4 */
138 uint32_t ssc_step_size; /* reg: 0x04a8, 0x04ac */
139 uint32_t plllock_cmp; /* reg: 0x047c, 0x0480, 0x0484 */
140 uint32_t pll_vco_div_ref; /* reg: 0x046c, 0x0470 */
141 uint32_t pll_vco_count; /* reg: 0x0474, 0x0478 */
142 uint32_t pll_kvco_div_ref; /* reg: 0x0440, 0x0444 */
143 uint32_t pll_kvco_count; /* reg: 0x0448, 0x044c */
144 uint32_t pll_misc1; /* reg: 0x04e8 */
145 uint32_t pll_lpf2_postdiv; /* reg: 0x0504 */
146 uint32_t pll_resetsm_cntrl; /* reg: 0x042c */
147 uint32_t pll_resetsm_cntrl2; /* reg: 0x0430 */
148 uint32_t pll_resetsm_cntrl5; /* reg: 0x043c */
149 uint32_t pll_kvco_code; /* reg: 0x0458 */
150
151 uint32_t cmn_clk_cfg0; /* reg: 0x0010 */
152 uint32_t cmn_clk_cfg1; /* reg: 0x0014 */
153 uint32_t cmn_ldo_cntrl; /* reg: 0x004c */
154
155 uint32_t pll_postdiv; /* vco */
156 uint32_t pll_n1div; /* vco */
157 uint32_t pll_n2div; /* hr_oclk3, pixel */
158 uint32_t fcvo;
159};
160
161struct dsi_pll_db {
162 struct dsi_pll_input in;
163 struct dsi_pll_output out;
164};
165
166void mdss_dsi_auto_pll_thulium_config(struct msm_panel_info *pinfo);
167
168#endif