vijay kumar | dd51c59 | 2015-01-05 12:46:28 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
Unnati Gandhi | bd9dbea | 2014-07-17 14:30:29 +0530 | [diff] [blame] | 37 | #include <platform.h> |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 38 | |
| 39 | |
| 40 | /* Mux source select values */ |
| 41 | #define cxo_source_val 0 |
| 42 | #define gpll0_source_val 1 |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 43 | #define cxo_mm_source_val 0 |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 44 | #define gpll0_mm_source_val 5 |
| 45 | #define gpll1_mm_source_val 1 |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 46 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 47 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 48 | /* Clock Operations */ |
| 49 | static struct clk_ops clk_ops_branch = |
| 50 | { |
| 51 | .enable = clock_lib2_branch_clk_enable, |
| 52 | .disable = clock_lib2_branch_clk_disable, |
| 53 | .set_rate = clock_lib2_branch_set_rate, |
| 54 | }; |
| 55 | |
| 56 | static struct clk_ops clk_ops_rcg_mnd = |
| 57 | { |
| 58 | .enable = clock_lib2_rcg_enable, |
| 59 | .set_rate = clock_lib2_rcg_set_rate, |
| 60 | }; |
| 61 | |
| 62 | static struct clk_ops clk_ops_rcg = |
| 63 | { |
| 64 | .enable = clock_lib2_rcg_enable, |
| 65 | .set_rate = clock_lib2_rcg_set_rate, |
| 66 | }; |
| 67 | |
| 68 | static struct clk_ops clk_ops_cxo = |
| 69 | { |
| 70 | .enable = cxo_clk_enable, |
| 71 | .disable = cxo_clk_disable, |
| 72 | }; |
| 73 | |
| 74 | static struct clk_ops clk_ops_pll_vote = |
| 75 | { |
| 76 | .enable = pll_vote_clk_enable, |
| 77 | .disable = pll_vote_clk_disable, |
| 78 | .auto_off = pll_vote_clk_disable, |
| 79 | .is_enabled = pll_vote_clk_is_enabled, |
| 80 | }; |
| 81 | |
| 82 | static struct clk_ops clk_ops_vote = |
| 83 | { |
| 84 | .enable = clock_lib2_vote_clk_enable, |
| 85 | .disable = clock_lib2_vote_clk_disable, |
| 86 | }; |
| 87 | |
| 88 | /* Clock Sources */ |
| 89 | static struct fixed_clk cxo_clk_src = |
| 90 | { |
| 91 | .c = { |
| 92 | .rate = 19200000, |
| 93 | .dbg_name = "cxo_clk_src", |
| 94 | .ops = &clk_ops_cxo, |
| 95 | }, |
| 96 | }; |
| 97 | |
| 98 | static struct pll_vote_clk gpll0_clk_src = |
| 99 | { |
| 100 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 101 | .en_mask = BIT(0), |
| 102 | .status_reg = (void *) GPLL0_STATUS, |
| 103 | .status_mask = BIT(17), |
| 104 | .parent = &cxo_clk_src.c, |
| 105 | |
| 106 | .c = { |
| 107 | .rate = 800000000, |
| 108 | .dbg_name = "gpll0_clk_src", |
| 109 | .ops = &clk_ops_pll_vote, |
| 110 | }, |
| 111 | }; |
| 112 | |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 113 | static struct pll_vote_clk gpll1_clk_src = |
| 114 | { |
| 115 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 116 | .en_mask = BIT(1), |
| 117 | .status_reg = (void *) GPLL1_STATUS, |
| 118 | .status_mask = BIT(17), |
| 119 | .parent = &cxo_clk_src.c, |
| 120 | |
| 121 | .c = { |
| 122 | .rate = 614400000, |
| 123 | .dbg_name = "gpll1_clk_src", |
| 124 | .ops = &clk_ops_pll_vote, |
| 125 | }, |
| 126 | }; |
| 127 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 128 | /* SDCC Clocks */ |
| 129 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 130 | { |
| 131 | F( 144000, cxo, 16, 3, 25), |
| 132 | F( 400000, cxo, 12, 1, 4), |
| 133 | F( 20000000, gpll0, 10, 1, 4), |
| 134 | F( 25000000, gpll0, 16, 1, 2), |
| 135 | F( 50000000, gpll0, 16, 0, 0), |
| 136 | F(100000000, gpll0, 8, 0, 0), |
| 137 | F(177770000, gpll0, 4.5, 0, 0), |
| 138 | F(200000000, gpll0, 4, 0, 0), |
| 139 | F_END |
| 140 | }; |
| 141 | |
| 142 | static struct rcg_clk sdcc1_apps_clk_src = |
| 143 | { |
| 144 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 145 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 146 | .m_reg = (uint32_t *) SDCC1_M, |
| 147 | .n_reg = (uint32_t *) SDCC1_N, |
| 148 | .d_reg = (uint32_t *) SDCC1_D, |
| 149 | |
| 150 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 151 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 152 | .current_freq = &rcg_dummy_freq, |
| 153 | |
| 154 | .c = { |
| 155 | .dbg_name = "sdc1_clk", |
| 156 | .ops = &clk_ops_rcg_mnd, |
| 157 | }, |
| 158 | }; |
| 159 | |
Aparna Mallavarapu | 3f24f3b | 2014-05-15 11:50:37 +0530 | [diff] [blame] | 160 | /* BLSP1_QUP2 Clocks */ |
| 161 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup2_i2c_apps_clk_src[] = |
| 162 | { |
| 163 | F( 96000, cxo, 10, 1, 2), |
| 164 | F( 4800000, cxo, 4, 0, 0), |
| 165 | F( 9600000, cxo, 2, 0, 0), |
| 166 | F( 16000000, gpll0, 10, 1, 5), |
| 167 | F( 19200000, gpll0, 1, 0, 0), |
| 168 | F( 25000000, gpll0, 16, 1, 2), |
| 169 | F( 50000000, gpll0, 16, 0, 0), |
| 170 | F_END |
| 171 | }; |
| 172 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 173 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 174 | { |
| 175 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 176 | .parent = &sdcc1_apps_clk_src.c, |
| 177 | |
| 178 | .c = { |
| 179 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 180 | .ops = &clk_ops_branch, |
| 181 | }, |
| 182 | }; |
| 183 | |
| 184 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 185 | { |
| 186 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 187 | .has_sibling = 1, |
| 188 | |
| 189 | .c = { |
| 190 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 191 | .ops = &clk_ops_branch, |
| 192 | }, |
| 193 | }; |
| 194 | |
| 195 | static struct rcg_clk sdcc2_apps_clk_src = |
| 196 | { |
| 197 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 198 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 199 | .m_reg = (uint32_t *) SDCC2_M, |
| 200 | .n_reg = (uint32_t *) SDCC2_N, |
| 201 | .d_reg = (uint32_t *) SDCC2_D, |
| 202 | |
| 203 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 204 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 205 | .current_freq = &rcg_dummy_freq, |
| 206 | |
| 207 | .c = { |
| 208 | .dbg_name = "sdc2_clk", |
| 209 | .ops = &clk_ops_rcg_mnd, |
| 210 | }, |
| 211 | }; |
| 212 | |
| 213 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 214 | { |
| 215 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 216 | .parent = &sdcc2_apps_clk_src.c, |
| 217 | |
| 218 | .c = { |
| 219 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 220 | .ops = &clk_ops_branch, |
| 221 | }, |
| 222 | }; |
| 223 | |
| 224 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 225 | { |
| 226 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 227 | .has_sibling = 1, |
| 228 | |
| 229 | .c = { |
| 230 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 231 | .ops = &clk_ops_branch, |
| 232 | }, |
| 233 | }; |
| 234 | |
| 235 | /* UART Clocks */ |
| 236 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 237 | { |
| 238 | F( 3686400, gpll0, 1, 72, 15625), |
| 239 | F( 7372800, gpll0, 1, 144, 15625), |
| 240 | F(14745600, gpll0, 1, 288, 15625), |
| 241 | F(16000000, gpll0, 10, 1, 5), |
| 242 | F(19200000, cxo, 1, 0, 0), |
| 243 | F(24000000, gpll0, 1, 3, 100), |
| 244 | F(25000000, gpll0, 16, 1, 2), |
| 245 | F(32000000, gpll0, 1, 1, 25), |
| 246 | F(40000000, gpll0, 1, 1, 20), |
| 247 | F(46400000, gpll0, 1, 29, 500), |
| 248 | F(48000000, gpll0, 1, 3, 50), |
| 249 | F(51200000, gpll0, 1, 8, 125), |
| 250 | F(56000000, gpll0, 1, 7, 100), |
| 251 | F(58982400, gpll0, 1,1152, 15625), |
| 252 | F(60000000, gpll0, 1, 3, 40), |
| 253 | F_END |
| 254 | }; |
| 255 | |
| 256 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 257 | { |
| 258 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 259 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 260 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 261 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 262 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 263 | |
| 264 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 265 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 266 | .current_freq = &rcg_dummy_freq, |
| 267 | |
| 268 | .c = { |
| 269 | .dbg_name = "blsp1_uart2_apps_clk", |
| 270 | .ops = &clk_ops_rcg_mnd, |
| 271 | }, |
| 272 | }; |
| 273 | |
| 274 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 275 | { |
| 276 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 277 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 278 | |
| 279 | .c = { |
| 280 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 281 | .ops = &clk_ops_branch, |
| 282 | }, |
| 283 | }; |
| 284 | |
| 285 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 286 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 287 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 288 | .en_mask = BIT(10), |
| 289 | |
| 290 | .c = { |
| 291 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 292 | .ops = &clk_ops_vote, |
| 293 | }, |
| 294 | }; |
| 295 | |
| 296 | /* USB Clocks */ |
| 297 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 298 | { |
| 299 | F(80000000, gpll0, 10, 0, 0), |
| 300 | F_END |
| 301 | }; |
| 302 | |
| 303 | static struct rcg_clk usb_hs_system_clk_src = |
| 304 | { |
| 305 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 306 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 307 | |
| 308 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 309 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 310 | .current_freq = &rcg_dummy_freq, |
| 311 | |
| 312 | .c = { |
| 313 | .dbg_name = "usb_hs_system_clk", |
| 314 | .ops = &clk_ops_rcg, |
| 315 | }, |
| 316 | }; |
| 317 | |
| 318 | static struct branch_clk gcc_usb_hs_system_clk = |
| 319 | { |
| 320 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 321 | .parent = &usb_hs_system_clk_src.c, |
| 322 | |
| 323 | .c = { |
| 324 | .dbg_name = "gcc_usb_hs_system_clk", |
| 325 | .ops = &clk_ops_branch, |
| 326 | }, |
| 327 | }; |
| 328 | |
| 329 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 330 | { |
| 331 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 332 | .has_sibling = 1, |
| 333 | |
| 334 | .c = { |
| 335 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 336 | .ops = &clk_ops_branch, |
| 337 | }, |
| 338 | }; |
| 339 | |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 340 | /* Display clocks */ |
| 341 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 342 | F_MM(19200000, cxo, 1, 0, 0), |
| 343 | F_END |
| 344 | }; |
| 345 | |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 346 | static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = { |
| 347 | F_MM(19200000, cxo, 1, 0, 0), |
| 348 | F_END |
| 349 | }; |
| 350 | |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 351 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 352 | F( 80000000, gpll0, 10, 0, 0), |
| 353 | F( 100000000, gpll0, 8, 0, 0), |
| 354 | F( 200000000, gpll0, 4, 0, 0), |
| 355 | F( 320000000, gpll0, 2.5, 0, 0), |
| 356 | F_END |
| 357 | }; |
| 358 | |
| 359 | static struct clk_freq_tbl ftbl_mdss_mdp_clk_src[] = { |
| 360 | F_MM( 50000000, gpll0, 16, 0, 0), |
| 361 | F_MM( 80000000, gpll0, 10, 0, 0), |
| 362 | F_MM( 100000000, gpll0, 8, 0, 0), |
| 363 | F_MM( 153600000, gpll1, 4, 0, 0), |
| 364 | F_MM( 160000000, gpll0, 5, 0, 0), |
| 365 | F_MM( 177780000, gpll0, 4.5, 0, 0), |
| 366 | F_MM( 200000000, gpll0, 4, 0, 0), |
| 367 | F_MM( 266670000, gpll0, 3, 0, 0), |
| 368 | F_MM( 307200000, gpll1, 2, 0, 0), |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 369 | F_END |
| 370 | }; |
| 371 | |
| 372 | static struct rcg_clk dsi_esc0_clk_src = { |
| 373 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 374 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 375 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 376 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 377 | |
| 378 | .c = { |
| 379 | .dbg_name = "dsi_esc0_clk_src", |
| 380 | .ops = &clk_ops_rcg, |
| 381 | }, |
| 382 | }; |
| 383 | |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 384 | static struct rcg_clk dsi_esc1_clk_src = { |
| 385 | .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR, |
| 386 | .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR, |
| 387 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 388 | .freq_tbl = ftbl_mdss_esc1_1_clk, |
| 389 | |
| 390 | .c = { |
| 391 | .dbg_name = "dsi_esc1_clk_src", |
| 392 | .ops = &clk_ops_rcg, |
| 393 | }, |
| 394 | }; |
| 395 | |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 396 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 397 | F_MM(19200000, cxo, 1, 0, 0), |
| 398 | F_END |
| 399 | }; |
| 400 | |
| 401 | static struct rcg_clk vsync_clk_src = { |
| 402 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 403 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 404 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 405 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 406 | |
| 407 | .c = { |
| 408 | .dbg_name = "vsync_clk_src", |
| 409 | .ops = &clk_ops_rcg, |
| 410 | }, |
| 411 | }; |
| 412 | |
| 413 | static struct branch_clk mdss_esc0_clk = { |
| 414 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 415 | .parent = &dsi_esc0_clk_src.c, |
| 416 | .has_sibling = 0, |
| 417 | |
| 418 | .c = { |
| 419 | .dbg_name = "mdss_esc0_clk", |
| 420 | .ops = &clk_ops_branch, |
| 421 | }, |
| 422 | }; |
| 423 | |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 424 | static struct branch_clk mdss_esc1_clk = { |
| 425 | .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR, |
| 426 | .parent = &dsi_esc1_clk_src.c, |
| 427 | .has_sibling = 0, |
| 428 | |
| 429 | .c = { |
| 430 | .dbg_name = "mdss_esc1_clk", |
| 431 | .ops = &clk_ops_branch, |
| 432 | }, |
| 433 | }; |
| 434 | |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 435 | static struct branch_clk mdss_axi_clk = { |
| 436 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 437 | .has_sibling = 1, |
| 438 | |
| 439 | .c = { |
| 440 | .dbg_name = "mdss_axi_clk", |
| 441 | .ops = &clk_ops_branch, |
| 442 | }, |
| 443 | }; |
| 444 | |
| 445 | static struct branch_clk mdp_ahb_clk = { |
| 446 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 447 | .has_sibling = 1, |
| 448 | |
| 449 | .c = { |
| 450 | .dbg_name = "mdp_ahb_clk", |
| 451 | .ops = &clk_ops_branch, |
| 452 | }, |
| 453 | }; |
| 454 | |
| 455 | static struct rcg_clk mdss_mdp_clk_src = { |
| 456 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 457 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 458 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 459 | .freq_tbl = ftbl_mdp_clk, |
| 460 | .current_freq = &rcg_dummy_freq, |
| 461 | |
| 462 | .c = { |
| 463 | .dbg_name = "mdss_mdp_clk_src", |
| 464 | .ops = &clk_ops_rcg, |
| 465 | }, |
| 466 | }; |
| 467 | |
| 468 | static struct branch_clk mdss_mdp_clk = { |
| 469 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 470 | .parent = &mdss_mdp_clk_src.c, |
| 471 | .has_sibling = 0, |
| 472 | |
| 473 | .c = { |
| 474 | .dbg_name = "mdss_mdp_clk", |
| 475 | .ops = &clk_ops_branch, |
| 476 | }, |
| 477 | }; |
| 478 | |
| 479 | static struct branch_clk mdss_vsync_clk = { |
Unnati Gandhi | bd9dbea | 2014-07-17 14:30:29 +0530 | [diff] [blame] | 480 | .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR, |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 481 | .parent = &vsync_clk_src.c, |
| 482 | .has_sibling = 0, |
| 483 | |
| 484 | .c = { |
| 485 | .dbg_name = "mdss_vsync_clk", |
| 486 | .ops = &clk_ops_branch, |
| 487 | }, |
| 488 | }; |
| 489 | |
Aparna Mallavarapu | 2e89967 | 2014-04-22 15:12:05 +0530 | [diff] [blame] | 490 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 491 | F(160000000, gpll0, 5, 0, 0), |
| 492 | F_END |
| 493 | }; |
| 494 | |
| 495 | static struct rcg_clk ce1_clk_src = { |
| 496 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 497 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 498 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 499 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 500 | .current_freq = &rcg_dummy_freq, |
| 501 | |
| 502 | .c = { |
| 503 | .dbg_name = "ce1_clk_src", |
| 504 | .ops = &clk_ops_rcg, |
| 505 | }, |
| 506 | }; |
| 507 | |
| 508 | static struct vote_clk gcc_ce1_clk = { |
| 509 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 510 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 511 | .en_mask = BIT(2), |
| 512 | |
| 513 | .c = { |
| 514 | .dbg_name = "gcc_ce1_clk", |
| 515 | .ops = &clk_ops_vote, |
| 516 | }, |
| 517 | }; |
| 518 | |
| 519 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 520 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 521 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 522 | .en_mask = BIT(0), |
| 523 | |
| 524 | .c = { |
| 525 | .dbg_name = "gcc_ce1_ahb_clk", |
| 526 | .ops = &clk_ops_vote, |
| 527 | }, |
| 528 | }; |
| 529 | |
| 530 | static struct vote_clk gcc_ce1_axi_clk = { |
| 531 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 532 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 533 | .en_mask = BIT(1), |
| 534 | |
| 535 | .c = { |
| 536 | .dbg_name = "gcc_ce1_axi_clk", |
| 537 | .ops = &clk_ops_vote, |
| 538 | }, |
| 539 | }; |
| 540 | |
Aparna Mallavarapu | 3f24f3b | 2014-05-15 11:50:37 +0530 | [diff] [blame] | 541 | |
| 542 | static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src = |
| 543 | { |
| 544 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP2_CMD_RCGR, |
| 545 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP2_CFG_RCGR, |
| 546 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 547 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 548 | .current_freq = &rcg_dummy_freq, |
| 549 | |
| 550 | .c = { |
| 551 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 552 | .ops = &clk_ops_rcg, |
| 553 | }, |
| 554 | }; |
| 555 | |
| 556 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
Unnati Gandhi | bd9dbea | 2014-07-17 14:30:29 +0530 | [diff] [blame] | 557 | .cbcr_reg = (uint32_t *) GCC_BLSP1_QUP2_APPS_CBCR, |
Aparna Mallavarapu | 3f24f3b | 2014-05-15 11:50:37 +0530 | [diff] [blame] | 558 | .parent = &gcc_blsp1_qup2_i2c_apps_clk_src.c, |
| 559 | |
| 560 | .c = { |
| 561 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 562 | .ops = &clk_ops_branch, |
| 563 | }, |
| 564 | }; |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 565 | /* Clock lookup table */ |
| 566 | static struct clk_lookup msm_clocks_8916[] = |
| 567 | { |
| 568 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 569 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 570 | |
| 571 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 572 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 573 | |
| 574 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 575 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 576 | |
| 577 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 578 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 579 | |
| 580 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 581 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 582 | CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c), |
Padmanabhan Komanduru | dd778b9 | 2014-03-21 19:25:17 +0530 | [diff] [blame] | 583 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 584 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 585 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 586 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
Aparna Mallavarapu | 2e89967 | 2014-04-22 15:12:05 +0530 | [diff] [blame] | 587 | |
| 588 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 589 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 590 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 591 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
Aparna Mallavarapu | 3f24f3b | 2014-05-15 11:50:37 +0530 | [diff] [blame] | 592 | |
| 593 | CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c), |
| 594 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c), |
| 595 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c), |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 596 | }; |
| 597 | |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 598 | void msm8939_clock_override() |
| 599 | { |
| 600 | mdss_mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_src; |
| 601 | } |
| 602 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 603 | void platform_clock_init(void) |
| 604 | { |
vijay kumar | dd51c59 | 2015-01-05 12:46:28 +0530 | [diff] [blame] | 605 | if (platform_is_msm8939() || platform_is_msm8929()) |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 606 | msm8939_clock_override(); |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 607 | clk_init(msm_clocks_8916, ARRAY_SIZE(msm_clocks_8916)); |
| 608 | } |