Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 1 | /* |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 2 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 11 | * * Neither the name of The Linux Foundation nor |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <err.h> |
| 33 | #include <limits.h> |
| 34 | #include <clock.h> |
Amol Jadi | c2c941c | 2012-06-22 00:02:01 -0700 | [diff] [blame] | 35 | #include <clock_pll.h> |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 36 | #include <clock-local.h> |
| 37 | #include <bits.h> |
| 38 | #include <platform/iomap.h> |
| 39 | #include <platform/clock.h> |
| 40 | #include <platform/timer.h> |
| 41 | #include <sys/types.h> |
| 42 | |
| 43 | extern void dmb(void); |
| 44 | |
| 45 | static int xo_clk_enable(struct clk *clk) |
| 46 | { |
| 47 | /* Assuming pxo already running */ |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | static void xo_clk_disable(struct clk *clk) |
| 52 | { |
| 53 | /* Do nothing */ |
| 54 | } |
| 55 | |
| 56 | static struct clk_ops clk_ops_xo = { |
| 57 | .enable = xo_clk_enable, |
| 58 | .disable = xo_clk_disable, |
| 59 | .get_rate = fixed_clk_get_rate, |
| 60 | }; |
| 61 | |
| 62 | static struct fixed_clk pxo_clk = { |
| 63 | .rate = 27000000, |
| 64 | .c = { |
| 65 | .dbg_name = "pxo_clk", |
| 66 | .ops = &clk_ops_xo, |
| 67 | }, |
| 68 | }; |
| 69 | |
| 70 | static struct fixed_clk cxo_clk = { |
| 71 | .rate = 19200000, |
| 72 | .c = { |
| 73 | .dbg_name = "cxo_clk", |
| 74 | .ops = &clk_ops_xo, |
| 75 | }, |
| 76 | }; |
| 77 | |
| 78 | /* |
| 79 | * PLL Clocks |
| 80 | */ |
Amol Jadi | c2c941c | 2012-06-22 00:02:01 -0700 | [diff] [blame] | 81 | struct clk_ops clk_ops_pll_vote = { |
| 82 | .enable = pll_vote_clk_enable, |
| 83 | .disable = pll_vote_clk_disable, |
| 84 | .is_enabled = pll_vote_clk_is_enabled, |
| 85 | .get_rate = pll_vote_clk_get_rate, |
| 86 | .get_parent = pll_vote_clk_get_parent, |
| 87 | }; |
| 88 | |
| 89 | struct clk_ops clk_ops_pll = { |
| 90 | .enable = pll_clk_enable, |
| 91 | .disable = pll_clk_disable, |
| 92 | .get_rate = pll_clk_get_rate, |
| 93 | .get_parent = pll_clk_get_parent, |
| 94 | }; |
| 95 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 96 | static struct pll_clk pll2_clk = { |
| 97 | .rate = 800000000, |
| 98 | .mode_reg = (void *)MM_PLL1_MODE_REG, |
| 99 | .parent = &pxo_clk.c, |
| 100 | .c = { |
| 101 | .dbg_name = "pll2_clk", |
| 102 | .ops = &clk_ops_pll, |
| 103 | }, |
| 104 | }; |
| 105 | |
| 106 | static struct pll_clk pll3_clk = { |
| 107 | .rate = 1200000000, |
| 108 | .mode_reg = (void *)BB_PLL3_MODE_REG, |
| 109 | .parent = &pxo_clk.c, |
| 110 | .c = { |
| 111 | .dbg_name = "pll3_clk", |
| 112 | .ops = &clk_ops_pll, |
| 113 | }, |
| 114 | }; |
| 115 | |
| 116 | static struct pll_vote_clk pll8_clk = { |
| 117 | .rate = 384000000, |
| 118 | .en_reg = (void *)BB_PLL_ENA_SC0_REG, |
| 119 | .en_mask = BIT(8), |
| 120 | .status_reg = (void *)BB_PLL8_STATUS_REG, |
Amol Jadi | c2c941c | 2012-06-22 00:02:01 -0700 | [diff] [blame] | 121 | .status_mask = BIT(16), |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 122 | .parent = &pxo_clk.c, |
| 123 | .c = { |
| 124 | .dbg_name = "pll8_clk", |
| 125 | .ops = &clk_ops_pll_vote, |
| 126 | }, |
| 127 | }; |
| 128 | |
| 129 | static struct clk_ops soc_clk_ops_8960 = { |
| 130 | .enable = local_clk_enable, |
| 131 | .disable = local_clk_disable, |
| 132 | .set_rate = local_clk_set_rate, |
| 133 | .get_rate = local_clk_get_rate, |
| 134 | .is_enabled = local_clk_is_enabled, |
| 135 | .round_rate = local_clk_round_rate, |
| 136 | .get_parent = local_clk_get_parent, |
| 137 | }; |
| 138 | |
| 139 | static struct clk_ops clk_ops_branch = { |
| 140 | .enable = branch_clk_enable, |
| 141 | .disable = branch_clk_disable, |
| 142 | .is_enabled = branch_clk_is_enabled, |
| 143 | .get_parent = branch_clk_get_parent, |
| 144 | .set_parent = branch_clk_set_parent, |
| 145 | }; |
| 146 | |
| 147 | /* |
| 148 | * Peripheral Clocks |
| 149 | */ |
| 150 | #define CLK_GSBI_UART(i, n, h_r, h_b) \ |
| 151 | struct rcg_clk i##_clk = { \ |
| 152 | .b = { \ |
| 153 | .ctl_reg = (void *)GSBIn_UART_APPS_NS_REG(n), \ |
| 154 | .en_mask = BIT(9), \ |
| 155 | .reset_reg = (void *)GSBIn_RESET_REG(n), \ |
| 156 | .reset_mask = BIT(0), \ |
| 157 | .halt_reg = (void *)h_r, \ |
| 158 | .halt_bit = h_b, \ |
| 159 | }, \ |
| 160 | .ns_reg = (void *)GSBIn_UART_APPS_NS_REG(n), \ |
| 161 | .md_reg = (void *)GSBIn_UART_APPS_MD_REG(n), \ |
| 162 | .root_en_mask = BIT(11), \ |
| 163 | .ns_mask = (BM(31, 16) | BM(6, 0)), \ |
| 164 | .set_rate = set_rate_mnd, \ |
| 165 | .freq_tbl = clk_tbl_gsbi_uart, \ |
| 166 | .current_freq = &local_dummy_freq, \ |
| 167 | .c = { \ |
| 168 | .dbg_name = #i "_clk", \ |
| 169 | .ops = &soc_clk_ops_8960, \ |
| 170 | }, \ |
| 171 | } |
| 172 | #define F_GSBI_UART(f, s, d, m, n) \ |
| 173 | { \ |
| 174 | .freq_hz = f, \ |
| 175 | .src_clk = &s##_clk.c, \ |
| 176 | .md_val = MD16(m, n), \ |
| 177 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 178 | .mnd_en_mask = BIT(8) * !!(n), \ |
| 179 | } |
| 180 | static struct clk_freq_tbl clk_tbl_gsbi_uart[] = { |
| 181 | F_GSBI_UART( 1843200, pll8, 1, 3, 625), |
| 182 | F_GSBI_UART( 3686400, pll8, 1, 6, 625), |
| 183 | F_GSBI_UART( 7372800, pll8, 1, 12, 625), |
| 184 | F_GSBI_UART(14745600, pll8, 1, 24, 625), |
| 185 | F_GSBI_UART(16000000, pll8, 4, 1, 6), |
| 186 | F_GSBI_UART(24000000, pll8, 4, 1, 4), |
| 187 | F_GSBI_UART(32000000, pll8, 4, 1, 3), |
| 188 | F_GSBI_UART(40000000, pll8, 1, 5, 48), |
| 189 | F_GSBI_UART(46400000, pll8, 1, 29, 240), |
| 190 | F_GSBI_UART(48000000, pll8, 4, 1, 2), |
| 191 | F_GSBI_UART(51200000, pll8, 1, 2, 15), |
| 192 | F_GSBI_UART(56000000, pll8, 1, 7, 48), |
| 193 | F_GSBI_UART(58982400, pll8, 1, 96, 625), |
| 194 | F_GSBI_UART(64000000, pll8, 2, 1, 3), |
| 195 | F_END |
| 196 | }; |
| 197 | |
| 198 | static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10); |
| 199 | static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6); |
| 200 | static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2); |
| 201 | static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26); |
| 202 | static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22); |
| 203 | static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18); |
| 204 | static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14); |
| 205 | static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10); |
| 206 | static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6); |
| 207 | static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2); |
| 208 | static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17); |
| 209 | static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13); |
| 210 | |
| 211 | #define CLK_GSBI_QUP(i, n, h_r, h_b) \ |
| 212 | struct rcg_clk i##_clk = { \ |
| 213 | .b = { \ |
| 214 | .ctl_reg = (void *)GSBIn_QUP_APPS_NS_REG(n), \ |
| 215 | .en_mask = BIT(9), \ |
| 216 | .reset_reg = (void *)GSBIn_RESET_REG(n), \ |
| 217 | .reset_mask = BIT(0), \ |
| 218 | .halt_reg = (void *)h_r, \ |
| 219 | .halt_bit = h_b, \ |
| 220 | }, \ |
| 221 | .ns_reg = (void *)GSBIn_QUP_APPS_NS_REG(n), \ |
| 222 | .md_reg = (void *)GSBIn_QUP_APPS_MD_REG(n), \ |
| 223 | .root_en_mask = BIT(11), \ |
| 224 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 225 | .set_rate = set_rate_mnd, \ |
| 226 | .freq_tbl = clk_tbl_gsbi_qup, \ |
| 227 | .current_freq = &local_dummy_freq, \ |
| 228 | .c = { \ |
| 229 | .dbg_name = #i "_clk", \ |
| 230 | .ops = &soc_clk_ops_8960, \ |
| 231 | }, \ |
| 232 | } |
| 233 | #define F_GSBI_QUP(f, s, d, m, n) \ |
| 234 | { \ |
| 235 | .freq_hz = f, \ |
| 236 | .src_clk = &s##_clk.c, \ |
| 237 | .md_val = MD8(16, m, 0, n), \ |
| 238 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 239 | .mnd_en_mask = BIT(8) * !!(n), \ |
| 240 | } |
| 241 | static struct clk_freq_tbl clk_tbl_gsbi_qup[] = { |
| 242 | F_GSBI_QUP( 1100000, pxo, 1, 2, 49), |
| 243 | F_GSBI_QUP( 5400000, pxo, 1, 1, 5), |
| 244 | F_GSBI_QUP(10800000, pxo, 1, 2, 5), |
| 245 | F_GSBI_QUP(15060000, pll8, 1, 2, 51), |
| 246 | F_GSBI_QUP(24000000, pll8, 4, 1, 4), |
| 247 | F_GSBI_QUP(25600000, pll8, 1, 1, 15), |
| 248 | F_GSBI_QUP(27000000, pxo, 1, 0, 0), |
| 249 | F_GSBI_QUP(48000000, pll8, 4, 1, 2), |
| 250 | F_GSBI_QUP(51200000, pll8, 1, 2, 15), |
| 251 | F_END |
| 252 | }; |
| 253 | |
| 254 | static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9); |
| 255 | static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4); |
| 256 | static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0); |
| 257 | static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24); |
| 258 | static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20); |
| 259 | static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16); |
| 260 | static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12); |
| 261 | static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8); |
| 262 | static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4); |
| 263 | static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0); |
| 264 | static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15); |
| 265 | static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11); |
| 266 | |
| 267 | #define F_USB(f, s, d, m, n) \ |
| 268 | { \ |
| 269 | .freq_hz = f, \ |
| 270 | .src_clk = &s##_clk.c, \ |
| 271 | .md_val = MD8(16, m, 0, n), \ |
| 272 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 273 | .mnd_en_mask = BIT(8) * !!(n), \ |
| 274 | } |
| 275 | static struct clk_freq_tbl clk_tbl_usb[] = { |
| 276 | F_USB(60000000, pll8, 1, 5, 32), |
| 277 | F_END |
| 278 | }; |
| 279 | |
| 280 | static struct rcg_clk usb_hs1_xcvr_clk = { |
| 281 | .b = { |
| 282 | .ctl_reg = (void *)USB_HS1_XCVR_FS_CLK_NS_REG, |
| 283 | .en_mask = BIT(9), |
| 284 | .reset_reg = (void *)USB_HS1_RESET_REG, |
| 285 | .reset_mask = BIT(0), |
| 286 | .halt_reg = (void *)CLK_HALT_DFAB_STATE_REG, |
| 287 | .halt_bit = 0, |
| 288 | }, |
| 289 | .ns_reg = (void *)USB_HS1_XCVR_FS_CLK_NS_REG, |
| 290 | .md_reg = (void *)USB_HS1_XCVR_FS_CLK_MD_REG, |
| 291 | .root_en_mask = BIT(11), |
| 292 | .ns_mask = (BM(23, 16) | BM(6, 0)), |
| 293 | .set_rate = set_rate_mnd, |
| 294 | .freq_tbl = clk_tbl_usb, |
| 295 | .current_freq = &local_dummy_freq, |
| 296 | .c = { |
| 297 | .dbg_name = "usb_hs1_xcvr_clk", |
| 298 | .ops = &soc_clk_ops_8960, |
| 299 | }, |
| 300 | }; |
| 301 | |
| 302 | #define CLK_SDC(i, n, h_r, h_c, h_b) \ |
| 303 | struct rcg_clk i##_clk = { \ |
| 304 | .b = { \ |
| 305 | .ctl_reg = (void *)SDCn_APPS_CLK_NS_REG(n), \ |
| 306 | .en_mask = BIT(9), \ |
| 307 | .reset_reg = (void *)SDCn_RESET_REG(n), \ |
| 308 | .reset_mask = BIT(0), \ |
| 309 | .halt_reg = (void *)h_r, \ |
| 310 | .halt_check = h_c, \ |
| 311 | .halt_bit = h_b, \ |
| 312 | }, \ |
| 313 | .ns_reg = (void *)SDCn_APPS_CLK_NS_REG(n), \ |
| 314 | .md_reg = (void *)SDCn_APPS_CLK_MD_REG(n), \ |
| 315 | .root_en_mask = BIT(11), \ |
| 316 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 317 | .set_rate = set_rate_mnd, \ |
| 318 | .freq_tbl = clk_tbl_sdc, \ |
| 319 | .current_freq = &local_dummy_freq, \ |
| 320 | .c = { \ |
| 321 | .dbg_name = #i "_clk", \ |
| 322 | .ops = &soc_clk_ops_8960, \ |
| 323 | }, \ |
| 324 | } |
| 325 | #define F_SDC(f, s, d, m, n) \ |
| 326 | { \ |
| 327 | .freq_hz = f, \ |
| 328 | .src_clk = &s##_clk.c, \ |
| 329 | .md_val = MD8(16, m, 0, n), \ |
| 330 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 331 | .mnd_en_mask = BIT(8) * !!(n), \ |
| 332 | } |
| 333 | static struct clk_freq_tbl clk_tbl_sdc[] = { |
| 334 | F_SDC( 144000, pxo, 3, 2, 125), |
| 335 | F_SDC( 400000, pll8, 4, 1, 240), |
| 336 | F_SDC( 16000000, pll8, 4, 1, 6), |
| 337 | F_SDC( 17070000, pll8, 1, 2, 45), |
| 338 | F_SDC( 20210000, pll8, 1, 1, 19), |
| 339 | F_SDC( 24000000, pll8, 4, 1, 4), |
| 340 | F_SDC( 48000000, pll8, 4, 1, 2), |
| 341 | F_SDC( 64000000, pll8, 3, 1, 2), |
| 342 | F_SDC( 96000000, pll8, 4, 0, 0), |
| 343 | F_SDC(192000000, pll8, 2, 0, 0), |
| 344 | F_END |
| 345 | }; |
| 346 | |
| 347 | static CLK_SDC(sdc1, 1, CLK_HALT_DFAB_STATE_REG, HALT, 6); |
| 348 | static CLK_SDC(sdc2, 2, CLK_HALT_DFAB_STATE_REG, HALT, 5); |
| 349 | static CLK_SDC(sdc3, 3, CLK_HALT_DFAB_STATE_REG, HALT, 4); |
| 350 | static CLK_SDC(sdc4, 4, CLK_HALT_DFAB_STATE_REG, HALT, 3); |
| 351 | static CLK_SDC(sdc5, 5, CLK_HALT_DFAB_STATE_REG, HALT, 2); |
| 352 | |
| 353 | static struct branch_clk ce1_core_clk = { |
| 354 | .b = { |
| 355 | .ctl_reg = (void *)CE1_CORE_CLK_CTL_REG, |
| 356 | .en_mask = BIT(4), |
| 357 | .halt_reg = (void *)CLK_HALT_CFPB_STATEC_REG, |
| 358 | .halt_bit = 27, |
| 359 | }, |
| 360 | .c = { |
| 361 | .dbg_name = "ce1_core_clk", |
| 362 | .ops = &clk_ops_branch, |
| 363 | }, |
| 364 | }; |
| 365 | static struct branch_clk ce1_p_clk = { |
| 366 | .b = { |
| 367 | .ctl_reg = (void *)CE1_HCLK_CTL_REG, |
| 368 | .en_mask = BIT(4), |
| 369 | .halt_reg = (void *)CLK_HALT_CFPB_STATEC_REG, |
| 370 | .halt_bit = 1, |
| 371 | }, |
| 372 | .c = { |
| 373 | .dbg_name = "ce1_p_clk", |
| 374 | .ops = &clk_ops_branch, |
| 375 | }, |
| 376 | }; |
| 377 | |
| 378 | #define F_CE(f, s, d) \ |
| 379 | { \ |
| 380 | .freq_hz = f, \ |
| 381 | .src_clk = &s##_clk.c, \ |
| 382 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
| 383 | } |
| 384 | static struct clk_freq_tbl clk_tbl_ce3[] = { |
| 385 | F_CE( 48000000, pll8, 8), |
| 386 | F_CE(100000000, pll3, 12), |
| 387 | F_END |
| 388 | }; |
| 389 | |
| 390 | static struct rcg_clk ce3_src_clk = { |
| 391 | .b = { |
| 392 | .ctl_reg = (void *)CE3_CLK_SRC_NS_REG, |
| 393 | .en_mask = 0, |
| 394 | .halt_check = NOCHECK, |
| 395 | }, |
| 396 | .ns_reg = (void *)CE3_CLK_SRC_NS_REG, |
| 397 | .root_en_mask = BIT(7), |
| 398 | .ns_mask = BM(6, 0), |
| 399 | .set_rate = set_rate_nop, |
| 400 | .freq_tbl = clk_tbl_ce3, |
| 401 | .current_freq = &local_dummy_freq, |
| 402 | .c = { |
| 403 | .dbg_name = "ce3_src_clk", |
| 404 | .ops = &soc_clk_ops_8960, |
| 405 | }, |
| 406 | }; |
| 407 | |
| 408 | static struct branch_clk ce3_core_clk = { |
| 409 | .b = { |
| 410 | .ctl_reg = (void *)CE3_CORE_CLK_CTL_REG, |
| 411 | .en_mask = BIT(4), |
| 412 | .halt_reg = (void *)CLK_HALT_GSS_KPSS_MISC_STATE_REG, |
| 413 | .halt_bit = 5, |
| 414 | }, |
| 415 | .parent = &ce3_src_clk.c, |
| 416 | .c = { |
| 417 | .dbg_name = "ce3_core_clk", |
| 418 | .ops = &clk_ops_branch, |
| 419 | }, |
| 420 | }; |
| 421 | |
| 422 | static struct branch_clk ce3_p_clk = { |
| 423 | .b = { |
| 424 | .ctl_reg = (void *)CE3_HCLK_CTL_REG, |
| 425 | .en_mask = BIT(4), |
| 426 | .halt_reg = (void *)CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 427 | .halt_bit = 16, |
| 428 | }, |
| 429 | .parent = &ce3_src_clk.c, |
| 430 | .c = { |
| 431 | .dbg_name = "ce3_p_clk", |
| 432 | .ops = &clk_ops_branch, |
| 433 | }, |
| 434 | }; |
| 435 | |
| 436 | static struct branch_clk gsbi1_p_clk = { |
| 437 | .b = { |
| 438 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(1), |
| 439 | .en_mask = BIT(4), |
| 440 | .halt_reg = (void *)CLK_HALT_CFPB_STATEA_REG, |
| 441 | .halt_bit = 11, |
| 442 | }, |
| 443 | .c = { |
| 444 | .dbg_name = "gsbi1_p_clk", |
| 445 | .ops = &clk_ops_branch, |
| 446 | }, |
| 447 | }; |
| 448 | |
| 449 | static struct branch_clk gsbi2_p_clk = { |
| 450 | .b = { |
| 451 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(2), |
| 452 | .en_mask = BIT(4), |
| 453 | .halt_reg = (void *)CLK_HALT_CFPB_STATEA_REG, |
| 454 | .halt_bit = 7, |
| 455 | }, |
| 456 | .c = { |
| 457 | .dbg_name = "gsbi2_p_clk", |
| 458 | .ops = &clk_ops_branch, |
| 459 | }, |
| 460 | }; |
| 461 | |
| 462 | static struct branch_clk gsbi3_p_clk = { |
| 463 | .b = { |
| 464 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(3), |
| 465 | .en_mask = BIT(4), |
| 466 | .halt_reg = (void *)CLK_HALT_CFPB_STATEA_REG, |
| 467 | .halt_bit = 3, |
| 468 | }, |
| 469 | .c = { |
| 470 | .dbg_name = "gsbi3_p_clk", |
| 471 | .ops = &clk_ops_branch, |
| 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static struct branch_clk gsbi4_p_clk = { |
| 476 | .b = { |
| 477 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(4), |
| 478 | .en_mask = BIT(4), |
| 479 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 480 | .halt_bit = 27, |
| 481 | }, |
| 482 | .c = { |
| 483 | .dbg_name = "gsbi4_p_clk", |
| 484 | .ops = &clk_ops_branch, |
| 485 | }, |
| 486 | }; |
| 487 | |
| 488 | static struct branch_clk gsbi5_p_clk = { |
| 489 | .b = { |
| 490 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(5), |
| 491 | .en_mask = BIT(4), |
| 492 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 493 | .halt_bit = 23, |
| 494 | }, |
| 495 | .c = { |
| 496 | .dbg_name = "gsbi5_p_clk", |
| 497 | .ops = &clk_ops_branch, |
| 498 | }, |
| 499 | }; |
| 500 | |
| 501 | static struct branch_clk gsbi6_p_clk = { |
| 502 | .b = { |
| 503 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(6), |
| 504 | .en_mask = BIT(4), |
| 505 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 506 | .halt_bit = 19, |
| 507 | }, |
| 508 | .c = { |
| 509 | .dbg_name = "gsbi6_p_clk", |
| 510 | .ops = &clk_ops_branch, |
| 511 | }, |
| 512 | }; |
| 513 | |
| 514 | static struct branch_clk gsbi7_p_clk = { |
| 515 | .b = { |
| 516 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(7), |
| 517 | .en_mask = BIT(4), |
| 518 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 519 | .halt_bit = 15, |
| 520 | }, |
| 521 | .c = { |
| 522 | .dbg_name = "gsbi7_p_clk", |
| 523 | .ops = &clk_ops_branch, |
| 524 | }, |
| 525 | }; |
| 526 | |
| 527 | static struct branch_clk gsbi8_p_clk = { |
| 528 | .b = { |
| 529 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(8), |
| 530 | .en_mask = BIT(4), |
| 531 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 532 | .halt_bit = 11, |
| 533 | }, |
| 534 | .c = { |
| 535 | .dbg_name = "gsbi8_p_clk", |
| 536 | .ops = &clk_ops_branch, |
| 537 | }, |
| 538 | }; |
| 539 | |
| 540 | static struct branch_clk gsbi9_p_clk = { |
| 541 | .b = { |
| 542 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(9), |
| 543 | .en_mask = BIT(4), |
| 544 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 545 | .halt_bit = 7, |
| 546 | }, |
| 547 | .c = { |
| 548 | .dbg_name = "gsbi9_p_clk", |
| 549 | .ops = &clk_ops_branch, |
| 550 | }, |
| 551 | }; |
| 552 | |
| 553 | static struct branch_clk gsbi10_p_clk = { |
| 554 | .b = { |
| 555 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(10), |
| 556 | .en_mask = BIT(4), |
| 557 | .halt_reg = (void *)CLK_HALT_CFPB_STATEB_REG, |
| 558 | .halt_bit = 3, |
| 559 | }, |
| 560 | .c = { |
| 561 | .dbg_name = "gsbi10_p_clk", |
| 562 | .ops = &clk_ops_branch, |
| 563 | }, |
| 564 | }; |
| 565 | |
| 566 | static struct branch_clk gsbi11_p_clk = { |
| 567 | .b = { |
| 568 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(11), |
| 569 | .en_mask = BIT(4), |
| 570 | .halt_reg = (void *)CLK_HALT_CFPB_STATEC_REG, |
| 571 | .halt_bit = 18, |
| 572 | }, |
| 573 | .c = { |
| 574 | .dbg_name = "gsbi11_p_clk", |
| 575 | .ops = &clk_ops_branch, |
| 576 | }, |
| 577 | }; |
| 578 | |
| 579 | static struct branch_clk gsbi12_p_clk = { |
| 580 | .b = { |
| 581 | .ctl_reg = (void *)GSBIn_HCLK_CTL_REG(12), |
| 582 | .en_mask = BIT(4), |
| 583 | .halt_reg = (void *)CLK_HALT_CFPB_STATEC_REG, |
| 584 | .halt_bit = 14, |
| 585 | }, |
| 586 | .c = { |
| 587 | .dbg_name = "gsbi12_p_clk", |
| 588 | .ops = &clk_ops_branch, |
| 589 | }, |
| 590 | }; |
| 591 | |
| 592 | static struct branch_clk mdp_axi_clk = { |
| 593 | .b = { |
| 594 | .ctl_reg = (void *)MAXI_EN_REG, |
| 595 | .en_mask = BIT(23), |
| 596 | .reset_reg = (void *)SW_RESET_AXI_REG, |
| 597 | .reset_mask = BIT(13), |
| 598 | .halt_reg = (void *)DBG_BUS_VEC_E_REG, |
| 599 | .halt_bit = 8, |
| 600 | }, |
| 601 | .c = { |
| 602 | .dbg_name = "mdp_axi_clk", |
| 603 | .ops = &clk_ops_branch, |
| 604 | }, |
| 605 | }; |
| 606 | |
| 607 | #define F_MDP(f, s, m, n) \ |
| 608 | { \ |
| 609 | .freq_hz = f, \ |
| 610 | .src_clk = &s##_clk.c, \ |
| 611 | .md_val = MD8(8, m, 0, n), \ |
| 612 | .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 613 | .ctl_val = CC_BANKED(9, 6, n), \ |
| 614 | .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \ |
| 615 | } |
| 616 | static struct clk_freq_tbl clk_tbl_mdp[] = { |
| 617 | F_MDP( 9600000, pll8, 1, 40), |
| 618 | F_MDP( 13710000, pll8, 1, 28), |
| 619 | F_MDP( 27000000, pxo, 0, 0), |
| 620 | F_MDP( 29540000, pll8, 1, 13), |
| 621 | F_MDP( 34910000, pll8, 1, 11), |
| 622 | F_MDP( 38400000, pll8, 1, 10), |
| 623 | F_MDP( 59080000, pll8, 2, 13), |
| 624 | F_MDP( 76800000, pll8, 1, 5), |
| 625 | F_MDP( 85330000, pll8, 2, 9), |
| 626 | F_MDP( 96000000, pll8, 1, 4), |
| 627 | F_MDP(128000000, pll8, 1, 3), |
| 628 | F_MDP(160000000, pll2, 1, 5), |
| 629 | F_MDP(177780000, pll2, 2, 9), |
| 630 | F_MDP(200000000, pll2, 1, 4), |
| 631 | F_END |
| 632 | }; |
| 633 | |
| 634 | static struct bank_masks bmnd_info_mdp = { |
| 635 | .bank_sel_mask = BIT(11), |
| 636 | .bank0_mask = { |
| 637 | .md_reg = (void *)MDP_MD0_REG, |
| 638 | .ns_mask = BM(29, 22) | BM(5, 3), |
| 639 | .rst_mask = BIT(31), |
| 640 | .mnd_en_mask = BIT(8), |
| 641 | .mode_mask = BM(10, 9), |
| 642 | }, |
| 643 | .bank1_mask = { |
| 644 | .md_reg = (void *)MDP_MD1_REG, |
| 645 | .ns_mask = BM(21, 14) | BM(2, 0), |
| 646 | .rst_mask = BIT(30), |
| 647 | .mnd_en_mask = BIT(5), |
| 648 | .mode_mask = BM(7, 6), |
| 649 | }, |
| 650 | }; |
| 651 | |
| 652 | static struct rcg_clk mdp_clk = { |
| 653 | .b = { |
| 654 | .ctl_reg = (void *)MDP_CC_REG, |
| 655 | .en_mask = BIT(0), |
| 656 | .reset_reg = (void *)SW_RESET_CORE_REG, |
| 657 | .reset_mask = BIT(21), |
| 658 | .halt_reg = (void *)DBG_BUS_VEC_C_REG, |
| 659 | .halt_bit = 10, |
| 660 | }, |
| 661 | .ns_reg = (void *)MDP_NS_REG, |
| 662 | .root_en_mask = BIT(2), |
| 663 | .set_rate = set_rate_mnd_banked, |
| 664 | .freq_tbl = clk_tbl_mdp, |
| 665 | .bank_masks = &bmnd_info_mdp, |
| 666 | .depends = &mdp_axi_clk.c, |
| 667 | .current_freq = &local_dummy_freq, |
| 668 | .c = { |
| 669 | .dbg_name = "mdp_clk", |
| 670 | .ops = &soc_clk_ops_8960, |
| 671 | }, |
| 672 | }; |
| 673 | |
| 674 | static struct branch_clk lut_mdp_clk = { |
| 675 | .b = { |
| 676 | .ctl_reg = (void *)MDP_LUT_CC_REG, |
| 677 | .en_mask = BIT(0), |
| 678 | .halt_reg = (void *)DBG_BUS_VEC_I_REG, |
| 679 | .halt_bit = 13, |
| 680 | }, |
| 681 | .parent = &mdp_clk.c, |
| 682 | .c = { |
| 683 | .dbg_name = "lut_mdp_clk", |
| 684 | .ops = &clk_ops_branch, |
| 685 | }, |
| 686 | }; |
| 687 | |
| 688 | #ifdef DEBUG_CLOCK |
| 689 | struct measure_sel { |
| 690 | uint32_t test_vector; |
| 691 | struct clk *clk; |
| 692 | }; |
| 693 | |
| 694 | static struct measure_sel measure_mux[] = { |
| 695 | { TEST_PER_LS(0x13), &sdc1_clk.c }, |
| 696 | { TEST_PER_LS(0x15), &sdc2_clk.c }, |
| 697 | { TEST_PER_LS(0x17), &sdc3_clk.c }, |
| 698 | { TEST_PER_LS(0x19), &sdc4_clk.c }, |
| 699 | { TEST_PER_LS(0x1B), &sdc5_clk.c }, |
| 700 | { TEST_PER_LS(0x3D), &gsbi1_p_clk.c }, |
| 701 | { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c }, |
| 702 | { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c }, |
| 703 | { TEST_PER_LS(0x41), &gsbi2_p_clk.c }, |
| 704 | { TEST_PER_LS(0x42), &gsbi2_uart_clk.c }, |
| 705 | { TEST_PER_LS(0x44), &gsbi2_qup_clk.c }, |
| 706 | { TEST_PER_LS(0x45), &gsbi3_p_clk.c }, |
| 707 | { TEST_PER_LS(0x46), &gsbi3_uart_clk.c }, |
| 708 | { TEST_PER_LS(0x48), &gsbi3_qup_clk.c }, |
| 709 | { TEST_PER_LS(0x49), &gsbi4_p_clk.c }, |
| 710 | { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c }, |
| 711 | { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c }, |
| 712 | { TEST_PER_LS(0x4D), &gsbi5_p_clk.c }, |
| 713 | { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c }, |
| 714 | { TEST_PER_LS(0x50), &gsbi5_qup_clk.c }, |
| 715 | { TEST_PER_LS(0x51), &gsbi6_p_clk.c }, |
| 716 | { TEST_PER_LS(0x52), &gsbi6_uart_clk.c }, |
| 717 | { TEST_PER_LS(0x54), &gsbi6_qup_clk.c }, |
| 718 | { TEST_PER_LS(0x55), &gsbi7_p_clk.c }, |
| 719 | { TEST_PER_LS(0x56), &gsbi7_uart_clk.c }, |
| 720 | { TEST_PER_LS(0x58), &gsbi7_qup_clk.c }, |
| 721 | { TEST_PER_LS(0x59), &gsbi8_p_clk.c }, |
| 722 | { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c }, |
| 723 | { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c }, |
| 724 | { TEST_PER_LS(0x5D), &gsbi9_p_clk.c }, |
| 725 | { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c }, |
| 726 | { TEST_PER_LS(0x60), &gsbi9_qup_clk.c }, |
| 727 | { TEST_PER_LS(0x61), &gsbi10_p_clk.c }, |
| 728 | { TEST_PER_LS(0x62), &gsbi10_uart_clk.c }, |
| 729 | { TEST_PER_LS(0x64), &gsbi10_qup_clk.c }, |
| 730 | { TEST_PER_LS(0x65), &gsbi11_p_clk.c }, |
| 731 | { TEST_PER_LS(0x66), &gsbi11_uart_clk.c }, |
| 732 | { TEST_PER_LS(0x68), &gsbi11_qup_clk.c }, |
| 733 | { TEST_PER_LS(0x69), &gsbi12_p_clk.c }, |
| 734 | { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c }, |
| 735 | { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c }, |
| 736 | { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c }, |
| 737 | { TEST_PER_LS(0x92), &ce1_p_clk.c }, |
| 738 | { TEST_PER_LS(0xA4), &ce1_core_clk.c }, |
| 739 | { TEST_PER_LS(0x5F), &ce3_p_clk.c }, |
| 740 | { TEST_PER_LS(0x60), &ce3_core_clk.c }, |
| 741 | |
| 742 | { TEST_MM_HS(0x15), &mdp_axi_clk.c }, |
| 743 | { TEST_MM_HS(0x1A), &mdp_clk.c }, |
| 744 | { TEST_MM_HS(0x28), &lut_mdp_clk.c }, |
| 745 | }; |
| 746 | |
| 747 | static struct measure_sel *find_measure_sel(struct clk *clk) |
| 748 | { |
| 749 | int i; |
| 750 | |
| 751 | for (i = 0; i < ARRAY_SIZE(measure_mux); i++) |
| 752 | if (measure_mux[i].clk == clk) |
| 753 | return &measure_mux[i]; |
| 754 | return NULL; |
| 755 | } |
| 756 | |
| 757 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
| 758 | { |
| 759 | int ret = 0; |
| 760 | uint32_t clk_sel; |
| 761 | struct measure_sel *p; |
| 762 | struct measure_clk *clk = to_measure_clk(c); |
| 763 | |
| 764 | if (!parent) |
| 765 | return ERR_INVALID_ARGS; |
| 766 | |
| 767 | p = find_measure_sel(parent); |
| 768 | if (!p) |
| 769 | return ERR_INVALID_ARGS; |
| 770 | |
| 771 | /* |
| 772 | * Program the test vector, measurement period (sample_ticks) |
| 773 | * and scaling multiplier. |
| 774 | */ |
| 775 | clk->sample_ticks = 0x10000; |
| 776 | clk_sel = p->test_vector & TEST_CLK_SEL_MASK; |
| 777 | clk->multiplier = 1; |
| 778 | switch (p->test_vector >> TEST_TYPE_SHIFT) { |
| 779 | case TEST_TYPE_PER_LS: |
| 780 | writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG); |
| 781 | break; |
| 782 | case TEST_TYPE_PER_HS: |
| 783 | writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG); |
| 784 | break; |
| 785 | case TEST_TYPE_MM_LS: |
| 786 | writel_relaxed(0x4030D97, CLK_TEST_REG); |
| 787 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG); |
| 788 | break; |
| 789 | case TEST_TYPE_MM_HS: |
| 790 | writel_relaxed(0x402B800, CLK_TEST_REG); |
| 791 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG); |
| 792 | break; |
| 793 | default: |
| 794 | ret = ERR_NOT_SUPPORTED; |
| 795 | } |
| 796 | /* Make sure test vector is set before starting measurements. */ |
| 797 | dmb(); |
| 798 | |
| 799 | return ret; |
| 800 | } |
| 801 | |
| 802 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 803 | static uint32_t run_measurement(unsigned ticks) |
| 804 | { |
| 805 | /* Stop counters and set the XO4 counter start value. */ |
| 806 | writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG); |
| 807 | |
| 808 | /* Wait for timer to become ready. */ |
| 809 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0) |
| 810 | dmb(); |
| 811 | |
| 812 | /* Run measurement and wait for completion. */ |
| 813 | writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG); |
| 814 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0) |
| 815 | dmb(); |
| 816 | |
| 817 | /* Stop counters. */ |
| 818 | writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG); |
| 819 | |
| 820 | /* Return measured ticks. */ |
| 821 | return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0); |
| 822 | } |
| 823 | |
| 824 | |
| 825 | /* Perform a hardware rate measurement for a given clock. |
| 826 | FOR DEBUG USE ONLY: Measurements take ~15 ms! */ |
| 827 | static unsigned long measure_clk_get_rate(struct clk *c) |
| 828 | { |
| 829 | uint32_t pdm_reg_backup, ringosc_reg_backup; |
| 830 | uint64_t raw_count_short, raw_count_full; |
| 831 | struct measure_clk *clk = to_measure_clk(c); |
| 832 | unsigned ret; |
| 833 | |
| 834 | ret = clk_enable(&cxo_clk.c); |
| 835 | if (ret) { |
| 836 | dprintf(CRITICAL, "CXO clock failed to enable. Can't measure\n"); |
| 837 | return 0; |
| 838 | } |
| 839 | |
| 840 | /* Enable CXO/4 and RINGOSC branch and root. */ |
| 841 | pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG); |
| 842 | ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG); |
| 843 | writel_relaxed(0x2898, PDM_CLK_NS_REG); |
| 844 | writel_relaxed(0xA00, RINGOSC_NS_REG); |
| 845 | |
| 846 | /* |
| 847 | * The ring oscillator counter will not reset if the measured clock |
| 848 | * is not running. To detect this, run a short measurement before |
| 849 | * the full measurement. If the raw results of the two are the same |
| 850 | * then the clock must be off. |
| 851 | */ |
| 852 | |
| 853 | /* Run a short measurement. (~1 ms) */ |
| 854 | raw_count_short = run_measurement(0x1000); |
| 855 | /* Run a full measurement. (~14 ms) */ |
| 856 | raw_count_full = run_measurement(clk->sample_ticks); |
| 857 | |
| 858 | writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG); |
| 859 | writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG); |
| 860 | |
| 861 | /* Return 0 if the clock is off. */ |
| 862 | if (raw_count_full == raw_count_short) |
| 863 | ret = 0; |
| 864 | else { |
| 865 | /* Compute rate in Hz. */ |
| 866 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
| 867 | raw_count_full /= ((clk->sample_ticks * 10) + 35); |
| 868 | ret = (raw_count_full * clk->multiplier); |
| 869 | } |
| 870 | |
| 871 | /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */ |
| 872 | writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG); |
| 873 | |
| 874 | clk_disable(&cxo_clk.c); |
| 875 | |
| 876 | return ret; |
| 877 | } |
| 878 | #else |
| 879 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 880 | { |
| 881 | return ERR_INVALID_ARGS; |
| 882 | } |
| 883 | |
| 884 | static unsigned long measure_clk_get_rate(struct clk *clk) |
| 885 | { |
| 886 | return 0; |
| 887 | } |
| 888 | #endif |
| 889 | |
| 890 | static struct clk_ops measure_clk_ops = { |
| 891 | .set_parent = measure_clk_set_parent, |
| 892 | .get_rate = measure_clk_get_rate, |
| 893 | }; |
| 894 | |
| 895 | static struct measure_clk measure_clk = { |
| 896 | .c = { |
| 897 | .dbg_name = "measure_clk", |
| 898 | .ops = &measure_clk_ops, |
| 899 | }, |
| 900 | .multiplier = 1, |
| 901 | }; |
| 902 | |
| 903 | static struct clk_lookup msm_clocks_8960[] = { |
| 904 | CLK_LOOKUP("gsbi1_uart_clk", gsbi1_uart_clk.c), |
| 905 | CLK_LOOKUP("gsbi2_uart_clk", gsbi2_uart_clk.c), |
| 906 | CLK_LOOKUP("gsbi3_uart_clk", gsbi3_uart_clk.c), |
| 907 | CLK_LOOKUP("gsbi4_uart_clk", gsbi4_uart_clk.c), |
| 908 | CLK_LOOKUP("gsbi5_uart_clk", gsbi5_uart_clk.c), |
| 909 | CLK_LOOKUP("gsbi6_uart_clk", gsbi6_uart_clk.c), |
| 910 | CLK_LOOKUP("gsbi7_uart_clk", gsbi7_uart_clk.c), |
| 911 | CLK_LOOKUP("gsbi8_uart_clk", gsbi8_uart_clk.c), |
| 912 | CLK_LOOKUP("gsbi9_uart_clk", gsbi9_uart_clk.c), |
| 913 | CLK_LOOKUP("gsbi10_uart_clk", gsbi10_uart_clk.c), |
| 914 | CLK_LOOKUP("gsbi11_uart_clk", gsbi11_uart_clk.c), |
| 915 | CLK_LOOKUP("gsbi12_uart_clk", gsbi12_uart_clk.c), |
| 916 | CLK_LOOKUP("gsbi1_qup_clk", gsbi1_qup_clk.c), |
| 917 | CLK_LOOKUP("gsbi2_qup_clk", gsbi2_qup_clk.c), |
| 918 | CLK_LOOKUP("gsbi3_qup_clk", gsbi3_qup_clk.c), |
| 919 | CLK_LOOKUP("gsbi4_qup_clk", gsbi4_qup_clk.c), |
| 920 | CLK_LOOKUP("gsbi5_qup_clk", gsbi5_qup_clk.c), |
| 921 | CLK_LOOKUP("gsbi6_qup_clk", gsbi6_qup_clk.c), |
| 922 | CLK_LOOKUP("gsbi7_qup_clk", gsbi7_qup_clk.c), |
| 923 | CLK_LOOKUP("gsbi8_qup_clk", gsbi8_qup_clk.c), |
| 924 | CLK_LOOKUP("gsbi9_qup_clk", gsbi9_qup_clk.c), |
| 925 | CLK_LOOKUP("gsbi10_qup_clk", gsbi10_qup_clk.c), |
| 926 | CLK_LOOKUP("gsbi11_qup_clk", gsbi11_qup_clk.c), |
| 927 | CLK_LOOKUP("gsbi12_qup_clk", gsbi12_qup_clk.c), |
| 928 | CLK_LOOKUP("gsbi1_pclk", gsbi1_p_clk.c), |
| 929 | CLK_LOOKUP("gsbi2_pclk", gsbi2_p_clk.c), |
| 930 | CLK_LOOKUP("gsbi3_pclk", gsbi3_p_clk.c), |
| 931 | CLK_LOOKUP("gsbi4_pclk", gsbi4_p_clk.c), |
| 932 | CLK_LOOKUP("gsbi5_pclk", gsbi5_p_clk.c), |
| 933 | CLK_LOOKUP("gsbi6_pclk", gsbi6_p_clk.c), |
| 934 | CLK_LOOKUP("gsbi7_pclk", gsbi7_p_clk.c), |
| 935 | CLK_LOOKUP("gsbi8_pclk", gsbi8_p_clk.c), |
| 936 | CLK_LOOKUP("gsbi9_pclk", gsbi9_p_clk.c), |
| 937 | CLK_LOOKUP("gsbi10_pclk", gsbi10_p_clk.c), |
| 938 | CLK_LOOKUP("gsbi11_pclk", gsbi11_p_clk.c), |
| 939 | CLK_LOOKUP("gsbi12_pclk", gsbi12_p_clk.c), |
| 940 | CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c), |
| 941 | CLK_LOOKUP("sdc1_clk", sdc1_clk.c), |
| 942 | CLK_LOOKUP("sdc2_clk", sdc2_clk.c), |
| 943 | CLK_LOOKUP("sdc3_clk", sdc3_clk.c), |
| 944 | CLK_LOOKUP("sdc4_clk", sdc4_clk.c), |
| 945 | CLK_LOOKUP("sdc5_clk", sdc5_clk.c), |
| 946 | CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c), |
| 947 | CLK_LOOKUP("mdp_clk", mdp_clk.c), |
| 948 | CLK_LOOKUP("lut_mdp", lut_mdp_clk.c), |
| 949 | CLK_LOOKUP("ce1_pclk", ce1_p_clk.c), |
| 950 | CLK_LOOKUP("ce1_clk", ce1_core_clk.c), |
| 951 | CLK_LOOKUP("ce3_src_clk", ce3_src_clk.c), |
| 952 | CLK_LOOKUP("ce3_pclk", ce3_p_clk.c), |
| 953 | CLK_LOOKUP("ce3_clk", ce3_core_clk.c), |
| 954 | CLK_LOOKUP("measure", measure_clk.c), |
| 955 | |
| 956 | }; |
| 957 | |
| 958 | static int sr_pll_clk_enable(struct clk *clk) |
| 959 | { |
| 960 | uint32_t mode; |
| 961 | struct pll_clk *pll = to_pll_clk(clk); |
| 962 | |
| 963 | mode = readl_relaxed(pll->mode_reg); |
| 964 | /* De-assert active-low PLL reset. */ |
| 965 | mode |= BIT(2); |
| 966 | writel_relaxed(mode, pll->mode_reg); |
| 967 | |
| 968 | /* |
| 969 | * H/W requires a 5us delay between disabling the bypass and |
| 970 | * de-asserting the reset. Delay 10us just to be safe. |
| 971 | */ |
| 972 | dmb(); |
| 973 | udelay(10); |
| 974 | |
| 975 | /* Disable PLL bypass mode. */ |
| 976 | mode |= BIT(1); |
| 977 | writel_relaxed(mode, pll->mode_reg); |
| 978 | |
| 979 | /* Wait until PLL is locked. */ |
| 980 | dmb(); |
| 981 | udelay(60); |
| 982 | |
| 983 | /* Enable PLL output. */ |
| 984 | mode |= BIT(0); |
| 985 | writel_relaxed(mode, pll->mode_reg); |
| 986 | |
| 987 | return 0; |
| 988 | } |
| 989 | |
| 990 | static unsigned msm_num_clocks_8960 = ARRAY_SIZE(msm_clocks_8960); |
| 991 | |
| 992 | void msm_clocks_init() |
| 993 | { |
| 994 | clk_ops_pll.enable = sr_pll_clk_enable; |
| 995 | clk_init(msm_clocks_8960, msm_num_clocks_8960); |
| 996 | } |
| 997 | |