Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | #ifndef _USB30_DWC_HWIO_H_ |
| 29 | #define _USB30_DWC_HWIO_H_ |
| 30 | |
| 31 | /* Macros to simplify dwc reg read */ |
| 32 | #define REG_READ(_dev, _reg) readl(DWC_##_reg##_ADDR(_dev->base)) |
| 33 | #define REG_READI(_dev, _reg, _index) readl(DWC_##_reg##_ADDR(_dev->base, _index)) |
| 34 | |
| 35 | /* Macros to simplify dwc reg write */ |
| 36 | #define REG_WRITE(_dev, _reg, _value) writel(_value, DWC_##_reg##_ADDR(_dev->base)) |
| 37 | #define REG_WRITEI(_dev, _reg, _index, _value) writel(_value, DWC_##_reg##_ADDR(_dev->base, _index)) |
| 38 | |
| 39 | #define REG_BMSK(_reg, _field) DWC_##_reg##_##_field##_BMSK |
| 40 | #define REG_SHFT(_reg, _field) DWC_##_reg##_##_field##_SHFT |
| 41 | |
| 42 | /* read specified field in the register */ |
| 43 | #define REG_READ_FIELD(_dev, _reg, _field) ((REG_READ(_dev,_reg) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field)) |
| 44 | #define REG_READ_FIELDI(_dev, _reg, _index, _field) ((REG_READI(_dev,_reg, _index) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field)) |
| 45 | #define REG_READ_FIELD_LOCAL(_addr, _reg, _field) (((*_addr) & REG_BMSK(_reg, _field)) >> REG_SHFT(_reg, _field)) |
| 46 | |
| 47 | |
| 48 | /* write specified field in the register: implements a read/modify/write */ |
| 49 | #define REG_WRITE_FIELD(_dev, _reg, _field, _value) \ |
| 50 | REG_WRITE(_dev, _reg, ((REG_READ(_dev, _reg) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field)))) |
| 51 | |
| 52 | #define REG_WRITE_FIELDI(_dev, _reg, _index, _field, _value) \ |
| 53 | REG_WRITEI(_dev, _reg, _index, ((REG_READI(_dev, _reg, _index) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field)))) |
| 54 | |
| 55 | #define REG_WRITE_FIELD_LOCAL(_addr, _reg, _field, _value) \ |
| 56 | (*(_addr) = ((*(_addr) & ~REG_BMSK(_reg, _field)) | (_value << REG_SHFT(_reg, _field)))) |
| 57 | |
| 58 | |
| 59 | |
| 60 | /* The following defines are auto generated. */ |
| 61 | |
| 62 | /** |
| 63 | @file usb30_dwc_hwio.h |
| 64 | @brief Auto-generated HWIO interface include file. |
| 65 | |
| 66 | This file contains HWIO register definitions for the following modules: |
| 67 | DWC_USB3 |
| 68 | |
| 69 | 'Include' filters applied: |
| 70 | 'Exclude' filters applied: RESERVED DUMMY |
| 71 | */ |
| 72 | /*---------------------------------------------------------------------------- |
| 73 | * MODULE: DWC_USB3 |
| 74 | *--------------------------------------------------------------------------*/ |
| 75 | #define DWC_USB3_REG_BASE_OFFS 0x00000000 |
| 76 | #define DWC_GUSB2PHYCFG_ADDR(base,p) ((base) + 0x0000c200 + 0x4 * (p)) |
| 77 | #define DWC_GUSB2PHYCFG_OFFS(p) (0x0000c200 + 0x4 * (p)) |
| 78 | #define DWC_GUSB2PHYCFG_RMSK 0xffffffff |
| 79 | #define DWC_GUSB2PHYCFG_MAXp 0 |
| 80 | #define DWC_GUSB2PHYCFG_POR 0x00002500 |
| 81 | #define DWC_GUSB2PHYCFG_PHYSOFTRST_BMSK 0x80000000 |
| 82 | #define DWC_GUSB2PHYCFG_PHYSOFTRST_SHFT 0x1f |
| 83 | #define DWC_GUSB2PHYCFG_RSVD_BMSK 0x7ff80000 |
| 84 | #define DWC_GUSB2PHYCFG_RSVD_SHFT 0x13 |
| 85 | #define DWC_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_BMSK 0x40000 |
| 86 | #define DWC_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHFT 0x12 |
| 87 | #define DWC_GUSB2PHYCFG_ULPIEXTVBUSDRV_BMSK 0x20000 |
| 88 | #define DWC_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHFT 0x11 |
| 89 | #define DWC_GUSB2PHYCFG_ULPICLKSUSM_BMSK 0x10000 |
| 90 | #define DWC_GUSB2PHYCFG_ULPICLKSUSM_SHFT 0x10 |
| 91 | #define DWC_GUSB2PHYCFG_ULPIAUTORES_BMSK 0x8000 |
| 92 | #define DWC_GUSB2PHYCFG_ULPIAUTORES_SHFT 0xf |
| 93 | #define DWC_GUSB2PHYCFG_RSVD9_BMSK 0x4000 |
| 94 | #define DWC_GUSB2PHYCFG_RSVD9_SHFT 0xe |
| 95 | #define DWC_GUSB2PHYCFG_USBTRDTIM_BMSK 0x3c00 |
| 96 | #define DWC_GUSB2PHYCFG_USBTRDTIM_SHFT 0xa |
| 97 | #define DWC_GUSB2PHYCFG_RSVD0_BMSK 0x200 |
| 98 | #define DWC_GUSB2PHYCFG_RSVD0_SHFT 0x9 |
| 99 | #define DWC_GUSB2PHYCFG_ENBLSLPM_BMSK 0x100 |
| 100 | #define DWC_GUSB2PHYCFG_ENBLSLPM_SHFT 0x8 |
| 101 | #define DWC_GUSB2PHYCFG_PHYSEL_BMSK 0x80 |
| 102 | #define DWC_GUSB2PHYCFG_PHYSEL_SHFT 0x7 |
| 103 | #define DWC_GUSB2PHYCFG_SUSPENDUSB20_BMSK 0x40 |
| 104 | #define DWC_GUSB2PHYCFG_SUSPENDUSB20_SHFT 0x6 |
| 105 | #define DWC_GUSB2PHYCFG_FSINTF_BMSK 0x20 |
| 106 | #define DWC_GUSB2PHYCFG_FSINTF_SHFT 0x5 |
| 107 | #define DWC_GUSB2PHYCFG_ULPI_UTMI_SEL_BMSK 0x10 |
| 108 | #define DWC_GUSB2PHYCFG_ULPI_UTMI_SEL_SHFT 0x4 |
| 109 | #define DWC_GUSB2PHYCFG_PHYIF_BMSK 0x8 |
| 110 | #define DWC_GUSB2PHYCFG_PHYIF_SHFT 0x3 |
| 111 | #define DWC_GUSB2PHYCFG_B1L_BMSK 0x7 |
| 112 | #define DWC_GUSB2PHYCFG_B1L_SHFT 0x0 |
| 113 | |
| 114 | #define DWC_GUSB2I2CCTL_ADDR(base,p) ((base) + 0x0000c240 + 0x4 * (p)) |
| 115 | #define DWC_GUSB2I2CCTL_OFFS(p) (0x0000c240 + 0x4 * (p)) |
| 116 | #define DWC_GUSB2I2CCTL_RMSK 0xffffffff |
| 117 | #define DWC_GUSB2I2CCTL_MAXp 0 |
| 118 | #define DWC_GUSB2I2CCTL_POR 0x00000000 |
| 119 | #define DWC_GUSB2I2CCTL_RSVD_BMSK 0x80000000 |
| 120 | #define DWC_GUSB2I2CCTL_RSVD_SHFT 0x1f |
| 121 | #define DWC_GUSB2I2CCTL_BSYDNE_BMSK 0x40000000 |
| 122 | #define DWC_GUSB2I2CCTL_BSYDNE_SHFT 0x1e |
| 123 | #define DWC_GUSB2I2CCTL_ACK_BMSK 0x20000000 |
| 124 | #define DWC_GUSB2I2CCTL_ACK_SHFT 0x1d |
| 125 | #define DWC_GUSB2I2CCTL_RW_BMSK 0x10000000 |
| 126 | #define DWC_GUSB2I2CCTL_RW_SHFT 0x1c |
| 127 | #define DWC_GUSB2I2CCTL_I2CDATSE0_BMSK 0x8000000 |
| 128 | #define DWC_GUSB2I2CCTL_I2CDATSE0_SHFT 0x1b |
| 129 | #define DWC_GUSB2I2CCTL_I2CDEVADR_BMSK 0x6000000 |
| 130 | #define DWC_GUSB2I2CCTL_I2CDEVADR_SHFT 0x19 |
| 131 | #define DWC_GUSB2I2CCTL_I2CSUSPCTL_BMSK 0x1000000 |
| 132 | #define DWC_GUSB2I2CCTL_I2CSUSPCTL_SHFT 0x18 |
| 133 | #define DWC_GUSB2I2CCTL_I2CEN_BMSK 0x800000 |
| 134 | #define DWC_GUSB2I2CCTL_I2CEN_SHFT 0x17 |
| 135 | #define DWC_GUSB2I2CCTL_ADDR_BMSK 0x7f0000 |
| 136 | #define DWC_GUSB2I2CCTL_ADDR_SHFT 0x10 |
| 137 | #define DWC_GUSB2I2CCTL_REGADDR_BMSK 0xff00 |
| 138 | #define DWC_GUSB2I2CCTL_REGADDR_SHFT 0x8 |
| 139 | #define DWC_GUSB2I2CCTL_RWDATA_BMSK 0xff |
| 140 | #define DWC_GUSB2I2CCTL_RWDATA_SHFT 0x0 |
| 141 | |
| 142 | #define DWC_GUSB2PHYACC_ULPI_ADDR(base,p) ((base) + 0x0000c280 + 0x4 * (p)) |
| 143 | #define DWC_GUSB2PHYACC_ULPI_OFFS(p) (0x0000c280 + 0x4 * (p)) |
| 144 | #define DWC_GUSB2PHYACC_ULPI_RMSK 0xffff1fff |
| 145 | #define DWC_GUSB2PHYACC_ULPI_MAXp 0 |
| 146 | #define DWC_GUSB2PHYACC_ULPI_POR 0x00000000 |
| 147 | #define DWC_GUSB2PHYACC_ULPI_RSVD42_BMSK 0xf8000000 |
| 148 | #define DWC_GUSB2PHYACC_ULPI_RSVD42_SHFT 0x1b |
| 149 | #define DWC_GUSB2PHYACC_ULPI_DISUIPIDRVR_BMSK 0x4000000 |
| 150 | #define DWC_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHFT 0x1a |
| 151 | #define DWC_GUSB2PHYACC_ULPI_NEWREGREQ_BMSK 0x2000000 |
| 152 | #define DWC_GUSB2PHYACC_ULPI_NEWREGREQ_SHFT 0x19 |
| 153 | #define DWC_GUSB2PHYACC_ULPI_VSTSDONE_BMSK 0x1000000 |
| 154 | #define DWC_GUSB2PHYACC_ULPI_VSTSDONE_SHFT 0x18 |
| 155 | #define DWC_GUSB2PHYACC_ULPI_VSTSBSY_BMSK 0x800000 |
| 156 | #define DWC_GUSB2PHYACC_ULPI_VSTSBSY_SHFT 0x17 |
| 157 | #define DWC_GUSB2PHYACC_ULPI_REGWR_BMSK 0x400000 |
| 158 | #define DWC_GUSB2PHYACC_ULPI_REGWR_SHFT 0x16 |
| 159 | #define DWC_GUSB2PHYACC_ULPI_REGADDR_BMSK 0x3f0000 |
| 160 | #define DWC_GUSB2PHYACC_ULPI_REGADDR_SHFT 0x10 |
| 161 | #define DWC_GUSB2PHYACC_ULPI_EXTREGADDR_BMSK 0x1f00 |
| 162 | #define DWC_GUSB2PHYACC_ULPI_EXTREGADDR_SHFT 0x8 |
| 163 | #define DWC_GUSB2PHYACC_ULPI_REGDATA_BMSK 0xff |
| 164 | #define DWC_GUSB2PHYACC_ULPI_REGDATA_SHFT 0x0 |
| 165 | |
| 166 | #define DWC_GUSB3PIPECTL_ADDR(base,p) ((base) + 0x0000c2c0 + 0x4 * (p)) |
| 167 | #define DWC_GUSB3PIPECTL_OFFS(p) (0x0000c2c0 + 0x4 * (p)) |
| 168 | #define DWC_GUSB3PIPECTL_RMSK 0xffffffff |
| 169 | #define DWC_GUSB3PIPECTL_MAXp 0 |
| 170 | #define DWC_GUSB3PIPECTL_POR 0x034c0003 |
| 171 | #define DWC_GUSB3PIPECTL_PHYSOFTRST_BMSK 0x80000000 |
| 172 | #define DWC_GUSB3PIPECTL_PHYSOFTRST_SHFT 0x1f |
| 173 | #define DWC_GUSB3PIPECTL_RSVD8_BMSK 0x40000000 |
| 174 | #define DWC_GUSB3PIPECTL_RSVD8_SHFT 0x1e |
| 175 | #define DWC_GUSB3PIPECTL_U2SSINACTP3OK_BMSK 0x20000000 |
| 176 | #define DWC_GUSB3PIPECTL_U2SSINACTP3OK_SHFT 0x1d |
| 177 | #define DWC_GUSB3PIPECTL_DISRXDETP3_BMSK 0x10000000 |
| 178 | #define DWC_GUSB3PIPECTL_DISRXDETP3_SHFT 0x1c |
| 179 | #define DWC_GUSB3PIPECTL_UX_EXIT_IN_PX_BMSK 0x8000000 |
| 180 | #define DWC_GUSB3PIPECTL_UX_EXIT_IN_PX_SHFT 0x1b |
| 181 | #define DWC_GUSB3PIPECTL_PING_ENHANCEMENT_EN_BMSK 0x4000000 |
| 182 | #define DWC_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHFT 0x1a |
| 183 | #define DWC_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_BMSK 0x2000000 |
| 184 | #define DWC_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHFT 0x19 |
| 185 | #define DWC_GUSB3PIPECTL_REQUEST_P1P2P3_BMSK 0x1000000 |
| 186 | #define DWC_GUSB3PIPECTL_REQUEST_P1P2P3_SHFT 0x18 |
| 187 | #define DWC_GUSB3PIPECTL_STARTRXDETU3RXDET_BMSK 0x800000 |
| 188 | #define DWC_GUSB3PIPECTL_STARTRXDETU3RXDET_SHFT 0x17 |
| 189 | #define DWC_GUSB3PIPECTL_DISRXDETU3RXDET_BMSK 0x400000 |
| 190 | #define DWC_GUSB3PIPECTL_DISRXDETU3RXDET_SHFT 0x16 |
| 191 | #define DWC_GUSB3PIPECTL_GUSBPIPECTL_BUS_BMSK 0x200000 |
| 192 | #define DWC_GUSB3PIPECTL_GUSBPIPECTL_BUS_SHFT 0x15 |
| 193 | #define DWC_GUSB3PIPECTL_DELAYP1P2P3_BMSK 0x180000 |
| 194 | #define DWC_GUSB3PIPECTL_DELAYP1P2P3_SHFT 0x13 |
| 195 | #define DWC_GUSB3PIPECTL_DELAYP1TRANS_BMSK 0x40000 |
| 196 | #define DWC_GUSB3PIPECTL_DELAYP1TRANS_SHFT 0x12 |
| 197 | #define DWC_GUSB3PIPECTL_SUSPENDENABLE_BMSK 0x20000 |
| 198 | #define DWC_GUSB3PIPECTL_SUSPENDENABLE_SHFT 0x11 |
| 199 | #define DWC_GUSB3PIPECTL_DATWIDTH_BMSK 0x18000 |
| 200 | #define DWC_GUSB3PIPECTL_DATWIDTH_SHFT 0xf |
| 201 | #define DWC_GUSB3PIPECTL_ABORTRXDETINU2_BMSK 0x4000 |
| 202 | #define DWC_GUSB3PIPECTL_ABORTRXDETINU2_SHFT 0xe |
| 203 | #define DWC_GUSB3PIPECTL_SKIPRXDET_BMSK 0x2000 |
| 204 | #define DWC_GUSB3PIPECTL_SKIPRXDET_SHFT 0xd |
| 205 | #define DWC_GUSB3PIPECTL_LFPSP0ALGN_BMSK 0x1000 |
| 206 | #define DWC_GUSB3PIPECTL_LFPSP0ALGN_SHFT 0xc |
| 207 | #define DWC_GUSB3PIPECTL_P3P2TRANOK_BMSK 0x800 |
| 208 | #define DWC_GUSB3PIPECTL_P3P2TRANOK_SHFT 0xb |
| 209 | #define DWC_GUSB3PIPECTL_P3EXSIGP2_BMSK 0x400 |
| 210 | #define DWC_GUSB3PIPECTL_P3EXSIGP2_SHFT 0xa |
| 211 | #define DWC_GUSB3PIPECTL_LFPSFILTER_BMSK 0x200 |
| 212 | #define DWC_GUSB3PIPECTL_LFPSFILTER_SHFT 0x9 |
| 213 | #define DWC_GUSB3PIPECTL_PRTOPDIR_BMSK 0x180 |
| 214 | #define DWC_GUSB3PIPECTL_PRTOPDIR_SHFT 0x7 |
| 215 | #define DWC_GUSB3PIPECTL_TX_SWING_BMSK 0x40 |
| 216 | #define DWC_GUSB3PIPECTL_TX_SWING_SHFT 0x6 |
| 217 | #define DWC_GUSB3PIPECTL_TX_MARGIN_BMSK 0x38 |
| 218 | #define DWC_GUSB3PIPECTL_TX_MARGIN_SHFT 0x3 |
| 219 | #define DWC_GUSB3PIPECTL_TX_DE_EPPHASIS_BMSK 0x6 |
| 220 | #define DWC_GUSB3PIPECTL_TX_DE_EPPHASIS_SHFT 0x1 |
| 221 | #define DWC_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_BMSK 0x1 |
| 222 | #define DWC_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHFT 0x0 |
| 223 | |
| 224 | #define DWC_GTXFIFOSIZ_ADDR(base,p) ((base) + 0x0000c300 + 0x4 * (p)) |
| 225 | #define DWC_GTXFIFOSIZ_OFFS(p) (0x0000c300 + 0x4 * (p)) |
| 226 | #define DWC_GTXFIFOSIZ_RMSK 0xffffffff |
| 227 | #define DWC_GTXFIFOSIZ_MAXp 15 |
| 228 | #define DWC_GTXFIFOSIZ_POR 0x00000000 |
| 229 | #define DWC_GTXFIFOSIZ_TXFSTADDR_N_BMSK 0xffff0000 |
| 230 | #define DWC_GTXFIFOSIZ_TXFSTADDR_N_SHFT 0x10 |
| 231 | #define DWC_GTXFIFOSIZ_TXFDEP_N_BMSK 0xffff |
| 232 | #define DWC_GTXFIFOSIZ_TXFDEP_N_SHFT 0x0 |
| 233 | |
| 234 | #define DWC_GRXFIFOSIZ_ADDR(base,p) ((base) + 0x0000c380 + 0x4 * (p)) |
| 235 | #define DWC_GRXFIFOSIZ_OFFS(p) (0x0000c380 + 0x4 * (p)) |
| 236 | #define DWC_GRXFIFOSIZ_RMSK 0xffffffff |
| 237 | #define DWC_GRXFIFOSIZ_MAXp 2 |
| 238 | #define DWC_GRXFIFOSIZ_POR 0x00000000 |
| 239 | #define DWC_GRXFIFOSIZ_RXFSTADDR_N_BMSK 0xffff0000 |
| 240 | #define DWC_GRXFIFOSIZ_RXFSTADDR_N_SHFT 0x10 |
| 241 | #define DWC_GRXFIFOSIZ_RXFDEP_N_BMSK 0xffff |
| 242 | #define DWC_GRXFIFOSIZ_RXFDEP_N_SHFT 0x0 |
| 243 | |
| 244 | #define DWC_GEVNTADRLO_ADDR(base,p) ((base) + 0x0000c400 + 0x10 * (p)) |
| 245 | #define DWC_GEVNTADRLO_OFFS(p) (0x0000c400 + 0x10 * (p)) |
| 246 | #define DWC_GEVNTADRLO_RMSK 0xffffffff |
| 247 | #define DWC_GEVNTADRLO_MAXp 1 |
| 248 | #define DWC_GEVNTADRLO_POR 0x00000000 |
| 249 | #define DWC_GEVNTADRLO_EVNTADRLO_BMSK 0xffffffff |
| 250 | #define DWC_GEVNTADRLO_EVNTADRLO_SHFT 0x0 |
| 251 | |
| 252 | #define DWC_GEVNTADRHI_ADDR(base,p) ((base) + 0x0000c404 + 0x10 * (p)) |
| 253 | #define DWC_GEVNTADRHI_OFFS(p) (0x0000c404 + 0x10 * (p)) |
| 254 | #define DWC_GEVNTADRHI_RMSK 0xffffffff |
| 255 | #define DWC_GEVNTADRHI_MAXp 1 |
| 256 | #define DWC_GEVNTADRHI_POR 0x00000000 |
| 257 | #define DWC_GEVNTADRHI_EVNTADRHI_BMSK 0xffffffff |
| 258 | #define DWC_GEVNTADRHI_EVNTADRHI_SHFT 0x0 |
| 259 | |
| 260 | #define DWC_GEVNTSIZ_ADDR(base,p) ((base) + 0x0000c408 + 0x10 * (p)) |
| 261 | #define DWC_GEVNTSIZ_OFFS(p) (0x0000c408 + 0x10 * (p)) |
| 262 | #define DWC_GEVNTSIZ_RMSK 0xffffffff |
| 263 | #define DWC_GEVNTSIZ_MAXp 1 |
| 264 | #define DWC_GEVNTSIZ_POR 0x00000000 |
| 265 | #define DWC_GEVNTSIZ_EVNTINTRPTMASK_BMSK 0x80000000 |
| 266 | #define DWC_GEVNTSIZ_EVNTINTRPTMASK_SHFT 0x1f |
| 267 | #define DWC_GEVNTSIZ_RSVD74_BMSK 0x7fff0000 |
| 268 | #define DWC_GEVNTSIZ_RSVD74_SHFT 0x10 |
| 269 | #define DWC_GEVNTSIZ_EVENTSIZ_BMSK 0xffff |
| 270 | #define DWC_GEVNTSIZ_EVENTSIZ_SHFT 0x0 |
| 271 | |
| 272 | #define DWC_GEVNTCOUNT_ADDR(base,p) ((base) + 0x0000c40c + 0x10 * (p)) |
| 273 | #define DWC_GEVNTCOUNT_OFFS(p) (0x0000c40c + 0x10 * (p)) |
| 274 | #define DWC_GEVNTCOUNT_RMSK 0xffffffff |
| 275 | #define DWC_GEVNTCOUNT_MAXp 1 |
| 276 | #define DWC_GEVNTCOUNT_POR 0x00000000 |
| 277 | #define DWC_GEVNTCOUNT_RSVD75_BMSK 0xffff0000 |
| 278 | #define DWC_GEVNTCOUNT_RSVD75_SHFT 0x10 |
| 279 | #define DWC_GEVNTCOUNT_EVNTCOUNT_BMSK 0xffff |
| 280 | #define DWC_GEVNTCOUNT_EVNTCOUNT_SHFT 0x0 |
| 281 | |
| 282 | #define DWC_GSBUSCFG0_ADDR(x) ((x) + 0x0000c100) |
| 283 | #define DWC_GSBUSCFG0_OFFS (0x0000c100) |
| 284 | #define DWC_GSBUSCFG0_RMSK 0xffffffff |
| 285 | #define DWC_GSBUSCFG0_POR 0x0000000e |
| 286 | #define DWC_GSBUSCFG0_RSVD10_BMSK 0xffffff00 |
| 287 | #define DWC_GSBUSCFG0_RSVD10_SHFT 0x8 |
| 288 | #define DWC_GSBUSCFG0_INCR256BRSTENA_BMSK 0x80 |
| 289 | #define DWC_GSBUSCFG0_INCR256BRSTENA_SHFT 0x7 |
| 290 | #define DWC_GSBUSCFG0_INCR128BRSTENA_BMSK 0x40 |
| 291 | #define DWC_GSBUSCFG0_INCR128BRSTENA_SHFT 0x6 |
| 292 | #define DWC_GSBUSCFG0_INCR64BRSTENA_BMSK 0x20 |
| 293 | #define DWC_GSBUSCFG0_INCR64BRSTENA_SHFT 0x5 |
| 294 | #define DWC_GSBUSCFG0_INCR32BRSTENA_BMSK 0x10 |
| 295 | #define DWC_GSBUSCFG0_INCR32BRSTENA_SHFT 0x4 |
| 296 | #define DWC_GSBUSCFG0_INCR16BRSTENA_BMSK 0x8 |
| 297 | #define DWC_GSBUSCFG0_INCR16BRSTENA_SHFT 0x3 |
| 298 | #define DWC_GSBUSCFG0_INCR8BRSTENA_BMSK 0x4 |
| 299 | #define DWC_GSBUSCFG0_INCR8BRSTENA_SHFT 0x2 |
| 300 | #define DWC_GSBUSCFG0_INCR4BRSTENA_BMSK 0x2 |
| 301 | #define DWC_GSBUSCFG0_INCR4BRSTENA_SHFT 0x1 |
| 302 | #define DWC_GSBUSCFG0_INCRBRSTENA_BMSK 0x1 |
| 303 | #define DWC_GSBUSCFG0_INCRBRSTENA_SHFT 0x0 |
| 304 | |
| 305 | #define DWC_GSBUSCFG1_ADDR(x) ((x) + 0x0000c104) |
| 306 | #define DWC_GSBUSCFG1_OFFS (0x0000c104) |
| 307 | #define DWC_GSBUSCFG1_RMSK 0xffffffff |
| 308 | #define DWC_GSBUSCFG1_POR 0x00001700 |
| 309 | #define DWC_GSBUSCFG1_RSVD0_BMSK 0xffffe000 |
| 310 | #define DWC_GSBUSCFG1_RSVD0_SHFT 0xd |
| 311 | #define DWC_GSBUSCFG1_EN1KPAGE_BMSK 0x1000 |
| 312 | #define DWC_GSBUSCFG1_EN1KPAGE_SHFT 0xc |
| 313 | #define DWC_GSBUSCFG1_PIPETRANSLIMIT_BMSK 0xf00 |
| 314 | #define DWC_GSBUSCFG1_PIPETRANSLIMIT_SHFT 0x8 |
| 315 | #define DWC_GSBUSCFG1_RSVD1_BMSK 0xff |
| 316 | #define DWC_GSBUSCFG1_RSVD1_SHFT 0x0 |
| 317 | |
| 318 | #define DWC_GTXTHRCFG_ADDR(x) ((x) + 0x0000c108) |
| 319 | #define DWC_GTXTHRCFG_OFFS (0x0000c108) |
| 320 | #define DWC_GTXTHRCFG_RMSK 0xffffffff |
| 321 | #define DWC_GTXTHRCFG_POR 0x00000000 |
| 322 | #define DWC_GTXTHRCFG_USBISOTHREN_BMSK 0x80000000 |
| 323 | #define DWC_GTXTHRCFG_USBISOTHREN_SHFT 0x1f |
| 324 | #define DWC_GTXTHRCFG_USBNONISOTHREN_BMSK 0x40000000 |
| 325 | #define DWC_GTXTHRCFG_USBNONISOTHREN_SHFT 0x1e |
| 326 | #define DWC_GTXTHRCFG_USBTXPKTCNTSEL_BMSK 0x20000000 |
| 327 | #define DWC_GTXTHRCFG_USBTXPKTCNTSEL_SHFT 0x1d |
| 328 | #define DWC_GTXTHRCFG_RSVD3_BMSK 0x10000000 |
| 329 | #define DWC_GTXTHRCFG_RSVD3_SHFT 0x1c |
| 330 | #define DWC_GTXTHRCFG_USBTXPKTCNT_BMSK 0xf000000 |
| 331 | #define DWC_GTXTHRCFG_USBTXPKTCNT_SHFT 0x18 |
| 332 | #define DWC_GTXTHRCFG_USBMAXTXBURSTSIZE_BMSK 0xff0000 |
| 333 | #define DWC_GTXTHRCFG_USBMAXTXBURSTSIZE_SHFT 0x10 |
| 334 | #define DWC_GTXTHRCFG_SBUSISOTHREN_BMSK 0x8000 |
| 335 | #define DWC_GTXTHRCFG_SBUSISOTHREN_SHFT 0xf |
| 336 | #define DWC_GTXTHRCFG_SBUSNONISOTHREN_BMSK 0x4000 |
| 337 | #define DWC_GTXTHRCFG_SBUSNONISOTHREN_SHFT 0xe |
| 338 | #define DWC_GTXTHRCFG_RSVD2_BMSK 0x3800 |
| 339 | #define DWC_GTXTHRCFG_RSVD2_SHFT 0xb |
| 340 | #define DWC_GTXTHRCFG_RSVD1_BMSK 0x7ff |
| 341 | #define DWC_GTXTHRCFG_RSVD1_SHFT 0x0 |
| 342 | |
| 343 | #define DWC_GRXTHRCFG_ADDR(x) ((x) + 0x0000c10c) |
| 344 | #define DWC_GRXTHRCFG_OFFS (0x0000c10c) |
| 345 | #define DWC_GRXTHRCFG_RMSK 0xffffffff |
| 346 | #define DWC_GRXTHRCFG_POR 0x00000000 |
| 347 | #define DWC_GRXTHRCFG_RSVD5_BMSK 0xc0000000 |
| 348 | #define DWC_GRXTHRCFG_RSVD5_SHFT 0x1e |
| 349 | #define DWC_GRXTHRCFG_USBRXPKTCNTSEL_BMSK 0x20000000 |
| 350 | #define DWC_GRXTHRCFG_USBRXPKTCNTSEL_SHFT 0x1d |
| 351 | #define DWC_GRXTHRCFG_RSVD4_BMSK 0x10000000 |
| 352 | #define DWC_GRXTHRCFG_RSVD4_SHFT 0x1c |
| 353 | #define DWC_GRXTHRCFG_USBRXPKTCNT_BMSK 0xf000000 |
| 354 | #define DWC_GRXTHRCFG_USBRXPKTCNT_SHFT 0x18 |
| 355 | #define DWC_GRXTHRCFG_USBMAXRXBURSTSIZE_BMSK 0xf80000 |
| 356 | #define DWC_GRXTHRCFG_USBMAXRXBURSTSIZE_SHFT 0x13 |
| 357 | #define DWC_GRXTHRCFG_RSVD3_BMSK 0x70000 |
| 358 | #define DWC_GRXTHRCFG_RSVD3_SHFT 0x10 |
| 359 | #define DWC_GRXTHRCFG_RXTHREN_BMSK 0x8000 |
| 360 | #define DWC_GRXTHRCFG_RXTHREN_SHFT 0xf |
| 361 | #define DWC_GRXTHRCFG_RSVD2_BMSK 0x7800 |
| 362 | #define DWC_GRXTHRCFG_RSVD2_SHFT 0xb |
| 363 | #define DWC_GRXTHRCFG_RSVD1_BMSK 0x7ff |
| 364 | #define DWC_GRXTHRCFG_RSVD1_SHFT 0x0 |
| 365 | |
| 366 | #define DWC_GCTL_ADDR(x) ((x) + 0x0000c110) |
| 367 | #define DWC_GCTL_OFFS (0x0000c110) |
| 368 | #define DWC_GCTL_RMSK 0xffffffff |
| 369 | #define DWC_GCTL_POR 0x30c02000 |
| 370 | #define DWC_GCTL_PWRDNSCALE_BMSK 0xfff80000 |
| 371 | #define DWC_GCTL_PWRDNSCALE_SHFT 0x13 |
| 372 | #define DWC_GCTL_MASTERFILTBYPASS_BMSK 0x40000 |
| 373 | #define DWC_GCTL_MASTERFILTBYPASS_SHFT 0x12 |
| 374 | #define DWC_GCTL_BYPSSETADDR_BMSK 0x20000 |
| 375 | #define DWC_GCTL_BYPSSETADDR_SHFT 0x11 |
| 376 | #define DWC_GCTL_U2RSTECN_BMSK 0x10000 |
| 377 | #define DWC_GCTL_U2RSTECN_SHFT 0x10 |
| 378 | #define DWC_GCTL_FRMSCLDWN_BMSK 0xc000 |
| 379 | #define DWC_GCTL_FRMSCLDWN_SHFT 0xe |
| 380 | #define DWC_GCTL_PRTCAPDIR_BMSK 0x3000 |
| 381 | #define DWC_GCTL_PRTCAPDIR_SHFT 0xc |
| 382 | #define DWC_GCTL_CORESOFTRESET_BMSK 0x800 |
| 383 | #define DWC_GCTL_CORESOFTRESET_SHFT 0xb |
| 384 | #define DWC_GCTL_SOFITPSYNC_BMSK 0x400 |
| 385 | #define DWC_GCTL_SOFITPSYNC_SHFT 0xa |
| 386 | #define DWC_GCTL_U1U2TIMERSCALE_BMSK 0x200 |
| 387 | #define DWC_GCTL_U1U2TIMERSCALE_SHFT 0x9 |
| 388 | #define DWC_GCTL_DEBUGATTACH_BMSK 0x100 |
| 389 | #define DWC_GCTL_DEBUGATTACH_SHFT 0x8 |
| 390 | #define DWC_GCTL_RAMCLKSEL_BMSK 0xc0 |
| 391 | #define DWC_GCTL_RAMCLKSEL_SHFT 0x6 |
| 392 | #define DWC_GCTL_SCALEDOWN_BMSK 0x30 |
| 393 | #define DWC_GCTL_SCALEDOWN_SHFT 0x4 |
| 394 | #define DWC_GCTL_DISSCRAMBLE_BMSK 0x8 |
| 395 | #define DWC_GCTL_DISSCRAMBLE_SHFT 0x3 |
| 396 | #define DWC_GCTL_RSVD6_BMSK 0x4 |
| 397 | #define DWC_GCTL_RSVD6_SHFT 0x2 |
| 398 | #define DWC_GCTL_GBLHIBERNATIONEN_BMSK 0x2 |
| 399 | #define DWC_GCTL_GBLHIBERNATIONEN_SHFT 0x1 |
| 400 | #define DWC_GCTL_DSBLCLKGTNG_BMSK 0x1 |
| 401 | #define DWC_GCTL_DSBLCLKGTNG_SHFT 0x0 |
| 402 | |
| 403 | #define DWC_GSTS_ADDR(x) ((x) + 0x0000c118) |
| 404 | #define DWC_GSTS_OFFS (0x0000c118) |
| 405 | #define DWC_GSTS_RMSK 0xffffffff |
| 406 | #define DWC_GSTS_POR 0x3e800002 |
| 407 | #define DWC_GSTS_CBELT_BMSK 0xfff00000 |
| 408 | #define DWC_GSTS_CBELT_SHFT 0x14 |
| 409 | #define DWC_GSTS_RSVD7_BMSK 0xff800 |
| 410 | #define DWC_GSTS_RSVD7_SHFT 0xb |
| 411 | #define DWC_GSTS_OTG_IP_BMSK 0x400 |
| 412 | #define DWC_GSTS_OTG_IP_SHFT 0xa |
| 413 | #define DWC_GSTS_BC_IP_BMSK 0x200 |
| 414 | #define DWC_GSTS_BC_IP_SHFT 0x9 |
| 415 | #define DWC_GSTS_ADP_IP_BMSK 0x100 |
| 416 | #define DWC_GSTS_ADP_IP_SHFT 0x8 |
| 417 | #define DWC_GSTS_HOST_IP_BMSK 0x80 |
| 418 | #define DWC_GSTS_HOST_IP_SHFT 0x7 |
| 419 | #define DWC_GSTS_DEVICE_IP_BMSK 0x40 |
| 420 | #define DWC_GSTS_DEVICE_IP_SHFT 0x6 |
| 421 | #define DWC_GSTS_CSRTIMEOUT_BMSK 0x20 |
| 422 | #define DWC_GSTS_CSRTIMEOUT_SHFT 0x5 |
| 423 | #define DWC_GSTS_BUSERRADDRVLD_BMSK 0x10 |
| 424 | #define DWC_GSTS_BUSERRADDRVLD_SHFT 0x4 |
| 425 | #define DWC_GSTS_R6_BMSK 0xc |
| 426 | #define DWC_GSTS_R6_SHFT 0x2 |
| 427 | #define DWC_GSTS_CURMOD_BMSK 0x3 |
| 428 | #define DWC_GSTS_CURMOD_SHFT 0x0 |
| 429 | |
| 430 | #define DWC_GSNPSID_ADDR(x) ((x) + 0x0000c120) |
| 431 | #define DWC_GSNPSID_OFFS (0x0000c120) |
| 432 | #define DWC_GSNPSID_RMSK 0xffffffff |
| 433 | #define DWC_GSNPSID_POR 0x5533203a |
| 434 | #define DWC_GSNPSID_SYNOPSYSID_BMSK 0xffffffff |
| 435 | #define DWC_GSNPSID_SYNOPSYSID_SHFT 0x0 |
| 436 | |
| 437 | #define DWC_GGPIO_ADDR(x) ((x) + 0x0000c124) |
| 438 | #define DWC_GGPIO_OFFS (0x0000c124) |
| 439 | #define DWC_GGPIO_RMSK 0xffffffff |
| 440 | #define DWC_GGPIO_POR 0x00000000 |
| 441 | #define DWC_GGPIO_GPO_BMSK 0xffff0000 |
| 442 | #define DWC_GGPIO_GPO_SHFT 0x10 |
| 443 | #define DWC_GGPIO_GPI_BMSK 0xffff |
| 444 | #define DWC_GGPIO_GPI_SHFT 0x0 |
| 445 | |
| 446 | #define DWC_GUID_ADDR(x) ((x) + 0x0000c128) |
| 447 | #define DWC_GUID_OFFS (0x0000c128) |
| 448 | #define DWC_GUID_RMSK 0xffffffff |
| 449 | #define DWC_GUID_POR 0x11203a27 |
| 450 | #define DWC_GUID_USERID_BMSK 0xffffffff |
| 451 | #define DWC_GUID_USERID_SHFT 0x0 |
| 452 | |
| 453 | #define DWC_GUCTL_ADDR(x) ((x) + 0x0000c12c) |
| 454 | #define DWC_GUCTL_OFFS (0x0000c12c) |
| 455 | #define DWC_GUCTL_RMSK 0xffdfffff |
| 456 | #define DWC_GUCTL_POR 0x00008010 |
| 457 | #define DWC_GUCTL_REFCLKPER_BMSK 0xffc00000 |
| 458 | #define DWC_GUCTL_REFCLKPER_SHFT 0x16 |
| 459 | #define DWC_GUCTL_RSVD_BMSK 0x1c0000 |
| 460 | #define DWC_GUCTL_RSVD_SHFT 0x12 |
| 461 | #define DWC_GUCTL_SPRSCTRLTRANSEN_BMSK 0x20000 |
| 462 | #define DWC_GUCTL_SPRSCTRLTRANSEN_SHFT 0x11 |
| 463 | #define DWC_GUCTL_RESBWHSEPS_BMSK 0x10000 |
| 464 | #define DWC_GUCTL_RESBWHSEPS_SHFT 0x10 |
| 465 | #define DWC_GUCTL_CMDEVADDR_BMSK 0x8000 |
| 466 | #define DWC_GUCTL_CMDEVADDR_SHFT 0xf |
| 467 | #define DWC_GUCTL_USBHSTINAUTORETRYEN_BMSK 0x4000 |
| 468 | #define DWC_GUCTL_USBHSTINAUTORETRYEN_SHFT 0xe |
| 469 | #define DWC_GUCTL_RSVD7_BMSK 0x3000 |
| 470 | #define DWC_GUCTL_RSVD7_SHFT 0xc |
| 471 | #define DWC_GUCTL_INSRTEXTRFSBODI_BMSK 0x800 |
| 472 | #define DWC_GUCTL_INSRTEXTRFSBODI_SHFT 0xb |
| 473 | #define DWC_GUCTL_DTCT_BMSK 0x600 |
| 474 | #define DWC_GUCTL_DTCT_SHFT 0x9 |
| 475 | #define DWC_GUCTL_DTFT_BMSK 0x1ff |
| 476 | #define DWC_GUCTL_DTFT_SHFT 0x0 |
| 477 | |
| 478 | #define DWC_GBUSERRADDRLO_ADDR(x) ((x) + 0x0000c130) |
| 479 | #define DWC_GBUSERRADDRLO_OFFS (0x0000c130) |
| 480 | #define DWC_GBUSERRADDRLO_RMSK 0xffffffff |
| 481 | #define DWC_GBUSERRADDRLO_POR 0x00000000 |
| 482 | #define DWC_GBUSERRADDRLO_BUSERRADDR_BMSK 0xffffffff |
| 483 | #define DWC_GBUSERRADDRLO_BUSERRADDR_SHFT 0x0 |
| 484 | |
| 485 | #define DWC_GBUSERRADDRHI_ADDR(x) ((x) + 0x0000c134) |
| 486 | #define DWC_GBUSERRADDRHI_OFFS (0x0000c134) |
| 487 | #define DWC_GBUSERRADDRHI_RMSK 0xffffffff |
| 488 | #define DWC_GBUSERRADDRHI_POR 0x00000000 |
| 489 | #define DWC_GBUSERRADDRHI_BUSERRADDR_BMSK 0xffffffff |
| 490 | #define DWC_GBUSERRADDRHI_BUSERRADDR_SHFT 0x0 |
| 491 | |
| 492 | #define DWC_GPRTBIMAPLO_ADDR(x) ((x) + 0x0000c138) |
| 493 | #define DWC_GPRTBIMAPLO_OFFS (0x0000c138) |
| 494 | #define DWC_GPRTBIMAPLO_RMSK 0xffffffff |
| 495 | #define DWC_GPRTBIMAPLO_POR 0x00000000 |
| 496 | #define DWC_GPRTBIMAPLO_BINUM8_BMSK 0xf0000000 |
| 497 | #define DWC_GPRTBIMAPLO_BINUM8_SHFT 0x1c |
| 498 | #define DWC_GPRTBIMAPLO_BINUM7_BMSK 0xf000000 |
| 499 | #define DWC_GPRTBIMAPLO_BINUM7_SHFT 0x18 |
| 500 | #define DWC_GPRTBIMAPLO_BINUM6_BMSK 0xf00000 |
| 501 | #define DWC_GPRTBIMAPLO_BINUM6_SHFT 0x14 |
| 502 | #define DWC_GPRTBIMAPLO_BINUM5_BMSK 0xf0000 |
| 503 | #define DWC_GPRTBIMAPLO_BINUM5_SHFT 0x10 |
| 504 | #define DWC_GPRTBIMAPLO_BINUM4_BMSK 0xf000 |
| 505 | #define DWC_GPRTBIMAPLO_BINUM4_SHFT 0xc |
| 506 | #define DWC_GPRTBIMAPLO_BINUM3_BMSK 0xf00 |
| 507 | #define DWC_GPRTBIMAPLO_BINUM3_SHFT 0x8 |
| 508 | #define DWC_GPRTBIMAPLO_BINUM2_BMSK 0xf0 |
| 509 | #define DWC_GPRTBIMAPLO_BINUM2_SHFT 0x4 |
| 510 | #define DWC_GPRTBIMAPLO_BINUM1_BMSK 0xf |
| 511 | #define DWC_GPRTBIMAPLO_BINUM1_SHFT 0x0 |
| 512 | |
| 513 | #define DWC_GPRTBIMAPHI_ADDR(x) ((x) + 0x0000c13c) |
| 514 | #define DWC_GPRTBIMAPHI_OFFS (0x0000c13c) |
| 515 | #define DWC_GPRTBIMAPHI_RMSK 0xffffffff |
| 516 | #define DWC_GPRTBIMAPHI_POR 0x00000000 |
| 517 | #define DWC_GPRTBIMAPHI_RSVD16_BMSK 0xf0000000 |
| 518 | #define DWC_GPRTBIMAPHI_RSVD16_SHFT 0x1c |
| 519 | #define DWC_GPRTBIMAPHI_BINUM15_BMSK 0xf000000 |
| 520 | #define DWC_GPRTBIMAPHI_BINUM15_SHFT 0x18 |
| 521 | #define DWC_GPRTBIMAPHI_BINUM14_BMSK 0xf00000 |
| 522 | #define DWC_GPRTBIMAPHI_BINUM14_SHFT 0x14 |
| 523 | #define DWC_GPRTBIMAPHI_BINUM13_BMSK 0xf0000 |
| 524 | #define DWC_GPRTBIMAPHI_BINUM13_SHFT 0x10 |
| 525 | #define DWC_GPRTBIMAPHI_BINUM12_BMSK 0xf000 |
| 526 | #define DWC_GPRTBIMAPHI_BINUM12_SHFT 0xc |
| 527 | #define DWC_GPRTBIMAPHI_BINUM11_BMSK 0xf00 |
| 528 | #define DWC_GPRTBIMAPHI_BINUM11_SHFT 0x8 |
| 529 | #define DWC_GPRTBIMAPHI_BINUM10_BMSK 0xf0 |
| 530 | #define DWC_GPRTBIMAPHI_BINUM10_SHFT 0x4 |
| 531 | #define DWC_GPRTBIMAPHI_BINUM9_BMSK 0xf |
| 532 | #define DWC_GPRTBIMAPHI_BINUM9_SHFT 0x0 |
| 533 | |
| 534 | #define DWC_GHWPARAMS0_ADDR(x) ((x) + 0x0000c140) |
| 535 | #define DWC_GHWPARAMS0_OFFS (0x0000c140) |
| 536 | #define DWC_GHWPARAMS0_RMSK 0xfffffffb |
| 537 | #define DWC_GHWPARAMS0_POR 0x00000000 |
| 538 | #define DWC_GHWPARAMS0_GHWPARAMS0_31_24_BMSK 0xff000000 |
| 539 | #define DWC_GHWPARAMS0_GHWPARAMS0_31_24_SHFT 0x18 |
| 540 | #define DWC_GHWPARAMS0_GHWPARAMS0_23_16_BMSK 0xff0000 |
| 541 | #define DWC_GHWPARAMS0_GHWPARAMS0_23_16_SHFT 0x10 |
| 542 | #define DWC_GHWPARAMS0_GHWPARAMS0_15_8_BMSK 0xff00 |
| 543 | #define DWC_GHWPARAMS0_GHWPARAMS0_15_8_SHFT 0x8 |
| 544 | #define DWC_GHWPARAMS0_GHWPARAMS0_7_6_BMSK 0xc0 |
| 545 | #define DWC_GHWPARAMS0_GHWPARAMS0_7_6_SHFT 0x6 |
| 546 | #define DWC_GHWPARAMS0_GHWPARAMS0_5_3_BMSK 0x38 |
| 547 | #define DWC_GHWPARAMS0_GHWPARAMS0_5_3_SHFT 0x3 |
| 548 | #define DWC_GHWPARAMS0_GHWPARAMS0_2_0_BMSK 0x3 |
| 549 | #define DWC_GHWPARAMS0_GHWPARAMS0_2_0_SHFT 0x0 |
| 550 | |
| 551 | #define DWC_GHWPARAMS1_ADDR(x) ((x) + 0x0000c144) |
| 552 | #define DWC_GHWPARAMS1_OFFS (0x0000c144) |
| 553 | #define DWC_GHWPARAMS1_RMSK 0xffffffff |
| 554 | #define DWC_GHWPARAMS1_POR 0x01614938 |
| 555 | #define DWC_GHWPARAMS1_GHWPARAMS1_31_BMSK 0x80000000 |
| 556 | #define DWC_GHWPARAMS1_GHWPARAMS1_31_SHFT 0x1f |
| 557 | #define DWC_GHWPARAMS1_GHWPARAMS1_30_BMSK 0x40000000 |
| 558 | #define DWC_GHWPARAMS1_GHWPARAMS1_30_SHFT 0x1e |
| 559 | #define DWC_GHWPARAMS1_GHWPARAMS1_29_BMSK 0x20000000 |
| 560 | #define DWC_GHWPARAMS1_GHWPARAMS1_29_SHFT 0x1d |
| 561 | #define DWC_GHWPARAMS1_GHWPARAMS1_28_BMSK 0x10000000 |
| 562 | #define DWC_GHWPARAMS1_GHWPARAMS1_28_SHFT 0x1c |
| 563 | #define DWC_GHWPARAMS1_GHWPARAMS1_27_BMSK 0x8000000 |
| 564 | #define DWC_GHWPARAMS1_GHWPARAMS1_27_SHFT 0x1b |
| 565 | #define DWC_GHWPARAMS1_GHWPARAMS1_26_BMSK 0x4000000 |
| 566 | #define DWC_GHWPARAMS1_GHWPARAMS1_26_SHFT 0x1a |
| 567 | #define DWC_GHWPARAMS1_GHWPARAMS1_25_24_BMSK 0x3000000 |
| 568 | #define DWC_GHWPARAMS1_GHWPARAMS1_25_24_SHFT 0x18 |
| 569 | #define DWC_GHWPARAMS1_GHWPARAMS1_23_BMSK 0x800000 |
| 570 | #define DWC_GHWPARAMS1_GHWPARAMS1_23_SHFT 0x17 |
| 571 | #define DWC_GHWPARAMS1_GHWPARAMS1_22_21_BMSK 0x600000 |
| 572 | #define DWC_GHWPARAMS1_GHWPARAMS1_22_21_SHFT 0x15 |
| 573 | #define DWC_GHWPARAMS1_GHWPARAMS1_20_15_BMSK 0x1f8000 |
| 574 | #define DWC_GHWPARAMS1_GHWPARAMS1_20_15_SHFT 0xf |
| 575 | #define DWC_GHWPARAMS1_GHWPARAMS1_14_12_BMSK 0x7000 |
| 576 | #define DWC_GHWPARAMS1_GHWPARAMS1_14_12_SHFT 0xc |
| 577 | #define DWC_GHWPARAMS1_GHWPARAMS1_11_9_BMSK 0xe00 |
| 578 | #define DWC_GHWPARAMS1_GHWPARAMS1_11_9_SHFT 0x9 |
| 579 | #define DWC_GHWPARAMS1_GHWPARAMS1_8_6_BMSK 0x1c0 |
| 580 | #define DWC_GHWPARAMS1_GHWPARAMS1_8_6_SHFT 0x6 |
| 581 | #define DWC_GHWPARAMS1_GHWPARAMS1_5_3_BMSK 0x38 |
| 582 | #define DWC_GHWPARAMS1_GHWPARAMS1_5_3_SHFT 0x3 |
| 583 | #define DWC_GHWPARAMS1_GHWPARAMS1_2_0_BMSK 0x7 |
| 584 | #define DWC_GHWPARAMS1_GHWPARAMS1_2_0_SHFT 0x0 |
| 585 | |
| 586 | #define DWC_GHWPARAMS2_ADDR(x) ((x) + 0x0000c148) |
| 587 | #define DWC_GHWPARAMS2_OFFS (0x0000c148) |
| 588 | #define DWC_GHWPARAMS2_RMSK 0xffffffff |
| 589 | #define DWC_GHWPARAMS2_POR 0x11203a27 |
| 590 | #define DWC_GHWPARAMS2_GHWPARAMS2_31_0_BMSK 0xffffffff |
| 591 | #define DWC_GHWPARAMS2_GHWPARAMS2_31_0_SHFT 0x0 |
| 592 | |
| 593 | #define DWC_GHWPARAMS3_ADDR(x) ((x) + 0x0000c14c) |
| 594 | #define DWC_GHWPARAMS3_OFFS (0x0000c14c) |
| 595 | #define DWC_GHWPARAMS3_RMSK 0xffffffff |
| 596 | #define DWC_GHWPARAMS3_POR 0x10420085 |
| 597 | #define DWC_GHWPARAMS3_GHWPARAMS3_31_BMSK 0x80000000 |
| 598 | #define DWC_GHWPARAMS3_GHWPARAMS3_31_SHFT 0x1f |
| 599 | #define DWC_GHWPARAMS3_GHWPARAMS3_30_23_BMSK 0x7f800000 |
| 600 | #define DWC_GHWPARAMS3_GHWPARAMS3_30_23_SHFT 0x17 |
| 601 | #define DWC_GHWPARAMS3_GHWPARAMS3_22_18_BMSK 0x7c0000 |
| 602 | #define DWC_GHWPARAMS3_GHWPARAMS3_22_18_SHFT 0x12 |
| 603 | #define DWC_GHWPARAMS3_GHWPARAMS3_17_12_BMSK 0x3f000 |
| 604 | #define DWC_GHWPARAMS3_GHWPARAMS3_17_12_SHFT 0xc |
| 605 | #define DWC_GHWPARAMS3_GHWPARAMS3_11_BMSK 0x800 |
| 606 | #define DWC_GHWPARAMS3_GHWPARAMS3_11_SHFT 0xb |
| 607 | #define DWC_GHWPARAMS3_GHWPARAMS3_10_BMSK 0x400 |
| 608 | #define DWC_GHWPARAMS3_GHWPARAMS3_10_SHFT 0xa |
| 609 | #define DWC_GHWPARAMS3_GHWPARAMS3_9_8_BMSK 0x300 |
| 610 | #define DWC_GHWPARAMS3_GHWPARAMS3_9_8_SHFT 0x8 |
| 611 | #define DWC_GHWPARAMS3_GHWPARAMS3_7_6_BMSK 0xc0 |
| 612 | #define DWC_GHWPARAMS3_GHWPARAMS3_7_6_SHFT 0x6 |
| 613 | #define DWC_GHWPARAMS3_GHWPARAMS3_5_4_BMSK 0x30 |
| 614 | #define DWC_GHWPARAMS3_GHWPARAMS3_5_4_SHFT 0x4 |
| 615 | #define DWC_GHWPARAMS3_GHWPARAMS3_3_2_BMSK 0xc |
| 616 | #define DWC_GHWPARAMS3_GHWPARAMS3_3_2_SHFT 0x2 |
| 617 | #define DWC_GHWPARAMS3_GHWPARAMS3_1_0_BMSK 0x3 |
| 618 | #define DWC_GHWPARAMS3_GHWPARAMS3_1_0_SHFT 0x0 |
| 619 | |
| 620 | #define DWC_GHWPARAMS4_ADDR(x) ((x) + 0x0000c150) |
| 621 | #define DWC_GHWPARAMS4_OFFS (0x0000c150) |
| 622 | #define DWC_GHWPARAMS4_RMSK 0xffffffff |
| 623 | #define DWC_GHWPARAMS4_POR 0x48822005 |
| 624 | #define DWC_GHWPARAMS4_GHWPARAMS4_31_28_BMSK 0xf0000000 |
| 625 | #define DWC_GHWPARAMS4_GHWPARAMS4_31_28_SHFT 0x1c |
| 626 | #define DWC_GHWPARAMS4_GHWPARAMS4_27_24_BMSK 0xf000000 |
| 627 | #define DWC_GHWPARAMS4_GHWPARAMS4_27_24_SHFT 0x18 |
| 628 | #define DWC_GHWPARAMS4_GHWPARAMS4_23_BMSK 0x800000 |
| 629 | #define DWC_GHWPARAMS4_GHWPARAMS4_23_SHFT 0x17 |
| 630 | #define DWC_GHWPARAMS4_GHWPARAMS4_22_BMSK 0x400000 |
| 631 | #define DWC_GHWPARAMS4_GHWPARAMS4_22_SHFT 0x16 |
| 632 | #define DWC_GHWPARAMS4_GHWPARAMS4_21_BMSK 0x200000 |
| 633 | #define DWC_GHWPARAMS4_GHWPARAMS4_21_SHFT 0x15 |
| 634 | #define DWC_GHWPARAMS4_GHWPARAMS4_20_17_BMSK 0x1e0000 |
| 635 | #define DWC_GHWPARAMS4_GHWPARAMS4_20_17_SHFT 0x11 |
| 636 | #define DWC_GHWPARAMS4_GHWPARAMS4_16_13_BMSK 0x1e000 |
| 637 | #define DWC_GHWPARAMS4_GHWPARAMS4_16_13_SHFT 0xd |
| 638 | #define DWC_GHWPARAMS4_GHWPARAMS4_12_6_BMSK 0x1fc0 |
| 639 | #define DWC_GHWPARAMS4_GHWPARAMS4_12_6_SHFT 0x6 |
| 640 | #define DWC_GHWPARAMS4_GHWPARAMS4_5_0_BMSK 0x3f |
| 641 | #define DWC_GHWPARAMS4_GHWPARAMS4_5_0_SHFT 0x0 |
| 642 | |
| 643 | #define DWC_GHWPARAMS5_ADDR(x) ((x) + 0x0000c154) |
| 644 | #define DWC_GHWPARAMS5_OFFS (0x0000c154) |
| 645 | #define DWC_GHWPARAMS5_RMSK 0xffffffff |
| 646 | #define DWC_GHWPARAMS5_POR 0x04202088 |
| 647 | #define DWC_GHWPARAMS5_GHWPARAMS5_31_28_BMSK 0xf0000000 |
| 648 | #define DWC_GHWPARAMS5_GHWPARAMS5_31_28_SHFT 0x1c |
| 649 | #define DWC_GHWPARAMS5_GHWPARAMS5_27_22_BMSK 0xfc00000 |
| 650 | #define DWC_GHWPARAMS5_GHWPARAMS5_27_22_SHFT 0x16 |
| 651 | #define DWC_GHWPARAMS5_GHWPARAMS5_21_16_BMSK 0x3f0000 |
| 652 | #define DWC_GHWPARAMS5_GHWPARAMS5_21_16_SHFT 0x10 |
| 653 | #define DWC_GHWPARAMS5_GHWPARAMS5_15_10_BMSK 0xfc00 |
| 654 | #define DWC_GHWPARAMS5_GHWPARAMS5_15_10_SHFT 0xa |
| 655 | #define DWC_GHWPARAMS5_GHWPARAMS5_9_4_BMSK 0x3f0 |
| 656 | #define DWC_GHWPARAMS5_GHWPARAMS5_9_4_SHFT 0x4 |
| 657 | #define DWC_GHWPARAMS5_GHWPARAMS5_3_0_BMSK 0xf |
| 658 | #define DWC_GHWPARAMS5_GHWPARAMS5_3_0_SHFT 0x0 |
| 659 | |
| 660 | #define DWC_GHWPARAMS6_ADDR(x) ((x) + 0x0000c158) |
| 661 | #define DWC_GHWPARAMS6_OFFS (0x0000c158) |
| 662 | #define DWC_GHWPARAMS6_RMSK 0xffffffff |
| 663 | #define DWC_GHWPARAMS6_POR 0x065c8c20 |
| 664 | #define DWC_GHWPARAMS6_GHWPARAMS6_31_16_BMSK 0xffff0000 |
| 665 | #define DWC_GHWPARAMS6_GHWPARAMS6_31_16_SHFT 0x10 |
| 666 | #define DWC_GHWPARAMS6_BUSFLTRSSUPPORT_BMSK 0x8000 |
| 667 | #define DWC_GHWPARAMS6_BUSFLTRSSUPPORT_SHFT 0xf |
| 668 | #define DWC_GHWPARAMS6_BCSUPPORT_BMSK 0x4000 |
| 669 | #define DWC_GHWPARAMS6_BCSUPPORT_SHFT 0xe |
| 670 | #define DWC_GHWPARAMS6_OTG_SS_SUPPORT_BMSK 0x2000 |
| 671 | #define DWC_GHWPARAMS6_OTG_SS_SUPPORT_SHFT 0xd |
| 672 | #define DWC_GHWPARAMS6_ADPSUPPORT_BMSK 0x1000 |
| 673 | #define DWC_GHWPARAMS6_ADPSUPPORT_SHFT 0xc |
| 674 | #define DWC_GHWPARAMS6_HNPSUPPORT_BMSK 0x800 |
| 675 | #define DWC_GHWPARAMS6_HNPSUPPORT_SHFT 0xb |
| 676 | #define DWC_GHWPARAMS6_SRPSUPPORT_BMSK 0x400 |
| 677 | #define DWC_GHWPARAMS6_SRPSUPPORT_SHFT 0xa |
| 678 | #define DWC_GHWPARAMS6_GHWPARAMS6_9_8_BMSK 0x300 |
| 679 | #define DWC_GHWPARAMS6_GHWPARAMS6_9_8_SHFT 0x8 |
| 680 | #define DWC_GHWPARAMS6_GHWPARAMS6_7_BMSK 0x80 |
| 681 | #define DWC_GHWPARAMS6_GHWPARAMS6_7_SHFT 0x7 |
| 682 | #define DWC_GHWPARAMS6_GHWPARAMS6_6_BMSK 0x40 |
| 683 | #define DWC_GHWPARAMS6_GHWPARAMS6_6_SHFT 0x6 |
| 684 | #define DWC_GHWPARAMS6_GHWPARAMS6_5_0_BMSK 0x3f |
| 685 | #define DWC_GHWPARAMS6_GHWPARAMS6_5_0_SHFT 0x0 |
| 686 | |
| 687 | #define DWC_GHWPARAMS7_ADDR(x) ((x) + 0x0000c15c) |
| 688 | #define DWC_GHWPARAMS7_OFFS (0x0000c15c) |
| 689 | #define DWC_GHWPARAMS7_RMSK 0xffffffff |
| 690 | #define DWC_GHWPARAMS7_POR 0x03080cea |
| 691 | #define DWC_GHWPARAMS7_GHWPARAMS7_31_16_BMSK 0xffff0000 |
| 692 | #define DWC_GHWPARAMS7_GHWPARAMS7_31_16_SHFT 0x10 |
| 693 | #define DWC_GHWPARAMS7_GHWPARAMS7_15_0_BMSK 0xffff |
| 694 | #define DWC_GHWPARAMS7_GHWPARAMS7_15_0_SHFT 0x0 |
| 695 | |
| 696 | #define DWC_GDBGFIFOSPACE_ADDR(x) ((x) + 0x0000c160) |
| 697 | #define DWC_GDBGFIFOSPACE_OFFS (0x0000c160) |
| 698 | #define DWC_GDBGFIFOSPACE_RMSK 0xffffffff |
| 699 | #define DWC_GDBGFIFOSPACE_POR 0x00820000 |
| 700 | #define DWC_GDBGFIFOSPACE_SPACE_AVAILABLE_BMSK 0xffff0000 |
| 701 | #define DWC_GDBGFIFOSPACE_SPACE_AVAILABLE_SHFT 0x10 |
| 702 | #define DWC_GDBGFIFOSPACE_RSVD8_BMSK 0xff00 |
| 703 | #define DWC_GDBGFIFOSPACE_RSVD8_SHFT 0x8 |
| 704 | #define DWC_GDBGFIFOSPACE_FIFO_QUEUE_SELECT_BMSK 0xff |
| 705 | #define DWC_GDBGFIFOSPACE_FIFO_QUEUE_SELECT_SHFT 0x0 |
| 706 | |
| 707 | #define DWC_GDBGLTSSM_ADDR(x) ((x) + 0x0000c164) |
| 708 | #define DWC_GDBGLTSSM_OFFS (0x0000c164) |
| 709 | #define DWC_GDBGLTSSM_RMSK 0xfddfffdf |
| 710 | #define DWC_GDBGLTSSM_POR 0x00000000 |
| 711 | #define DWC_GDBGLTSSM_RSVD14_BMSK 0xc0000000 |
| 712 | #define DWC_GDBGLTSSM_RSVD14_SHFT 0x1e |
| 713 | #define DWC_GDBGLTSSM_X3_XS_SWAPPING_BMSK 0x20000000 |
| 714 | #define DWC_GDBGLTSSM_X3_XS_SWAPPING_SHFT 0x1d |
| 715 | #define DWC_GDBGLTSSM_X3_DS_HOST_SHUTDOWN_BMSK 0x10000000 |
| 716 | #define DWC_GDBGLTSSM_X3_DS_HOST_SHUTDOWN_SHFT 0x1c |
| 717 | #define DWC_GDBGLTSSM_PRTDIRECTION_BMSK 0x8000000 |
| 718 | #define DWC_GDBGLTSSM_PRTDIRECTION_SHFT 0x1b |
| 719 | #define DWC_GDBGLTSSM_LTDBTIMEOUT_BMSK 0x4000000 |
| 720 | #define DWC_GDBGLTSSM_LTDBTIMEOUT_SHFT 0x1a |
| 721 | #define DWC_GDBGLTSSM_LTDBLINKSTATE_BMSK 0x1c00000 |
| 722 | #define DWC_GDBGLTSSM_LTDBLINKSTATE_SHFT 0x16 |
| 723 | #define DWC_GDBGLTSSM_LTDBSUBSTATE_BMSK 0x1c0000 |
| 724 | #define DWC_GDBGLTSSM_LTDBSUBSTATE_SHFT 0x12 |
| 725 | #define DWC_GDBGLTSSM_ELASTICBUFFERMODE_BMSK 0x20000 |
| 726 | #define DWC_GDBGLTSSM_ELASTICBUFFERMODE_SHFT 0x11 |
| 727 | #define DWC_GDBGLTSSM_TXELECLDLE_BMSK 0x10000 |
| 728 | #define DWC_GDBGLTSSM_TXELECLDLE_SHFT 0x10 |
| 729 | #define DWC_GDBGLTSSM_RXPOLARITY_BMSK 0x8000 |
| 730 | #define DWC_GDBGLTSSM_RXPOLARITY_SHFT 0xf |
| 731 | #define DWC_GDBGLTSSM_TXDETRXLOOPBACK_BMSK 0x4000 |
| 732 | #define DWC_GDBGLTSSM_TXDETRXLOOPBACK_SHFT 0xe |
| 733 | #define DWC_GDBGLTSSM_RSVD12_BMSK 0x2000 |
| 734 | #define DWC_GDBGLTSSM_RSVD12_SHFT 0xd |
| 735 | #define DWC_GDBGLTSSM_LTDBPHYCMDSTATE_BMSK 0x1800 |
| 736 | #define DWC_GDBGLTSSM_LTDBPHYCMDSTATE_SHFT 0xb |
| 737 | #define DWC_GDBGLTSSM_POWERDOWN_BMSK 0x600 |
| 738 | #define DWC_GDBGLTSSM_POWERDOWN_SHFT 0x9 |
| 739 | #define DWC_GDBGLTSSM_RXEQTRAIN_BMSK 0x100 |
| 740 | #define DWC_GDBGLTSSM_RXEQTRAIN_SHFT 0x8 |
| 741 | #define DWC_GDBGLTSSM_TXDEEMPHASIS_BMSK 0xc0 |
| 742 | #define DWC_GDBGLTSSM_TXDEEMPHASIS_SHFT 0x6 |
| 743 | #define DWC_GDBGLTSSM_LTDBCLKSTATE_BMSK 0x18 |
| 744 | #define DWC_GDBGLTSSM_LTDBCLKSTATE_SHFT 0x3 |
| 745 | #define DWC_GDBGLTSSM_TXSWING_BMSK 0x4 |
| 746 | #define DWC_GDBGLTSSM_TXSWING_SHFT 0x2 |
| 747 | #define DWC_GDBGLTSSM_RXTERMINATION_BMSK 0x2 |
| 748 | #define DWC_GDBGLTSSM_RXTERMINATION_SHFT 0x1 |
| 749 | #define DWC_GDBGLTSSM_TXONESZEROS_BMSK 0x1 |
| 750 | #define DWC_GDBGLTSSM_TXONESZEROS_SHFT 0x0 |
| 751 | |
| 752 | #define DWC_GDBGLNMCC_ADDR(x) ((x) + 0x0000c168) |
| 753 | #define DWC_GDBGLNMCC_OFFS (0x0000c168) |
| 754 | #define DWC_GDBGLNMCC_RMSK 0x7ffffeff |
| 755 | #define DWC_GDBGLNMCC_POR 0x00000000 |
| 756 | #define DWC_GDBGLNMCC_RSVD2_BMSK 0x7ffffe00 |
| 757 | #define DWC_GDBGLNMCC_RSVD2_SHFT 0x9 |
| 758 | #define DWC_GDBGLNMCC_LNMCC_BERC_BMSK 0xff |
| 759 | #define DWC_GDBGLNMCC_LNMCC_BERC_SHFT 0x0 |
| 760 | |
| 761 | #define DWC_GDBGBMU_ADDR(x) ((x) + 0x0000c16c) |
| 762 | #define DWC_GDBGBMU_OFFS (0x0000c16c) |
| 763 | #define DWC_GDBGBMU_RMSK 0xffffffff |
| 764 | #define DWC_GDBGBMU_POR 0x00000000 |
| 765 | #define DWC_GDBGBMU_BMU_BCU_BMSK 0xffffff00 |
| 766 | #define DWC_GDBGBMU_BMU_BCU_SHFT 0x8 |
| 767 | #define DWC_GDBGBMU_BMU_DCU_BMSK 0xf0 |
| 768 | #define DWC_GDBGBMU_BMU_DCU_SHFT 0x4 |
| 769 | #define DWC_GDBGBMU_BMU_CCU_BMSK 0xf |
| 770 | #define DWC_GDBGBMU_BMU_CCU_SHFT 0x0 |
| 771 | |
| 772 | #define DWC_GDBGLSPMUX_HST_ADDR(x) ((x) + 0x0000c170) |
| 773 | #define DWC_GDBGLSPMUX_HST_OFFS (0x0000c170) |
| 774 | #define DWC_GDBGLSPMUX_HST_RMSK 0xffffffff |
| 775 | #define DWC_GDBGLSPMUX_HST_POR 0x00000000 |
| 776 | #define DWC_GDBGLSPMUX_HST_RSVD3_BMSK 0xffffc000 |
| 777 | #define DWC_GDBGLSPMUX_HST_RSVD3_SHFT 0xe |
| 778 | #define DWC_GDBGLSPMUX_HST_HOSTSELECT_BMSK 0x3fff |
| 779 | #define DWC_GDBGLSPMUX_HST_HOSTSELECT_SHFT 0x0 |
| 780 | |
| 781 | #define DWC_GDBGLSP_ADDR(x) ((x) + 0x0000c174) |
| 782 | #define DWC_GDBGLSP_OFFS (0x0000c174) |
| 783 | #define DWC_GDBGLSP_RMSK 0xffffffff |
| 784 | #define DWC_GDBGLSP_POR 0x00000000 |
| 785 | #define DWC_GDBGLSP_LSPDEBUG_BMSK 0xffffffff |
| 786 | #define DWC_GDBGLSP_LSPDEBUG_SHFT 0x0 |
| 787 | |
| 788 | #define DWC_GDBGEPINFO0_ADDR(x) ((x) + 0x0000c178) |
| 789 | #define DWC_GDBGEPINFO0_OFFS (0x0000c178) |
| 790 | #define DWC_GDBGEPINFO0_RMSK 0xffffffff |
| 791 | #define DWC_GDBGEPINFO0_POR 0x00000000 |
| 792 | #define DWC_GDBGEPINFO0_EPDEBUG_BMSK 0xffffffff |
| 793 | #define DWC_GDBGEPINFO0_EPDEBUG_SHFT 0x0 |
| 794 | |
| 795 | #define DWC_GDBGEPINFO1_ADDR(x) ((x) + 0x0000c17c) |
| 796 | #define DWC_GDBGEPINFO1_OFFS (0x0000c17c) |
| 797 | #define DWC_GDBGEPINFO1_RMSK 0xffffffff |
| 798 | #define DWC_GDBGEPINFO1_POR 0x00000000 |
| 799 | #define DWC_GDBGEPINFO1_EPDEBUG_BMSK 0xffffffff |
| 800 | #define DWC_GDBGEPINFO1_EPDEBUG_SHFT 0x0 |
| 801 | |
| 802 | #define DWC_GPRTBIMAP_HSLO_ADDR(x) ((x) + 0x0000c180) |
| 803 | #define DWC_GPRTBIMAP_HSLO_OFFS (0x0000c180) |
| 804 | #define DWC_GPRTBIMAP_HSLO_RMSK 0xffffffff |
| 805 | #define DWC_GPRTBIMAP_HSLO_POR 0x00000000 |
| 806 | #define DWC_GPRTBIMAP_HSLO_BINUM8_BMSK 0xf0000000 |
| 807 | #define DWC_GPRTBIMAP_HSLO_BINUM8_SHFT 0x1c |
| 808 | #define DWC_GPRTBIMAP_HSLO_BINUM7_BMSK 0xf000000 |
| 809 | #define DWC_GPRTBIMAP_HSLO_BINUM7_SHFT 0x18 |
| 810 | #define DWC_GPRTBIMAP_HSLO_BINUM6_BMSK 0xf00000 |
| 811 | #define DWC_GPRTBIMAP_HSLO_BINUM6_SHFT 0x14 |
| 812 | #define DWC_GPRTBIMAP_HSLO_BINUM5_BMSK 0xf0000 |
| 813 | #define DWC_GPRTBIMAP_HSLO_BINUM5_SHFT 0x10 |
| 814 | #define DWC_GPRTBIMAP_HSLO_BINUM4_BMSK 0xf000 |
| 815 | #define DWC_GPRTBIMAP_HSLO_BINUM4_SHFT 0xc |
| 816 | #define DWC_GPRTBIMAP_HSLO_BINUM3_BMSK 0xf00 |
| 817 | #define DWC_GPRTBIMAP_HSLO_BINUM3_SHFT 0x8 |
| 818 | #define DWC_GPRTBIMAP_HSLO_BINUM2_BMSK 0xf0 |
| 819 | #define DWC_GPRTBIMAP_HSLO_BINUM2_SHFT 0x4 |
| 820 | #define DWC_GPRTBIMAP_HSLO_BINUM1_BMSK 0xf |
| 821 | #define DWC_GPRTBIMAP_HSLO_BINUM1_SHFT 0x0 |
| 822 | |
| 823 | #define DWC_GPRTBIMAP_HSHI_ADDR(x) ((x) + 0x0000c184) |
| 824 | #define DWC_GPRTBIMAP_HSHI_OFFS (0x0000c184) |
| 825 | #define DWC_GPRTBIMAP_HSHI_RMSK 0xffffffff |
| 826 | #define DWC_GPRTBIMAP_HSHI_POR 0x00000000 |
| 827 | #define DWC_GPRTBIMAP_HSHI_RSVD16_BMSK 0xf0000000 |
| 828 | #define DWC_GPRTBIMAP_HSHI_RSVD16_SHFT 0x1c |
| 829 | #define DWC_GPRTBIMAP_HSHI_BINUM15_BMSK 0xf000000 |
| 830 | #define DWC_GPRTBIMAP_HSHI_BINUM15_SHFT 0x18 |
| 831 | #define DWC_GPRTBIMAP_HSHI_BINUM14_BMSK 0xf00000 |
| 832 | #define DWC_GPRTBIMAP_HSHI_BINUM14_SHFT 0x14 |
| 833 | #define DWC_GPRTBIMAP_HSHI_BINUM13_BMSK 0xf0000 |
| 834 | #define DWC_GPRTBIMAP_HSHI_BINUM13_SHFT 0x10 |
| 835 | #define DWC_GPRTBIMAP_HSHI_BINUM12_BMSK 0xf000 |
| 836 | #define DWC_GPRTBIMAP_HSHI_BINUM12_SHFT 0xc |
| 837 | #define DWC_GPRTBIMAP_HSHI_BINUM11_BMSK 0xf00 |
| 838 | #define DWC_GPRTBIMAP_HSHI_BINUM11_SHFT 0x8 |
| 839 | #define DWC_GPRTBIMAP_HSHI_BINUM10_BMSK 0xf0 |
| 840 | #define DWC_GPRTBIMAP_HSHI_BINUM10_SHFT 0x4 |
| 841 | #define DWC_GPRTBIMAP_HSHI_BINUM9_BMSK 0xf |
| 842 | #define DWC_GPRTBIMAP_HSHI_BINUM9_SHFT 0x0 |
| 843 | |
| 844 | #define DWC_GPRTBIMAP_FSLO_ADDR(x) ((x) + 0x0000c188) |
| 845 | #define DWC_GPRTBIMAP_FSLO_OFFS (0x0000c188) |
| 846 | #define DWC_GPRTBIMAP_FSLO_RMSK 0xffffffff |
| 847 | #define DWC_GPRTBIMAP_FSLO_POR 0x00000000 |
| 848 | #define DWC_GPRTBIMAP_FSLO_BINUM8_BMSK 0xf0000000 |
| 849 | #define DWC_GPRTBIMAP_FSLO_BINUM8_SHFT 0x1c |
| 850 | #define DWC_GPRTBIMAP_FSLO_BINUM7_BMSK 0xf000000 |
| 851 | #define DWC_GPRTBIMAP_FSLO_BINUM7_SHFT 0x18 |
| 852 | #define DWC_GPRTBIMAP_FSLO_BINUM6_BMSK 0xf00000 |
| 853 | #define DWC_GPRTBIMAP_FSLO_BINUM6_SHFT 0x14 |
| 854 | #define DWC_GPRTBIMAP_FSLO_BINUM5_BMSK 0xf0000 |
| 855 | #define DWC_GPRTBIMAP_FSLO_BINUM5_SHFT 0x10 |
| 856 | #define DWC_GPRTBIMAP_FSLO_BINUM4_BMSK 0xf000 |
| 857 | #define DWC_GPRTBIMAP_FSLO_BINUM4_SHFT 0xc |
| 858 | #define DWC_GPRTBIMAP_FSLO_BINUM3_BMSK 0xf00 |
| 859 | #define DWC_GPRTBIMAP_FSLO_BINUM3_SHFT 0x8 |
| 860 | #define DWC_GPRTBIMAP_FSLO_BINUM2_BMSK 0xf0 |
| 861 | #define DWC_GPRTBIMAP_FSLO_BINUM2_SHFT 0x4 |
| 862 | #define DWC_GPRTBIMAP_FSLO_BINUM1_BMSK 0xf |
| 863 | #define DWC_GPRTBIMAP_FSLO_BINUM1_SHFT 0x0 |
| 864 | |
| 865 | #define DWC_GPRTBIMAP_FSHI_ADDR(x) ((x) + 0x0000c18c) |
| 866 | #define DWC_GPRTBIMAP_FSHI_OFFS (0x0000c18c) |
| 867 | #define DWC_GPRTBIMAP_FSHI_RMSK 0xffffffff |
| 868 | #define DWC_GPRTBIMAP_FSHI_POR 0x00000000 |
| 869 | #define DWC_GPRTBIMAP_FSHI_RSVD16_BMSK 0xf0000000 |
| 870 | #define DWC_GPRTBIMAP_FSHI_RSVD16_SHFT 0x1c |
| 871 | #define DWC_GPRTBIMAP_FSHI_BINUM15_BMSK 0xf000000 |
| 872 | #define DWC_GPRTBIMAP_FSHI_BINUM15_SHFT 0x18 |
| 873 | #define DWC_GPRTBIMAP_FSHI_BINUM14_BMSK 0xf00000 |
| 874 | #define DWC_GPRTBIMAP_FSHI_BINUM14_SHFT 0x14 |
| 875 | #define DWC_GPRTBIMAP_FSHI_BINUM13_BMSK 0xf0000 |
| 876 | #define DWC_GPRTBIMAP_FSHI_BINUM13_SHFT 0x10 |
| 877 | #define DWC_GPRTBIMAP_FSHI_BINUM12_BMSK 0xf000 |
| 878 | #define DWC_GPRTBIMAP_FSHI_BINUM12_SHFT 0xc |
| 879 | #define DWC_GPRTBIMAP_FSHI_BINUM11_BMSK 0xf00 |
| 880 | #define DWC_GPRTBIMAP_FSHI_BINUM11_SHFT 0x8 |
| 881 | #define DWC_GPRTBIMAP_FSHI_BINUM10_BMSK 0xf0 |
| 882 | #define DWC_GPRTBIMAP_FSHI_BINUM10_SHFT 0x4 |
| 883 | #define DWC_GPRTBIMAP_FSHI_BINUM9_BMSK 0xf |
| 884 | #define DWC_GPRTBIMAP_FSHI_BINUM9_SHFT 0x0 |
| 885 | |
| 886 | #define DWC_GHWPARAMS8_ADDR(x) ((x) + 0x0000c600) |
| 887 | #define DWC_GHWPARAMS8_OFFS (0x0000c600) |
| 888 | #define DWC_GHWPARAMS8_RMSK 0xffffffff |
| 889 | #define DWC_GHWPARAMS8_POR 0x0000065c |
| 890 | #define DWC_GHWPARAMS8_GHWPARAMS8_32_0_BMSK 0xffffffff |
| 891 | #define DWC_GHWPARAMS8_GHWPARAMS8_32_0_SHFT 0x0 |
| 892 | |
| 893 | #define DWC_DEPCMDPAR2_ADDR(base,p) ((base) + 0x0000c800 + 0x10 * (p)) |
| 894 | #define DWC_DEPCMDPAR2_OFFS(p) (0x0000c800 + 0x10 * (p)) |
| 895 | #define DWC_DEPCMDPAR2_RMSK 0xffffffff |
| 896 | #define DWC_DEPCMDPAR2_MAXp 31 |
| 897 | #define DWC_DEPCMDPAR2_POR 0x00000000 |
| 898 | #define DWC_DEPCMDPAR2_PARAMETER_BMSK 0xffffffff |
| 899 | #define DWC_DEPCMDPAR2_PARAMETER_SHFT 0x0 |
| 900 | |
| 901 | #define DWC_DEPCMDPAR1_ADDR(base,p) ((base) + 0x0000c804 + 0x10 * (p)) |
| 902 | #define DWC_DEPCMDPAR1_OFFS(p) (0x0000c804 + 0x10 * (p)) |
| 903 | #define DWC_DEPCMDPAR1_RMSK 0xffffffff |
| 904 | #define DWC_DEPCMDPAR1_MAXp 31 |
| 905 | #define DWC_DEPCMDPAR1_POR 0x00000000 |
| 906 | #define DWC_DEPCMDPAR1_PARAMETER_BMSK 0xffffffff |
| 907 | #define DWC_DEPCMDPAR1_PARAMETER_SHFT 0x0 |
| 908 | |
| 909 | #define DWC_DEPCMDPAR0_ADDR(base,p) ((base) + 0x0000c808 + 0x10 * (p)) |
| 910 | #define DWC_DEPCMDPAR0_OFFS(p) (0x0000c808 + 0x10 * (p)) |
| 911 | #define DWC_DEPCMDPAR0_RMSK 0xffffffff |
| 912 | #define DWC_DEPCMDPAR0_MAXp 31 |
| 913 | #define DWC_DEPCMDPAR0_POR 0x00000000 |
| 914 | #define DWC_DEPCMDPAR0_PARAMETER_BMSK 0xffffffff |
| 915 | #define DWC_DEPCMDPAR0_PARAMETER_SHFT 0x0 |
| 916 | |
| 917 | #define DWC_DEPCMD_ADDR(base,p) ((base) + 0x0000c80c + 0x10 * (p)) |
| 918 | #define DWC_DEPCMD_OFFS(p) (0x0000c80c + 0x10 * (p)) |
| 919 | #define DWC_DEPCMD_RMSK 0xffffffff |
| 920 | #define DWC_DEPCMD_MAXp 31 |
| 921 | #define DWC_DEPCMD_POR 0x00000000 |
| 922 | #define DWC_DEPCMD_COMMANDPARAM_BMSK 0xffff0000 |
| 923 | #define DWC_DEPCMD_COMMANDPARAM_SHFT 0x10 |
| 924 | #define DWC_DEPCMD_CMDSTATUS_BMSK 0xf000 |
| 925 | #define DWC_DEPCMD_CMDSTATUS_SHFT 0xc |
| 926 | #define DWC_DEPCMD_HIPRI_FORCERM_BMSK 0x800 |
| 927 | #define DWC_DEPCMD_HIPRI_FORCERM_SHFT 0xb |
| 928 | #define DWC_DEPCMD_CMDACT_BMSK 0x400 |
| 929 | #define DWC_DEPCMD_CMDACT_SHFT 0xa |
| 930 | #define DWC_DEPCMD_R39_BMSK 0x200 |
| 931 | #define DWC_DEPCMD_R39_SHFT 0x9 |
| 932 | #define DWC_DEPCMD_CMDIOC_BMSK 0x100 |
| 933 | #define DWC_DEPCMD_CMDIOC_SHFT 0x8 |
| 934 | #define DWC_DEPCMD_RSVD90_BMSK 0xf0 |
| 935 | #define DWC_DEPCMD_RSVD90_SHFT 0x4 |
| 936 | #define DWC_DEPCMD_CMDTYP_BMSK 0xf |
| 937 | #define DWC_DEPCMD_CMDTYP_SHFT 0x0 |
| 938 | |
| 939 | #define DWC_DCFG_ADDR(x) ((x) + 0x0000c700) |
| 940 | #define DWC_DCFG_OFFS (0x0000c700) |
| 941 | #define DWC_DCFG_RMSK 0xffffffff |
| 942 | #define DWC_DCFG_POR 0x00080804 |
| 943 | #define DWC_DCFG_RSVD9_BMSK 0xff000000 |
| 944 | #define DWC_DCFG_RSVD9_SHFT 0x18 |
| 945 | #define DWC_DCFG_IGNSTRMPP_BMSK 0x800000 |
| 946 | #define DWC_DCFG_IGNSTRMPP_SHFT 0x17 |
| 947 | #define DWC_DCFG_LPMCAP_BMSK 0x400000 |
| 948 | #define DWC_DCFG_LPMCAP_SHFT 0x16 |
| 949 | #define DWC_DCFG_NUMP_BMSK 0x3e0000 |
| 950 | #define DWC_DCFG_NUMP_SHFT 0x11 |
| 951 | #define DWC_DCFG_INTRNUM_BMSK 0x1f000 |
| 952 | #define DWC_DCFG_INTRNUM_SHFT 0xc |
| 953 | #define DWC_DCFG_PERFRINT_BMSK 0xc00 |
| 954 | #define DWC_DCFG_PERFRINT_SHFT 0xa |
| 955 | #define DWC_DCFG_DEVADDR_BMSK 0x3f8 |
| 956 | #define DWC_DCFG_DEVADDR_SHFT 0x3 |
| 957 | #define DWC_DCFG_DEVSPD_BMSK 0x7 |
| 958 | #define DWC_DCFG_DEVSPD_SHFT 0x0 |
| 959 | |
| 960 | #define DWC_DCTL_ADDR(x) ((x) + 0x0000c704) |
| 961 | #define DWC_DCTL_OFFS (0x0000c704) |
| 962 | #define DWC_DCTL_RMSK 0xffffffff |
| 963 | #define DWC_DCTL_POR 0x00000000 |
| 964 | #define DWC_DCTL_RUN_STOP_BMSK 0x80000000 |
| 965 | #define DWC_DCTL_RUN_STOP_SHFT 0x1f |
| 966 | #define DWC_DCTL_CSFTRST_BMSK 0x40000000 |
| 967 | #define DWC_DCTL_CSFTRST_SHFT 0x1e |
| 968 | #define DWC_DCTL_LSFTRST_BMSK 0x20000000 |
| 969 | #define DWC_DCTL_LSFTRST_SHFT 0x1d |
| 970 | #define DWC_DCTL_HIRDTHRES_BMSK 0x1f000000 |
| 971 | #define DWC_DCTL_HIRDTHRES_SHFT 0x18 |
| 972 | #define DWC_DCTL_APPL1RES_BMSK 0x800000 |
| 973 | #define DWC_DCTL_APPL1RES_SHFT 0x17 |
| 974 | #define DWC_DCTL_RSVD40_BMSK 0x700000 |
| 975 | #define DWC_DCTL_RSVD40_SHFT 0x14 |
| 976 | #define DWC_DCTL_HIBERNATIONEN_BMSK 0x80000 |
| 977 | #define DWC_DCTL_HIBERNATIONEN_SHFT 0x13 |
| 978 | #define DWC_DCTL_L1HIBERNATIONEN_BMSK 0x40000 |
| 979 | #define DWC_DCTL_L1HIBERNATIONEN_SHFT 0x12 |
| 980 | #define DWC_DCTL_CRS_BMSK 0x20000 |
| 981 | #define DWC_DCTL_CRS_SHFT 0x11 |
| 982 | #define DWC_DCTL_CSS_BMSK 0x10000 |
| 983 | #define DWC_DCTL_CSS_SHFT 0x10 |
| 984 | #define DWC_DCTL_RSVD41_BMSK 0xe000 |
| 985 | #define DWC_DCTL_RSVD41_SHFT 0xd |
| 986 | #define DWC_DCTL_INITU2ENA_BMSK 0x1000 |
| 987 | #define DWC_DCTL_INITU2ENA_SHFT 0xc |
| 988 | #define DWC_DCTL_ACCEPTU2ENA_BMSK 0x800 |
| 989 | #define DWC_DCTL_ACCEPTU2ENA_SHFT 0xb |
| 990 | #define DWC_DCTL_INITU1ENA_BMSK 0x400 |
| 991 | #define DWC_DCTL_INITU1ENA_SHFT 0xa |
| 992 | #define DWC_DCTL_ACCEPTU1ENA_BMSK 0x200 |
| 993 | #define DWC_DCTL_ACCEPTU1ENA_SHFT 0x9 |
| 994 | #define DWC_DCTL_ULSTCHNGREQ_BMSK 0x1e0 |
| 995 | #define DWC_DCTL_ULSTCHNGREQ_SHFT 0x5 |
| 996 | #define DWC_DCTL_TSTCTL_BMSK 0x1e |
| 997 | #define DWC_DCTL_TSTCTL_SHFT 0x1 |
| 998 | #define DWC_DCTL_RSVD0_BMSK 0x1 |
| 999 | #define DWC_DCTL_RSVD0_SHFT 0x0 |
| 1000 | |
| 1001 | #define DWC_DEVTEN_ADDR(x) ((x) + 0x0000c708) |
| 1002 | #define DWC_DEVTEN_OFFS (0x0000c708) |
| 1003 | #define DWC_DEVTEN_RMSK 0xffffffff |
| 1004 | #define DWC_DEVTEN_POR 0x00000000 |
| 1005 | #define DWC_DEVTEN_RSVD2_BMSK 0xffffc000 |
| 1006 | #define DWC_DEVTEN_RSVD2_SHFT 0xe |
| 1007 | #define DWC_DEVTEN_U2INACTTIMOUTRCVDEN_BMSK 0x2000 |
| 1008 | #define DWC_DEVTEN_U2INACTTIMOUTRCVDEN_SHFT 0xd |
| 1009 | #define DWC_DEVTEN_VENDEVTSTRCVDEN_BMSK 0x1000 |
| 1010 | #define DWC_DEVTEN_VENDEVTSTRCVDEN_SHFT 0xc |
| 1011 | #define DWC_DEVTEN_EVNTOVERFLOWEN_BMSK 0x800 |
| 1012 | #define DWC_DEVTEN_EVNTOVERFLOWEN_SHFT 0xb |
| 1013 | #define DWC_DEVTEN_CMDCMPLTEN_BMSK 0x400 |
| 1014 | #define DWC_DEVTEN_CMDCMPLTEN_SHFT 0xa |
| 1015 | #define DWC_DEVTEN_ERRTICERREVTEN_BMSK 0x200 |
| 1016 | #define DWC_DEVTEN_ERRTICERREVTEN_SHFT 0x9 |
| 1017 | #define DWC_DEVTEN_RSVD39_BMSK 0x100 |
| 1018 | #define DWC_DEVTEN_RSVD39_SHFT 0x8 |
| 1019 | #define DWC_DEVTEN_SOFTEVTEN_BMSK 0x80 |
| 1020 | #define DWC_DEVTEN_SOFTEVTEN_SHFT 0x7 |
| 1021 | #define DWC_DEVTEN_EOPFEVTEN_BMSK 0x40 |
| 1022 | #define DWC_DEVTEN_EOPFEVTEN_SHFT 0x6 |
| 1023 | #define DWC_DEVTEN_HIBERNATIONREQEVTEN_BMSK 0x20 |
| 1024 | #define DWC_DEVTEN_HIBERNATIONREQEVTEN_SHFT 0x5 |
| 1025 | #define DWC_DEVTEN_WKUPEVTEN_BMSK 0x10 |
| 1026 | #define DWC_DEVTEN_WKUPEVTEN_SHFT 0x4 |
| 1027 | #define DWC_DEVTEN_ULSTCNGEN_BMSK 0x8 |
| 1028 | #define DWC_DEVTEN_ULSTCNGEN_SHFT 0x3 |
| 1029 | #define DWC_DEVTEN_CONNECTDONEEVTEN_BMSK 0x4 |
| 1030 | #define DWC_DEVTEN_CONNECTDONEEVTEN_SHFT 0x2 |
| 1031 | #define DWC_DEVTEN_USBRSTEVTEN_BMSK 0x2 |
| 1032 | #define DWC_DEVTEN_USBRSTEVTEN_SHFT 0x1 |
| 1033 | #define DWC_DEVTEN_DISSCONNEVTEN_BMSK 0x1 |
| 1034 | #define DWC_DEVTEN_DISSCONNEVTEN_SHFT 0x0 |
| 1035 | |
| 1036 | #define DWC_DSTS_ADDR(x) ((x) + 0x0000c70c) |
| 1037 | #define DWC_DSTS_OFFS (0x0000c70c) |
| 1038 | #define DWC_DSTS_RMSK 0xffffffff |
| 1039 | #define DWC_DSTS_POR 0x20820004 |
| 1040 | #define DWC_DSTS_RSVD4_BMSK 0xc0000000 |
| 1041 | #define DWC_DSTS_RSVD4_SHFT 0x1e |
| 1042 | #define DWC_DSTS_DCNRD_BMSK 0x20000000 |
| 1043 | #define DWC_DSTS_DCNRD_SHFT 0x1d |
| 1044 | #define DWC_DSTS_RSVD3_BMSK 0x10000000 |
| 1045 | #define DWC_DSTS_RSVD3_SHFT 0x1c |
| 1046 | #define DWC_DSTS_PLC_BMSK 0x8000000 |
| 1047 | #define DWC_DSTS_PLC_SHFT 0x1b |
| 1048 | #define DWC_DSTS_CSC_BMSK 0x4000000 |
| 1049 | #define DWC_DSTS_CSC_SHFT 0x1a |
| 1050 | #define DWC_DSTS_RSS_BMSK 0x2000000 |
| 1051 | #define DWC_DSTS_RSS_SHFT 0x19 |
| 1052 | #define DWC_DSTS_SSS_BMSK 0x1000000 |
| 1053 | #define DWC_DSTS_SSS_SHFT 0x18 |
| 1054 | #define DWC_DSTS_COREIDLE_BMSK 0x800000 |
| 1055 | #define DWC_DSTS_COREIDLE_SHFT 0x17 |
| 1056 | #define DWC_DSTS_DEVCTRLHLT_BMSK 0x400000 |
| 1057 | #define DWC_DSTS_DEVCTRLHLT_SHFT 0x16 |
| 1058 | #define DWC_DSTS_USBLNKST_BMSK 0x3c0000 |
| 1059 | #define DWC_DSTS_USBLNKST_SHFT 0x12 |
| 1060 | #define DWC_DSTS_RXFIFOEMPTY_BMSK 0x20000 |
| 1061 | #define DWC_DSTS_RXFIFOEMPTY_SHFT 0x11 |
| 1062 | #define DWC_DSTS_SOFFN_BMSK 0x1fff8 |
| 1063 | #define DWC_DSTS_SOFFN_SHFT 0x3 |
| 1064 | #define DWC_DSTS_CONNECTSPD_BMSK 0x7 |
| 1065 | #define DWC_DSTS_CONNECTSPD_SHFT 0x0 |
| 1066 | |
| 1067 | #define DWC_DGCMDPAR_ADDR(x) ((x) + 0x0000c710) |
| 1068 | #define DWC_DGCMDPAR_OFFS (0x0000c710) |
| 1069 | #define DWC_DGCMDPAR_RMSK 0xffffffff |
| 1070 | #define DWC_DGCMDPAR_POR 0x00000000 |
| 1071 | #define DWC_DGCMDPAR_PARAMETER_BMSK 0xffffffff |
| 1072 | #define DWC_DGCMDPAR_PARAMETER_SHFT 0x0 |
| 1073 | |
| 1074 | #define DWC_DGCMD_ADDR(x) ((x) + 0x0000c714) |
| 1075 | #define DWC_DGCMD_OFFS (0x0000c714) |
| 1076 | #define DWC_DGCMD_RMSK 0xffffffff |
| 1077 | #define DWC_DGCMD_POR 0x00000000 |
| 1078 | #define DWC_DGCMD_RSVD6_BMSK 0xffff0000 |
| 1079 | #define DWC_DGCMD_RSVD6_SHFT 0x10 |
| 1080 | #define DWC_DGCMD_CMDSTATUS_BMSK 0xf000 |
| 1081 | #define DWC_DGCMD_CMDSTATUS_SHFT 0xc |
| 1082 | #define DWC_DGCMD_RSVD5_BMSK 0x800 |
| 1083 | #define DWC_DGCMD_RSVD5_SHFT 0xb |
| 1084 | #define DWC_DGCMD_CMDACT_BMSK 0x400 |
| 1085 | #define DWC_DGCMD_CMDACT_SHFT 0xa |
| 1086 | #define DWC_DGCMD_RSVD4_BMSK 0x200 |
| 1087 | #define DWC_DGCMD_RSVD4_SHFT 0x9 |
| 1088 | #define DWC_DGCMD_CMDIOC_BMSK 0x100 |
| 1089 | #define DWC_DGCMD_CMDIOC_SHFT 0x8 |
| 1090 | #define DWC_DGCMD_CMDTYP_BMSK 0xff |
| 1091 | #define DWC_DGCMD_CMDTYP_SHFT 0x0 |
| 1092 | |
| 1093 | #define DWC_DALEPENA_ADDR(x) ((x) + 0x0000c720) |
| 1094 | #define DWC_DALEPENA_OFFS (0x0000c720) |
| 1095 | #define DWC_DALEPENA_RMSK 0xffffffff |
| 1096 | #define DWC_DALEPENA_POR 0x00000000 |
| 1097 | #define DWC_DALEPENA_USBACTEP_BMSK 0xffffffff |
| 1098 | #define DWC_DALEPENA_USBACTEP_SHFT 0x0 |
| 1099 | |
| 1100 | #define DWC_OCFG_ADDR(x) ((x) + 0x0000cc00) |
| 1101 | #define DWC_OCFG_OFFS (0x0000cc00) |
| 1102 | #define DWC_OCFG_RMSK 0xffffffff |
| 1103 | #define DWC_OCFG_POR 0x00000000 |
| 1104 | #define DWC_OCFG_RSVD0_BMSK 0xffffffc0 |
| 1105 | #define DWC_OCFG_RSVD0_SHFT 0x6 |
| 1106 | #define DWC_OCFG_DISPRTPWRCUTOFF_BMSK 0x20 |
| 1107 | #define DWC_OCFG_DISPRTPWRCUTOFF_SHFT 0x5 |
| 1108 | #define DWC_OCFG_OTGHIBDISMASK_BMSK 0x10 |
| 1109 | #define DWC_OCFG_OTGHIBDISMASK_SHFT 0x4 |
| 1110 | #define DWC_OCFG_OTGSFTRSTMSK_BMSK 0x8 |
| 1111 | #define DWC_OCFG_OTGSFTRSTMSK_SHFT 0x3 |
| 1112 | #define DWC_OCFG_OTG_VERSION_BMSK 0x4 |
| 1113 | #define DWC_OCFG_OTG_VERSION_SHFT 0x2 |
| 1114 | #define DWC_OCFG_HNPCAP_BMSK 0x2 |
| 1115 | #define DWC_OCFG_HNPCAP_SHFT 0x1 |
| 1116 | #define DWC_OCFG_SRPCAP_BMSK 0x1 |
| 1117 | #define DWC_OCFG_SRPCAP_SHFT 0x0 |
| 1118 | |
| 1119 | #define DWC_OCTL_ADDR(x) ((x) + 0x0000cc04) |
| 1120 | #define DWC_OCTL_OFFS (0x0000cc04) |
| 1121 | #define DWC_OCTL_RMSK 0xffffffff |
| 1122 | #define DWC_OCTL_POR 0x00000040 |
| 1123 | #define DWC_OCTL_RSVD0_BMSK 0xffffff00 |
| 1124 | #define DWC_OCTL_RSVD0_SHFT 0x8 |
| 1125 | #define DWC_OCTL_OTG3_GOERR_BMSK 0x80 |
| 1126 | #define DWC_OCTL_OTG3_GOERR_SHFT 0x7 |
| 1127 | #define DWC_OCTL_PERIMODE_BMSK 0x40 |
| 1128 | #define DWC_OCTL_PERIMODE_SHFT 0x6 |
| 1129 | #define DWC_OCTL_PRTPWRCTL_BMSK 0x20 |
| 1130 | #define DWC_OCTL_PRTPWRCTL_SHFT 0x5 |
| 1131 | #define DWC_OCTL_HNPREQ_BMSK 0x10 |
| 1132 | #define DWC_OCTL_HNPREQ_SHFT 0x4 |
| 1133 | #define DWC_OCTL_SESREQ_BMSK 0x8 |
| 1134 | #define DWC_OCTL_SESREQ_SHFT 0x3 |
| 1135 | #define DWC_OCTL_TERMSELDLPULSE_BMSK 0x4 |
| 1136 | #define DWC_OCTL_TERMSELDLPULSE_SHFT 0x2 |
| 1137 | #define DWC_OCTL_DEVSETHNPEN_BMSK 0x2 |
| 1138 | #define DWC_OCTL_DEVSETHNPEN_SHFT 0x1 |
| 1139 | #define DWC_OCTL_HSTSETHNPEN_BMSK 0x1 |
| 1140 | #define DWC_OCTL_HSTSETHNPEN_SHFT 0x0 |
| 1141 | |
| 1142 | #define DWC_OEVT_ADDR(x) ((x) + 0x0000cc08) |
| 1143 | #define DWC_OEVT_OFFS (0x0000cc08) |
| 1144 | #define DWC_OEVT_RMSK 0xffffffff |
| 1145 | #define DWC_OEVT_POR 0x00000000 |
| 1146 | #define DWC_OEVT_DEVICEMODE_BMSK 0x80000000 |
| 1147 | #define DWC_OEVT_DEVICEMODE_SHFT 0x1f |
| 1148 | #define DWC_OEVT_RSVD0_BMSK 0x70000000 |
| 1149 | #define DWC_OEVT_RSVD0_SHFT 0x1c |
| 1150 | #define DWC_OEVT_OTGXHCIRUNSTPSETEVNT_BMSK 0x8000000 |
| 1151 | #define DWC_OEVT_OTGXHCIRUNSTPSETEVNT_SHFT 0x1b |
| 1152 | #define DWC_OEVT_OTGDEVRUNSTPSETEVNT_BMSK 0x4000000 |
| 1153 | #define DWC_OEVT_OTGDEVRUNSTPSETEVNT_SHFT 0x1a |
| 1154 | #define DWC_OEVT_OTGHIBENTRYEVNT_BMSK 0x2000000 |
| 1155 | #define DWC_OEVT_OTGHIBENTRYEVNT_SHFT 0x19 |
| 1156 | #define DWC_OEVT_OTGCONIDSTSCHNGEVNT_BMSK 0x1000000 |
| 1157 | #define DWC_OEVT_OTGCONIDSTSCHNGEVNT_SHFT 0x18 |
| 1158 | #define DWC_OEVT_HRRCONFNOTIFEVNT_BMSK 0x800000 |
| 1159 | #define DWC_OEVT_HRRCONFNOTIFEVNT_SHFT 0x17 |
| 1160 | #define DWC_OEVT_HRRINITNOTIFEVNT_BMSK 0x400000 |
| 1161 | #define DWC_OEVT_HRRINITNOTIFEVNT_SHFT 0x16 |
| 1162 | #define DWC_OEVT_OTGADEVIDLEEVNT_BMSK 0x200000 |
| 1163 | #define DWC_OEVT_OTGADEVIDLEEVNT_SHFT 0x15 |
| 1164 | #define DWC_OEVT_OTGADEVBHOSTENDEVNT_BMSK 0x100000 |
| 1165 | #define DWC_OEVT_OTGADEVBHOSTENDEVNT_SHFT 0x14 |
| 1166 | #define DWC_OEVT_OTGADEVHOSTEVNT_BMSK 0x80000 |
| 1167 | #define DWC_OEVT_OTGADEVHOSTEVNT_SHFT 0x13 |
| 1168 | #define DWC_OEVT_OTGADEVHNPCHNGEVNT_BMSK 0x40000 |
| 1169 | #define DWC_OEVT_OTGADEVHNPCHNGEVNT_SHFT 0x12 |
| 1170 | #define DWC_OEVT_OTGADEVSRPDETEVNT_BMSK 0x20000 |
| 1171 | #define DWC_OEVT_OTGADEVSRPDETEVNT_SHFT 0x11 |
| 1172 | #define DWC_OEVT_OTGADEVSESSENDDETEVNT_BMSK 0x10000 |
| 1173 | #define DWC_OEVT_OTGADEVSESSENDDETEVNT_SHFT 0x10 |
| 1174 | #define DWC_OEVT_RSVD2_BMSK 0xf000 |
| 1175 | #define DWC_OEVT_RSVD2_SHFT 0xc |
| 1176 | #define DWC_OEVT_OTGBDEVBHOSTENDEVNT_BMSK 0x800 |
| 1177 | #define DWC_OEVT_OTGBDEVBHOSTENDEVNT_SHFT 0xb |
| 1178 | #define DWC_OEVT_OTGBDEVHNPCHNGEVNT_BMSK 0x400 |
| 1179 | #define DWC_OEVT_OTGBDEVHNPCHNGEVNT_SHFT 0xa |
| 1180 | #define DWC_OEVT_OTGBDEVSESSVLDDETEVNT_BMSK 0x200 |
| 1181 | #define DWC_OEVT_OTGBDEVSESSVLDDETEVNT_SHFT 0x9 |
| 1182 | #define DWC_OEVT_OTGBDEVVBUSCHNGEVNT_BMSK 0x100 |
| 1183 | #define DWC_OEVT_OTGBDEVVBUSCHNGEVNT_SHFT 0x8 |
| 1184 | #define DWC_OEVT_RSVD3_BMSK 0xf0 |
| 1185 | #define DWC_OEVT_RSVD3_SHFT 0x4 |
| 1186 | #define DWC_OEVT_BSESVLD_BMSK 0x8 |
| 1187 | #define DWC_OEVT_BSESVLD_SHFT 0x3 |
| 1188 | #define DWC_OEVT_HSTNEGSTS_BMSK 0x4 |
| 1189 | #define DWC_OEVT_HSTNEGSTS_SHFT 0x2 |
| 1190 | #define DWC_OEVT_SESREQSTS_BMSK 0x2 |
| 1191 | #define DWC_OEVT_SESREQSTS_SHFT 0x1 |
| 1192 | #define DWC_OEVT_OEVTERROR_BMSK 0x1 |
| 1193 | #define DWC_OEVT_OEVTERROR_SHFT 0x0 |
| 1194 | |
| 1195 | #define DWC_OEVTEN_ADDR(x) ((x) + 0x0000cc0c) |
| 1196 | #define DWC_OEVTEN_OFFS (0x0000cc0c) |
| 1197 | #define DWC_OEVTEN_RMSK 0xffffffff |
| 1198 | #define DWC_OEVTEN_POR 0x00000000 |
| 1199 | #define DWC_OEVTEN_RSVD0_BMSK 0xf0000000 |
| 1200 | #define DWC_OEVTEN_RSVD0_SHFT 0x1c |
| 1201 | #define DWC_OEVTEN_OTGXHCIRUNSTPSETEVNTEN_BMSK 0x8000000 |
| 1202 | #define DWC_OEVTEN_OTGXHCIRUNSTPSETEVNTEN_SHFT 0x1b |
| 1203 | #define DWC_OEVTEN_OTGDEVRUNSTPSETEVNTEN_BMSK 0x4000000 |
| 1204 | #define DWC_OEVTEN_OTGDEVRUNSTPSETEVNTEN_SHFT 0x1a |
| 1205 | #define DWC_OEVTEN_OTGHIBENTRYEVNTEN_BMSK 0x2000000 |
| 1206 | #define DWC_OEVTEN_OTGHIBENTRYEVNTEN_SHFT 0x19 |
| 1207 | #define DWC_OEVTEN_OTGCONIDSTSCHNGEVNTEN_BMSK 0x1000000 |
| 1208 | #define DWC_OEVTEN_OTGCONIDSTSCHNGEVNTEN_SHFT 0x18 |
| 1209 | #define DWC_OEVTEN_HRRCONFNOTIFEVNTEN_BMSK 0x800000 |
| 1210 | #define DWC_OEVTEN_HRRCONFNOTIFEVNTEN_SHFT 0x17 |
| 1211 | #define DWC_OEVTEN_HRRINITNOTIFEVNTEN_BMSK 0x400000 |
| 1212 | #define DWC_OEVTEN_HRRINITNOTIFEVNTEN_SHFT 0x16 |
| 1213 | #define DWC_OEVTEN_OTGADEVIDLEEVNTEN_BMSK 0x200000 |
| 1214 | #define DWC_OEVTEN_OTGADEVIDLEEVNTEN_SHFT 0x15 |
| 1215 | #define DWC_OEVTEN_OTGADEVBHOSTENDEVNTEN_BMSK 0x100000 |
| 1216 | #define DWC_OEVTEN_OTGADEVBHOSTENDEVNTEN_SHFT 0x14 |
| 1217 | #define DWC_OEVTEN_OTGADEVHOSTEVNTEN_BMSK 0x80000 |
| 1218 | #define DWC_OEVTEN_OTGADEVHOSTEVNTEN_SHFT 0x13 |
| 1219 | #define DWC_OEVTEN_OTGADEVHNPCHNGEVNTEN_BMSK 0x40000 |
| 1220 | #define DWC_OEVTEN_OTGADEVHNPCHNGEVNTEN_SHFT 0x12 |
| 1221 | #define DWC_OEVTEN_OTGADEVSRPDETEVNTEN_BMSK 0x20000 |
| 1222 | #define DWC_OEVTEN_OTGADEVSRPDETEVNTEN_SHFT 0x11 |
| 1223 | #define DWC_OEVTEN_OTGADEVSESSENDDETEVNTEN_BMSK 0x10000 |
| 1224 | #define DWC_OEVTEN_OTGADEVSESSENDDETEVNTEN_SHFT 0x10 |
| 1225 | #define DWC_OEVTEN_RSVD2_BMSK 0xf000 |
| 1226 | #define DWC_OEVTEN_RSVD2_SHFT 0xc |
| 1227 | #define DWC_OEVTEN_OTGBDEVBHOSTENDEVNTEN_BMSK 0x800 |
| 1228 | #define DWC_OEVTEN_OTGBDEVBHOSTENDEVNTEN_SHFT 0xb |
| 1229 | #define DWC_OEVTEN_OTGBDEVHNPCHNGEVNTEN_BMSK 0x400 |
| 1230 | #define DWC_OEVTEN_OTGBDEVHNPCHNGEVNTEN_SHFT 0xa |
| 1231 | #define DWC_OEVTEN_OTGBDEVSESSVLDDETEVNTEN_BMSK 0x200 |
| 1232 | #define DWC_OEVTEN_OTGBDEVSESSVLDDETEVNTEN_SHFT 0x9 |
| 1233 | #define DWC_OEVTEN_OTGBDEVVBUSCHNGEVNTEN_BMSK 0x100 |
| 1234 | #define DWC_OEVTEN_OTGBDEVVBUSCHNGEVNTEN_SHFT 0x8 |
| 1235 | #define DWC_OEVTEN_RSVD3_BMSK 0xff |
| 1236 | #define DWC_OEVTEN_RSVD3_SHFT 0x0 |
| 1237 | |
| 1238 | #define DWC_OSTS_ADDR(x) ((x) + 0x0000cc10) |
| 1239 | #define DWC_OSTS_OFFS (0x0000cc10) |
| 1240 | #define DWC_OSTS_RMSK 0xffffffff |
| 1241 | #define DWC_OSTS_POR 0x00000819 |
| 1242 | #define DWC_OSTS_RSVD0_BMSK 0xffffc000 |
| 1243 | #define DWC_OSTS_RSVD0_SHFT 0xe |
| 1244 | #define DWC_OSTS_DEVRUNSTP_BMSK 0x2000 |
| 1245 | #define DWC_OSTS_DEVRUNSTP_SHFT 0xd |
| 1246 | #define DWC_OSTS_XHCIRUNSTP_BMSK 0x1000 |
| 1247 | #define DWC_OSTS_XHCIRUNSTP_SHFT 0xc |
| 1248 | #define DWC_OSTS_OTGSTATE_BMSK 0xf00 |
| 1249 | #define DWC_OSTS_OTGSTATE_SHFT 0x8 |
| 1250 | #define DWC_OSTS_RSVD1_BMSK 0xe0 |
| 1251 | #define DWC_OSTS_RSVD1_SHFT 0x5 |
| 1252 | #define DWC_OSTS_PERIPHERALSTATE_BMSK 0x10 |
| 1253 | #define DWC_OSTS_PERIPHERALSTATE_SHFT 0x4 |
| 1254 | #define DWC_OSTS_XHCIPRTPOWER_BMSK 0x8 |
| 1255 | #define DWC_OSTS_XHCIPRTPOWER_SHFT 0x3 |
| 1256 | #define DWC_OSTS_BSESVLD_BMSK 0x4 |
| 1257 | #define DWC_OSTS_BSESVLD_SHFT 0x2 |
| 1258 | #define DWC_OSTS_ASESVLD_BMSK 0x2 |
| 1259 | #define DWC_OSTS_ASESVLD_SHFT 0x1 |
| 1260 | #define DWC_OSTS_CONIDSTS_BMSK 0x1 |
| 1261 | #define DWC_OSTS_CONIDSTS_SHFT 0x0 |
| 1262 | |
| 1263 | #define DWC_ADPCFG_ADDR(x) ((x) + 0x0000cc20) |
| 1264 | #define DWC_ADPCFG_OFFS (0x0000cc20) |
| 1265 | #define DWC_ADPCFG_RMSK 0xffffffff |
| 1266 | #define DWC_ADPCFG_POR 0x00000000 |
| 1267 | #define DWC_ADPCFG_PRBPER_BMSK 0xc0000000 |
| 1268 | #define DWC_ADPCFG_PRBPER_SHFT 0x1e |
| 1269 | #define DWC_ADPCFG_PRBDELTA_BMSK 0x30000000 |
| 1270 | #define DWC_ADPCFG_PRBDELTA_SHFT 0x1c |
| 1271 | #define DWC_ADPCFG_PRBDSCHG_BMSK 0xc000000 |
| 1272 | #define DWC_ADPCFG_PRBDSCHG_SHFT 0x1a |
| 1273 | #define DWC_ADPCFG_RSVD0_BMSK 0x3ffffff |
| 1274 | #define DWC_ADPCFG_RSVD0_SHFT 0x0 |
| 1275 | |
| 1276 | #define DWC_ADPCTL_ADDR(x) ((x) + 0x0000cc24) |
| 1277 | #define DWC_ADPCTL_OFFS (0x0000cc24) |
| 1278 | #define DWC_ADPCTL_RMSK 0xffffffff |
| 1279 | #define DWC_ADPCTL_POR 0x00000000 |
| 1280 | #define DWC_ADPCTL_RSVD0_BMSK 0xe0000000 |
| 1281 | #define DWC_ADPCTL_RSVD0_SHFT 0x1d |
| 1282 | #define DWC_ADPCTL_ENAPRB_BMSK 0x10000000 |
| 1283 | #define DWC_ADPCTL_ENAPRB_SHFT 0x1c |
| 1284 | #define DWC_ADPCTL_ENASNS_BMSK 0x8000000 |
| 1285 | #define DWC_ADPCTL_ENASNS_SHFT 0x1b |
| 1286 | #define DWC_ADPCTL_ADPEN_BMSK 0x4000000 |
| 1287 | #define DWC_ADPCTL_ADPEN_SHFT 0x1a |
| 1288 | #define DWC_ADPCTL_ADPRES_BMSK 0x2000000 |
| 1289 | #define DWC_ADPCTL_ADPRES_SHFT 0x19 |
| 1290 | #define DWC_ADPCTL_WB_BMSK 0x1000000 |
| 1291 | #define DWC_ADPCTL_WB_SHFT 0x18 |
| 1292 | #define DWC_ADPCTL_RSVD1_BMSK 0xffffff |
| 1293 | #define DWC_ADPCTL_RSVD1_SHFT 0x0 |
| 1294 | |
| 1295 | #define DWC_ADPEVT_ADDR(x) ((x) + 0x0000cc28) |
| 1296 | #define DWC_ADPEVT_OFFS (0x0000cc28) |
| 1297 | #define DWC_ADPEVT_RMSK 0xffffffff |
| 1298 | #define DWC_ADPEVT_POR 0x00000000 |
| 1299 | #define DWC_ADPEVT_RSVD0_BMSK 0xe0000000 |
| 1300 | #define DWC_ADPEVT_RSVD0_SHFT 0x1d |
| 1301 | #define DWC_ADPEVT_ADPPRBEVNT_BMSK 0x10000000 |
| 1302 | #define DWC_ADPEVT_ADPPRBEVNT_SHFT 0x1c |
| 1303 | #define DWC_ADPEVT_ADPSNSEVNT_BMSK 0x8000000 |
| 1304 | #define DWC_ADPEVT_ADPSNSEVNT_SHFT 0x1b |
| 1305 | #define DWC_ADPEVT_ADPTMOUTEVNT_BMSK 0x4000000 |
| 1306 | #define DWC_ADPEVT_ADPTMOUTEVNT_SHFT 0x1a |
| 1307 | #define DWC_ADPEVT_ADPRSTCMPLTEVNT_BMSK 0x2000000 |
| 1308 | #define DWC_ADPEVT_ADPRSTCMPLTEVNT_SHFT 0x19 |
| 1309 | #define DWC_ADPEVT_RSVD1_BMSK 0x1fff800 |
| 1310 | #define DWC_ADPEVT_RSVD1_SHFT 0xb |
| 1311 | #define DWC_ADPEVT_RTIM_BMSK 0x7ff |
| 1312 | #define DWC_ADPEVT_RTIM_SHFT 0x0 |
| 1313 | |
| 1314 | #define DWC_ADPEVTEN_ADDR(x) ((x) + 0x0000cc2c) |
| 1315 | #define DWC_ADPEVTEN_OFFS (0x0000cc2c) |
| 1316 | #define DWC_ADPEVTEN_RMSK 0xffffffff |
| 1317 | #define DWC_ADPEVTEN_POR 0x00000000 |
| 1318 | #define DWC_ADPEVTEN_RSVD0_BMSK 0xe0000000 |
| 1319 | #define DWC_ADPEVTEN_RSVD0_SHFT 0x1d |
| 1320 | #define DWC_ADPEVTEN_ADPPRBEVNTEN_BMSK 0x10000000 |
| 1321 | #define DWC_ADPEVTEN_ADPPRBEVNTEN_SHFT 0x1c |
| 1322 | #define DWC_ADPEVTEN_ADPSNSEVNTEN_BMSK 0x8000000 |
| 1323 | #define DWC_ADPEVTEN_ADPSNSEVNTEN_SHFT 0x1b |
| 1324 | #define DWC_ADPEVTEN_ADPTMOUTEVNTEN_BMSK 0x4000000 |
| 1325 | #define DWC_ADPEVTEN_ADPTMOUTEVNTEN_SHFT 0x1a |
| 1326 | #define DWC_ADPEVTEN_ADPRSTCMPLTEVNTEN_BMSK 0x2000000 |
| 1327 | #define DWC_ADPEVTEN_ADPRSTCMPLTEVNTEN_SHFT 0x19 |
| 1328 | #define DWC_ADPEVTEN_RSVD1_BMSK 0x1ffffff |
| 1329 | #define DWC_ADPEVTEN_RSVD1_SHFT 0x0 |
| 1330 | |
| 1331 | /*---------------------------------------------------------------------------- |
| 1332 | * MODULE: USB30_QSCRATCH |
| 1333 | *--------------------------------------------------------------------------*/ |
| 1334 | #define USB30_QSCRATCH_REG_BASE_OFFS 0x000f8800 |
| 1335 | #define DWC_HS_PHY_CTRL_ADDR(x) ((x) + 0x00000010) |
| 1336 | #define DWC_HS_PHY_CTRL_OFFS (0x00000010) |
| 1337 | #define DWC_HS_PHY_CTRL_RMSK 0x7ffffff |
| 1338 | #define DWC_HS_PHY_CTRL_POR 0x072203b2 |
| 1339 | #define DWC_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_BMSK 0x4000000 |
| 1340 | #define DWC_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_SHFT 0x1a |
| 1341 | #define DWC_HS_PHY_CTRL_FREECLK_SEL_BMSK 0x2000000 |
| 1342 | #define DWC_HS_PHY_CTRL_FREECLK_SEL_SHFT 0x19 |
| 1343 | #define DWC_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_BMSK 0x1000000 |
| 1344 | #define DWC_HS_PHY_CTRL_DMSEHV_CLAMP_EN_N_SHFT 0x18 |
| 1345 | #define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_BMSK 0x800000 |
| 1346 | #define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SEL_SHFT 0x17 |
| 1347 | #define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_BMSK 0x400000 |
| 1348 | #define DWC_HS_PHY_CTRL_USB2_SUSPEND_N_SHFT 0x16 |
| 1349 | #define DWC_HS_PHY_CTRL_USB2_UTMI_CLK_EN_BMSK 0x200000 |
| 1350 | #define DWC_HS_PHY_CTRL_USB2_UTMI_CLK_EN_SHFT 0x15 |
| 1351 | #define DWC_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_BMSK 0x100000 |
| 1352 | #define DWC_HS_PHY_CTRL_UTMI_OTG_VBUS_VALID_SHFT 0x14 |
| 1353 | #define DWC_HS_PHY_CTRL_AUTORESUME_BMSK 0x80000 |
| 1354 | #define DWC_HS_PHY_CTRL_AUTORESUME_SHFT 0x13 |
| 1355 | #define DWC_HS_PHY_CTRL_USE_CLKCORE_BMSK 0x40000 |
| 1356 | #define DWC_HS_PHY_CTRL_USE_CLKCORE_SHFT 0x12 |
| 1357 | #define DWC_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_BMSK 0x20000 |
| 1358 | #define DWC_HS_PHY_CTRL_DPSEHV_CLAMP_EN_N_SHFT 0x11 |
| 1359 | #define DWC_HS_PHY_CTRL_IDHV_INTEN_BMSK 0x10000 |
| 1360 | #define DWC_HS_PHY_CTRL_IDHV_INTEN_SHFT 0x10 |
| 1361 | #define DWC_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_BMSK 0x8000 |
| 1362 | #define DWC_HS_PHY_CTRL_OTGSESSVLDHV_INTEN_SHFT 0xf |
| 1363 | #define DWC_HS_PHY_CTRL_VBUSVLDEXTSEL0_BMSK 0x4000 |
| 1364 | #define DWC_HS_PHY_CTRL_VBUSVLDEXTSEL0_SHFT 0xe |
| 1365 | #define DWC_HS_PHY_CTRL_VBUSVLDEXT0_BMSK 0x2000 |
| 1366 | #define DWC_HS_PHY_CTRL_VBUSVLDEXT0_SHFT 0xd |
| 1367 | #define DWC_HS_PHY_CTRL_OTGDISABLE0_BMSK 0x1000 |
| 1368 | #define DWC_HS_PHY_CTRL_OTGDISABLE0_SHFT 0xc |
| 1369 | #define DWC_HS_PHY_CTRL_COMMONONN_BMSK 0x800 |
| 1370 | #define DWC_HS_PHY_CTRL_COMMONONN_SHFT 0xb |
| 1371 | #define DWC_HS_PHY_CTRL_ULPIPOR_BMSK 0x400 |
| 1372 | #define DWC_HS_PHY_CTRL_ULPIPOR_SHFT 0xa |
| 1373 | #define DWC_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_BMSK 0x200 |
| 1374 | #define DWC_HS_PHY_CTRL_ID_HV_CLAMP_EN_N_SHFT 0x9 |
| 1375 | #define DWC_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_BMSK 0x100 |
| 1376 | #define DWC_HS_PHY_CTRL_OTGSESSVLD_HV_CLAMP_EN_N_SHFT 0x8 |
| 1377 | #define DWC_HS_PHY_CTRL_CLAMP_EN_N_BMSK 0x80 |
| 1378 | #define DWC_HS_PHY_CTRL_CLAMP_EN_N_SHFT 0x7 |
| 1379 | #define DWC_HS_PHY_CTRL_FSEL_BMSK 0x70 |
| 1380 | #define DWC_HS_PHY_CTRL_FSEL_SHFT 0x4 |
| 1381 | #define DWC_HS_PHY_CTRL_REFCLKOUT_EN_BMSK 0x8 |
| 1382 | #define DWC_HS_PHY_CTRL_REFCLKOUT_EN_SHFT 0x3 |
| 1383 | #define DWC_HS_PHY_CTRL_SIDDQ_BMSK 0x4 |
| 1384 | #define DWC_HS_PHY_CTRL_SIDDQ_SHFT 0x2 |
| 1385 | #define DWC_HS_PHY_CTRL_RETENABLEN_BMSK 0x2 |
| 1386 | #define DWC_HS_PHY_CTRL_RETENABLEN_SHFT 0x1 |
| 1387 | #define DWC_HS_PHY_CTRL_POR_BMSK 0x1 |
| 1388 | #define DWC_HS_PHY_CTRL_POR_SHFT 0x0 |
| 1389 | |
| 1390 | #define DWC_CHARGING_DET_CTRL_ADDR(x) ((x) + 0x00000018) |
| 1391 | #define DWC_CHARGING_DET_CTRL_PHYS(x) ((x) + 0x00000018) |
| 1392 | #define DWC_CHARGING_DET_CTRL_OFFS (0x00000018) |
| 1393 | #define DWC_CHARGING_DET_CTRL_RMSK 0x3f |
| 1394 | #define DWC_CHARGING_DET_CTRL_POR 0x00000000 |
| 1395 | #define DWC_CHARGING_DET_CTRL_VDATDETENB0_BMSK 0x20 |
| 1396 | #define DWC_CHARGING_DET_CTRL_VDATDETENB0_SHFT 0x5 |
| 1397 | #define DWC_CHARGING_DET_CTRL_VDATSRCENB0_BMSK 0x10 |
| 1398 | #define DWC_CHARGING_DET_CTRL_VDATSRCENB0_SHFT 0x4 |
| 1399 | #define DWC_CHARGING_DET_CTRL_VDMSRCAUTO_BMSK 0x8 |
| 1400 | #define DWC_CHARGING_DET_CTRL_VDMSRCAUTO_SHFT 0x3 |
| 1401 | #define DWC_CHARGING_DET_CTRL_CHRGSEL0_BMSK 0x4 |
| 1402 | #define DWC_CHARGING_DET_CTRL_CHRGSEL0_SHFT 0x2 |
| 1403 | #define DWC_CHARGING_DET_CTRL_DCDENB0_BMSK 0x2 |
| 1404 | #define DWC_CHARGING_DET_CTRL_DCDENB0_SHFT 0x1 |
| 1405 | #define DWC_CHARGING_DET_CTRL_ACAENB0_BMSK 0x1 |
| 1406 | #define DWC_CHARGING_DET_CTRL_ACAENB0_SHFT 0x0 |
| 1407 | |
| 1408 | #define DWC_CHARGING_DET_OUTPUT_ADDR(x) ((x) + 0x0000001c) |
| 1409 | #define DWC_CHARGING_DET_OUTPUT_PHYS(x) ((x) + 0x0000001c) |
| 1410 | #define DWC_CHARGING_DET_OUTPUT_OFFS (0x0000001c) |
| 1411 | #define DWC_CHARGING_DET_OUTPUT_RMSK 0xfff |
| 1412 | #define DWC_CHARGING_DET_OUTPUT_POR 0x00000000 |
| 1413 | #define DWC_CHARGING_DET_OUTPUT_DMSEHV_BMSK 0x800 |
| 1414 | #define DWC_CHARGING_DET_OUTPUT_DMSEHV_SHFT 0xb |
| 1415 | #define DWC_CHARGING_DET_OUTPUT_DPSEHV_BMSK 0x400 |
| 1416 | #define DWC_CHARGING_DET_OUTPUT_DPSEHV_SHFT 0xa |
| 1417 | #define DWC_CHARGING_DET_OUTPUT_LINESTATE_BMSK 0x300 |
| 1418 | #define DWC_CHARGING_DET_OUTPUT_LINESTATE_SHFT 0x8 |
| 1419 | #define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_N_BMSK 0x80 |
| 1420 | #define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_N_SHFT 0x7 |
| 1421 | #define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_BMSK 0x40 |
| 1422 | #define DWC_CHARGING_DET_OUTPUT_RIDFLOAT_SHFT 0x6 |
| 1423 | #define DWC_CHARGING_DET_OUTPUT_RIDGND_BMSK 0x20 |
| 1424 | #define DWC_CHARGING_DET_OUTPUT_RIDGND_SHFT 0x5 |
| 1425 | #define DWC_CHARGING_DET_OUTPUT_RIDC_BMSK 0x10 |
| 1426 | #define DWC_CHARGING_DET_OUTPUT_RIDC_SHFT 0x4 |
| 1427 | #define DWC_CHARGING_DET_OUTPUT_RIDB_BMSK 0x8 |
| 1428 | #define DWC_CHARGING_DET_OUTPUT_RIDB_SHFT 0x3 |
| 1429 | #define DWC_CHARGING_DET_OUTPUT_RIDA_BMSK 0x4 |
| 1430 | #define DWC_CHARGING_DET_OUTPUT_RIDA_SHFT 0x2 |
| 1431 | #define DWC_CHARGING_DET_OUTPUT_DCDOUT_BMSK 0x2 |
| 1432 | #define DWC_CHARGING_DET_OUTPUT_DCDOUT_SHFT 0x1 |
| 1433 | #define DWC_CHARGING_DET_OUTPUT_CHGDET_BMSK 0x1 |
| 1434 | #define DWC_CHARGING_DET_OUTPUT_CHGDET_SHFT 0x0 |
| 1435 | |
| 1436 | #define DWC_ALT_INTERRUPT_EN_ADDR(x) ((x) + 0x00000020) |
| 1437 | #define DWC_ALT_INTERRUPT_EN_PHYS(x) ((x) + 0x00000020) |
| 1438 | #define DWC_ALT_INTERRUPT_EN_OFFS (0x00000020) |
| 1439 | #define DWC_ALT_INTERRUPT_EN_RMSK 0xfff |
| 1440 | #define DWC_ALT_INTERRUPT_EN_POR 0x00000000 |
| 1441 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_BMSK 0x800 |
| 1442 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_LO_INTEN_SHFT 0xb |
| 1443 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_BMSK 0x400 |
| 1444 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_HI_INTEN_SHFT 0xa |
| 1445 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_BMSK 0x200 |
| 1446 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_LO_INTEN_SHFT 0x9 |
| 1447 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_BMSK 0x100 |
| 1448 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_HI_INTEN_SHFT 0x8 |
| 1449 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_INTEN_BMSK 0x80 |
| 1450 | #define DWC_ALT_INTERRUPT_EN_DMSEHV_INTEN_SHFT 0x7 |
| 1451 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_INTEN_BMSK 0x40 |
| 1452 | #define DWC_ALT_INTERRUPT_EN_DPSEHV_INTEN_SHFT 0x6 |
| 1453 | #define DWC_ALT_INTERRUPT_EN_RIDFLOATNINTEN_BMSK 0x20 |
| 1454 | #define DWC_ALT_INTERRUPT_EN_RIDFLOATNINTEN_SHFT 0x5 |
| 1455 | #define DWC_ALT_INTERRUPT_EN_CHGDETINTEN_BMSK 0x10 |
| 1456 | #define DWC_ALT_INTERRUPT_EN_CHGDETINTEN_SHFT 0x4 |
| 1457 | #define DWC_ALT_INTERRUPT_EN_DPINTEN_BMSK 0x8 |
| 1458 | #define DWC_ALT_INTERRUPT_EN_DPINTEN_SHFT 0x3 |
| 1459 | #define DWC_ALT_INTERRUPT_EN_DCDINTEN_BMSK 0x4 |
| 1460 | #define DWC_ALT_INTERRUPT_EN_DCDINTEN_SHFT 0x2 |
| 1461 | #define DWC_ALT_INTERRUPT_EN_DMINTEN_BMSK 0x2 |
| 1462 | #define DWC_ALT_INTERRUPT_EN_DMINTEN_SHFT 0x1 |
| 1463 | #define DWC_ALT_INTERRUPT_EN_ACAINTEN_BMSK 0x1 |
| 1464 | #define DWC_ALT_INTERRUPT_EN_ACAINTEN_SHFT 0x0 |
| 1465 | |
| 1466 | #define DWC_HS_PHY_IRQ_STAT_ADDR(x) ((x) + 0x00000024) |
| 1467 | #define DWC_HS_PHY_IRQ_STAT_PHYS(x) ((x) + 0x00000024) |
| 1468 | #define DWC_HS_PHY_IRQ_STAT_OFFS (0x00000024) |
| 1469 | #define DWC_HS_PHY_IRQ_STAT_RMSK 0xfff |
| 1470 | #define DWC_HS_PHY_IRQ_STAT_POR 0x00000000 |
| 1471 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_BMSK 0x800 |
| 1472 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_LO_INTLCH_SHFT 0xb |
| 1473 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_BMSK 0x400 |
| 1474 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_HI_INTLCH_SHFT 0xa |
| 1475 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_BMSK 0x200 |
| 1476 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_LO_INTLCH_SHFT 0x9 |
| 1477 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_BMSK 0x100 |
| 1478 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_HI_INTLCH_SHFT 0x8 |
| 1479 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_BMSK 0x80 |
| 1480 | #define DWC_HS_PHY_IRQ_STAT_DMSEHV_INTLCH_SHFT 0x7 |
| 1481 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_BMSK 0x40 |
| 1482 | #define DWC_HS_PHY_IRQ_STAT_DPSEHV_INTLCH_SHFT 0x6 |
| 1483 | #define DWC_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_BMSK 0x20 |
| 1484 | #define DWC_HS_PHY_IRQ_STAT_RIDFLOATNINTLCH_SHFT 0x5 |
| 1485 | #define DWC_HS_PHY_IRQ_STAT_CHGDETINTLCH_BMSK 0x10 |
| 1486 | #define DWC_HS_PHY_IRQ_STAT_CHGDETINTLCH_SHFT 0x4 |
| 1487 | #define DWC_HS_PHY_IRQ_STAT_DPINTLCH_BMSK 0x8 |
| 1488 | #define DWC_HS_PHY_IRQ_STAT_DPINTLCH_SHFT 0x3 |
| 1489 | #define DWC_HS_PHY_IRQ_STAT_DCDINTLCH_BMSK 0x4 |
| 1490 | #define DWC_HS_PHY_IRQ_STAT_DCDINTLCH_SHFT 0x2 |
| 1491 | #define DWC_HS_PHY_IRQ_STAT_DMINTLCH_BMSK 0x2 |
| 1492 | #define DWC_HS_PHY_IRQ_STAT_DMINTLCH_SHFT 0x1 |
| 1493 | #define DWC_HS_PHY_IRQ_STAT_ACAINTLCH_BMSK 0x1 |
| 1494 | #define DWC_HS_PHY_IRQ_STAT_ACAINTLCH_SHFT 0x0 |
| 1495 | |
| 1496 | |
| 1497 | #define DWC_SS_PHY_CTRL_ADDR(x) ((x) + 0x00000030) |
| 1498 | #define DWC_SS_PHY_CTRL_OFFS (0x00000030) |
| 1499 | #define DWC_SS_PHY_CTRL_RMSK 0x1fffffff |
| 1500 | #define DWC_SS_PHY_CTRL_POR 0x10108002 |
| 1501 | #define DWC_SS_PHY_CTRL_REF_USE_PAD_BMSK 0x10000000 |
| 1502 | #define DWC_SS_PHY_CTRL_REF_USE_PAD_SHFT 0x1c |
| 1503 | #define DWC_SS_PHY_CTRL_TEST_BURNIN_BMSK 0x8000000 |
| 1504 | #define DWC_SS_PHY_CTRL_TEST_BURNIN_SHFT 0x1b |
| 1505 | #define DWC_SS_PHY_CTRL_TEST_POWERDOWN_BMSK 0x4000000 |
| 1506 | #define DWC_SS_PHY_CTRL_TEST_POWERDOWN_SHFT 0x1a |
| 1507 | #define DWC_SS_PHY_CTRL_RTUNE_REQ_BMSK 0x2000000 |
| 1508 | #define DWC_SS_PHY_CTRL_RTUNE_REQ_SHFT 0x19 |
| 1509 | #define DWC_SS_PHY_CTRL_LANE0_PWR_PRESENT_BMSK 0x1000000 |
| 1510 | #define DWC_SS_PHY_CTRL_LANE0_PWR_PRESENT_SHFT 0x18 |
| 1511 | #define DWC_SS_PHY_CTRL_USB2_REF_CLK_EN_BMSK 0x800000 |
| 1512 | #define DWC_SS_PHY_CTRL_USB2_REF_CLK_EN_SHFT 0x17 |
| 1513 | #define DWC_SS_PHY_CTRL_USB2_REF_CLK_SEL_BMSK 0x400000 |
| 1514 | #define DWC_SS_PHY_CTRL_USB2_REF_CLK_SEL_SHFT 0x16 |
| 1515 | #define DWC_SS_PHY_CTRL_SSC_REF_CLK_SEL_BMSK 0x3fe000 |
| 1516 | #define DWC_SS_PHY_CTRL_SSC_REF_CLK_SEL_SHFT 0xd |
| 1517 | #define DWC_SS_PHY_CTRL_SSC_RANGE_BMSK 0x1c00 |
| 1518 | #define DWC_SS_PHY_CTRL_SSC_RANGE_SHFT 0xa |
| 1519 | #define DWC_SS_PHY_CTRL_REF_USB2_EN_BMSK 0x200 |
| 1520 | #define DWC_SS_PHY_CTRL_REF_USB2_EN_SHFT 0x9 |
| 1521 | #define DWC_SS_PHY_CTRL_REF_SS_PHY_EN_BMSK 0x100 |
| 1522 | #define DWC_SS_PHY_CTRL_REF_SS_PHY_EN_SHFT 0x8 |
| 1523 | #define DWC_SS_PHY_CTRL_SS_PHY_RESET_BMSK 0x80 |
| 1524 | #define DWC_SS_PHY_CTRL_SS_PHY_RESET_SHFT 0x7 |
| 1525 | #define DWC_SS_PHY_CTRL_MPLL_MULTI_BMSK 0x7f |
| 1526 | #define DWC_SS_PHY_CTRL_MPLL_MULTI_SHFT 0x0 |
| 1527 | |
| 1528 | |
| 1529 | #endif /* _DWC_DWC_H_ */ |