Channagoud Kadabi | eb6e9e7 | 2015-06-13 10:48:30 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012,2015 The Linux Foundation. All rights reserved. |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 2 | * |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <bam.h> |
| 30 | #include <reg.h> |
| 31 | #include <debug.h> |
| 32 | #include <stdlib.h> |
Deepa Dinamani | 62df2c7 | 2012-12-19 17:17:58 -0800 | [diff] [blame] | 33 | #include <arch/ops.h> |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 34 | #include <platform.h> |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 35 | #include <platform/interrupts.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <platform/irqs.h> |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 38 | #include <pow2.h> |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 39 | |
| 40 | #define HLOS_EE_INDEX 0 |
| 41 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 42 | /* Resets pipe registers and state machines */ |
Deepa Dinamani | 87feab8 | 2012-10-04 14:28:05 -0700 | [diff] [blame] | 43 | void bam_pipe_reset(struct bam_instance *bam, |
| 44 | uint8_t pipe_num) |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 45 | { |
| 46 | /* Start sw reset of the pipe to be allocated */ |
| 47 | writel(1, BAM_P_RSTn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 48 | |
| 49 | /* No delay required */ |
| 50 | |
| 51 | /* Stop sw reset of the pipe to be allocated */ |
| 52 | writel(0, BAM_P_RSTn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 53 | } |
| 54 | |
| 55 | static enum handler_return bam_interrupt_handler(void* arg) |
| 56 | { |
| 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | /* A blocking function that waits till an interrupt is signalled. |
| 61 | * bam : BAM instance for the descriptors to be queued. |
| 62 | * pipe_num : pipe number for the descriptors to be queued. |
| 63 | * interrupt: interrupt to wait for. |
| 64 | */ |
| 65 | int bam_wait_for_interrupt(struct bam_instance *bam, |
| 66 | uint8_t pipe_num, |
| 67 | enum p_int_type interrupt) |
| 68 | { |
| 69 | uint32_t val; |
| 70 | |
| 71 | while (1) |
| 72 | { |
| 73 | /* Wait for a interrupt on the right pipe */ |
| 74 | do{ |
| 75 | /* Determine the pipe causing the interrupt */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 76 | val = readl(BAM_IRQ_SRCS(bam->base, bam->ee)); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 77 | /* Flush out the right most global interrupt bit */ |
| 78 | } while (!((val & 0x7FFF) & (1 << bam->pipe[pipe_num].pipe_num))); |
| 79 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 80 | /* Check the interrupt type */ |
| 81 | /* Read interrupt status register */ |
| 82 | val = readl(BAM_P_IRQ_STTSn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 83 | |
| 84 | /* Check for error */ |
| 85 | if (val & P_ERR_EN_MASK) |
| 86 | goto bam_wait_int_error; |
| 87 | |
| 88 | if (val & interrupt) |
| 89 | { |
| 90 | /* Correct interrupt was fired. */ |
| 91 | /* Clear the other interrupts */ |
| 92 | val = P_OUT_OF_DESC_EN_MASK | P_PRCSD_DESC_EN_MASK | P_TRNSFR_END_EN_MASK; |
| 93 | writel (val, BAM_P_IRQ_CLRn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 94 | return BAM_RESULT_SUCCESS; |
| 95 | } |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | bam_wait_int_error: |
| 99 | |
Sundarajan Srinivasan | 802a9ec | 2013-07-11 16:02:57 -0700 | [diff] [blame] | 100 | dprintf(CRITICAL, "Unexpected interrupt : val %u\n", val); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 101 | return BAM_RESULT_FAILURE; |
| 102 | } |
| 103 | |
| 104 | /* Enable BAM and pipe level interrupts */ |
| 105 | void bam_enable_interrupts(struct bam_instance *bam, uint8_t pipe_num) |
| 106 | { |
| 107 | |
| 108 | uint32_t int_mask = P_ERR_EN_MASK | P_OUT_OF_DESC_EN_MASK | |
Sundarajan Srinivasan | 802a9ec | 2013-07-11 16:02:57 -0700 | [diff] [blame] | 109 | P_PRCSD_DESC_EN_MASK; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 110 | uint32_t val; |
| 111 | |
Deepa Dinamani | 5f68e84 | 2013-05-14 16:46:08 -0700 | [diff] [blame] | 112 | /* Leave BAM error interrupts disabled. */ |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 113 | /* Enable the interrupts for the pipe by enabling the relevant bits |
| 114 | * in the BAM_PIPE_INTERRUPT_ENABLE register. |
| 115 | */ |
| 116 | writel(int_mask, |
| 117 | BAM_P_IRQ_ENn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 118 | |
| 119 | /* Enable pipe interrups */ |
| 120 | /* Do read-modify-write */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 121 | val = readl(BAM_IRQ_SRCS_MSK(bam->base, bam->ee)); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 122 | writel((1 << bam->pipe[pipe_num].pipe_num) | val, |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 123 | BAM_IRQ_SRCS_MSK(bam->base, bam->ee)); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 124 | |
| 125 | /* Unmask the QGIC interrupts only in the case of |
| 126 | * interrupt based transfer. |
| 127 | * Use polling othwerwise. |
| 128 | */ |
| 129 | if (bam->pipe[pipe_num].int_mode) |
| 130 | { |
| 131 | /* Register interrupt handler */ |
| 132 | register_int_handler(bam->pipe[pipe_num].spi_num, bam_interrupt_handler, 0); |
| 133 | |
| 134 | /* Unmask the interrupt */ |
| 135 | unmask_interrupt(bam->pipe[pipe_num].spi_num); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | /* Reset and initialize the bam module */ |
| 140 | void bam_init(struct bam_instance *bam) |
| 141 | { |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 142 | /* Check for only one pipe's direction. |
| 143 | * The other is assumed to be the opposite system |
| 144 | * transaction. |
| 145 | */ |
| 146 | if (bam->pipe[0].trans_type == SYS2BAM || |
| 147 | bam->pipe[0].trans_type == BAM2SYS) |
| 148 | { |
| 149 | /* Program the threshold count */ |
| 150 | writel(bam->threshold, BAM_DESC_CNT_TRSHLD_REG(bam->base)); |
| 151 | } |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* Funtion to setup a simple fifo structure. |
| 155 | * Note: Addr should be 8 byte aligned. |
| 156 | * bam : BAM instance for the descriptors to be queued. |
| 157 | * pipe_num : pipe number for the descriptors to be queued. |
| 158 | */ |
| 159 | int bam_pipe_fifo_init(struct bam_instance *bam, |
| 160 | uint8_t pipe_num) |
| 161 | { |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 162 | if (bam->pipe[pipe_num].fifo.size > 0x7FFF) |
| 163 | { |
| 164 | dprintf(CRITICAL, |
| 165 | "Size exceeds max size for a descriptor(0x7FFF)\n"); |
| 166 | return BAM_RESULT_FAILURE; |
| 167 | } |
| 168 | |
| 169 | /* Check if fifo start is 8-byte alligned */ |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 170 | ASSERT(!((uint32_t)PA((addr_t)bam->pipe[pipe_num].fifo.head & 0x7))); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 171 | |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 172 | /* Check if fifo size is a power of 2. |
| 173 | * The circular fifo logic in lk expects this. |
| 174 | */ |
| 175 | ASSERT(ispow2(bam->pipe[pipe_num].fifo.size)); |
| 176 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 177 | bam->pipe[pipe_num].fifo.current = bam->pipe[pipe_num].fifo.head; |
| 178 | |
| 179 | /* Set the descriptor buffer size. Must be a multiple of 8 */ |
| 180 | writel(bam->pipe[pipe_num].fifo.size * BAM_DESC_SIZE, |
| 181 | BAM_P_FIFO_SIZESn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 182 | |
| 183 | /* Write descriptors FIFO base addr must be 8-byte aligned */ |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 184 | /* Needs a physical address conversion as we are setting up |
| 185 | * the base of the FIFO for the BAM state machine. |
| 186 | */ |
| 187 | writel((uint32_t)PA((addr_t)bam->pipe[pipe_num].fifo.head), |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 188 | BAM_P_DESC_FIFO_ADDRn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 189 | |
| 190 | /* Initialize FIFO offset for the first read */ |
| 191 | bam->pipe[pipe_num].fifo.offset = BAM_DESC_SIZE; |
| 192 | |
Deepa Dinamani | a0407ea | 2013-07-09 12:51:45 -0700 | [diff] [blame] | 193 | writel(P_ENABLE | readl(BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base)), |
| 194 | BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 195 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 196 | /* Everything is set. |
| 197 | * Flag pipe init done. |
| 198 | */ |
| 199 | bam->pipe[pipe_num].initialized = 1; |
| 200 | |
| 201 | return BAM_RESULT_SUCCESS; |
| 202 | } |
| 203 | |
| 204 | void bam_sys_pipe_init(struct bam_instance *bam, |
| 205 | uint8_t pipe_num) |
| 206 | { |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 207 | /* Reset the pipe to be allocated */ |
| 208 | bam_pipe_reset(bam, pipe_num); |
| 209 | |
| 210 | /* Enable minimal interrupts */ |
| 211 | bam_enable_interrupts(bam, pipe_num); |
| 212 | |
| 213 | /* Pipe event threshold register is not relevant in sys modes */ |
| 214 | |
| 215 | /* Enable pipe in system mode and set the direction */ |
Deepa Dinamani | a0407ea | 2013-07-09 12:51:45 -0700 | [diff] [blame] | 216 | writel(P_SYS_MODE_MASK | bam->pipe[pipe_num].lock_grp << P_LOCK_GRP_SHIFT | |
| 217 | (bam->pipe[pipe_num].trans_type << P_DIRECTION_SHIFT), |
| 218 | BAM_P_CTRLn(bam->pipe[pipe_num].pipe_num, bam->base)); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 219 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 220 | /* Mark the pipe FIFO as uninitialized. */ |
| 221 | bam->pipe[pipe_num].initialized = 0; |
| 222 | } |
| 223 | |
| 224 | /* Function to notify written descriptors to BAM. |
| 225 | * bam : BAM instance for the descriptors to be queued. |
| 226 | * pipe_num : pipe number for the descriptors to be queued. |
| 227 | * num_desc : number of the descriptors. |
| 228 | * fifo : Circular FIFO used for the descriptors. |
| 229 | */ |
| 230 | void bam_sys_gen_event(struct bam_instance *bam, |
| 231 | uint8_t pipe_num, |
| 232 | unsigned int num_desc) |
| 233 | { |
| 234 | uint32_t val = 0; |
| 235 | |
| 236 | if (num_desc >= bam->pipe[pipe_num].fifo.size) { |
| 237 | dprintf(CRITICAL, |
| 238 | "Max allowed desc is one less than the fifo length\n"); |
| 239 | return; |
| 240 | } |
| 241 | |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 242 | /* bits 0:15 of BAM_P_EVNT_REGn denotes the offset. We read the offset, |
| 243 | * and update the offset to notify BAM HW that new descriptors have been written |
| 244 | */ |
| 245 | val = readl(BAM_P_EVNT_REGn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 246 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 247 | /* Update the fifo peer offset */ |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 248 | val += (num_desc) * BAM_DESC_SIZE; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 249 | val &= (bam->pipe[pipe_num].fifo.size * BAM_DESC_SIZE - 1); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 250 | |
| 251 | writel(val, BAM_P_EVNT_REGn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 252 | } |
| 253 | |
| 254 | /* Function to read the updates for FIFO offsets. |
| 255 | * bam : BAM that uses the FIFO. |
| 256 | * pipe : BAM pipe that uses the FIFO. |
Sundarajan Srinivasan | 024bda5 | 2014-02-27 16:48:48 -0800 | [diff] [blame] | 257 | * return : void. |
| 258 | * Note : As per IPCAT This register denotes the pointer Offset of the first un-Acknowledged Descriptor. |
| 259 | * This register is only used by the Software. After receiving an interrupt, software reads this register |
| 260 | * in order to know what descriptors has been processed. Although being Writable, Software |
| 261 | * should never write to this register. |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 262 | */ |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 263 | void bam_read_offset_update(struct bam_instance *bam, unsigned int pipe_num) |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 264 | { |
| 265 | uint32_t offset; |
| 266 | |
| 267 | offset = readl(BAM_P_SW_OFSTSn(bam->pipe[pipe_num].pipe_num, bam->base)); |
| 268 | offset &= 0xFFFF; |
| 269 | |
Deepa Dinamani | 9c59ac6 | 2012-12-03 10:51:59 -0800 | [diff] [blame] | 270 | dprintf(SPEW, "Offset value is %d \n", offset); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | /* Function to get the next desc address. |
| 274 | * Keeps track of circular properties of the FIFO |
| 275 | * and returns the appropriate address. |
| 276 | */ |
| 277 | static struct bam_desc* fifo_getnext(struct bam_desc_fifo *fifo, |
| 278 | struct bam_desc* desc) |
| 279 | { |
| 280 | uint16_t offset; |
| 281 | |
| 282 | offset = desc - fifo->head; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 283 | |
| 284 | if (offset == (fifo->size - 1)) |
| 285 | return fifo->head; |
| 286 | else |
| 287 | return desc + 1; |
| 288 | } |
| 289 | |
| 290 | /* Function to add BAM descriptors for a given fifo. |
| 291 | * bam : BAM instance to be used. |
| 292 | * data_ptr : Memory address for data transfer. |
| 293 | * data_len : Length of the data_ptr. |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 294 | * flags : Flags to be set on the last desc added. |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 295 | * |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 296 | * Note: This function also notifies the BAM about the added descriptors. |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 297 | */ |
| 298 | int bam_add_desc(struct bam_instance *bam, |
| 299 | unsigned int pipe_num, |
| 300 | unsigned char *data_ptr, |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 301 | unsigned int data_len, |
| 302 | unsigned flags) |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 303 | { |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 304 | int bam_ret = BAM_RESULT_SUCCESS; |
| 305 | unsigned int len = data_len; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 306 | unsigned int desc_len; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 307 | unsigned int n = 0; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 308 | unsigned int desc_flags; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 309 | |
Deepa Dinamani | 9c59ac6 | 2012-12-03 10:51:59 -0800 | [diff] [blame] | 310 | dprintf(SPEW, "Data length for BAM transfer is %u\n", data_len); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 311 | |
| 312 | if (data_ptr == NULL || len == 0) |
| 313 | { |
| 314 | dprintf(CRITICAL, "Wrong params for BAM transfer \n"); |
| 315 | bam_ret = BAM_RESULT_FAILURE; |
| 316 | goto bam_add_desc_error; |
| 317 | } |
| 318 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 319 | /* Check if we have enough space in FIFO */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 320 | if (len > (unsigned)bam->pipe[pipe_num].fifo.size * bam->max_desc_len) |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 321 | { |
| 322 | dprintf(CRITICAL, "Data transfer exceeds desc fifo length.\n"); |
| 323 | bam_ret = BAM_RESULT_FAILURE; |
| 324 | goto bam_add_desc_error; |
| 325 | } |
| 326 | |
| 327 | while (len) |
| 328 | { |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 329 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 330 | /* There are only 16 bits to write data length. |
| 331 | * If more bits are needed, create more |
| 332 | * descriptors. |
| 333 | */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 334 | if (len > bam->max_desc_len) |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 335 | { |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 336 | desc_len = bam->max_desc_len; |
| 337 | len -= bam->max_desc_len; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 338 | desc_flags = 0; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 339 | } |
| 340 | else |
| 341 | { |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 342 | desc_len = len; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 343 | len = 0; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 344 | /* Set correct flags on the last desc. */ |
| 345 | desc_flags = flags; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 346 | } |
| 347 | |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 348 | /* Write descriptor */ |
| 349 | bam_add_one_desc(bam, pipe_num, data_ptr, desc_len, desc_flags); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 350 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 351 | data_ptr += bam->max_desc_len; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 352 | n++; |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 353 | } |
| 354 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 355 | |
| 356 | /* Create a read/write event to notify the periperal of the added desc. */ |
| 357 | bam_sys_gen_event(bam, pipe_num, n); |
| 358 | |
| 359 | bam_add_desc_error: |
| 360 | |
| 361 | return bam_ret; |
| 362 | } |
| 363 | |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 364 | /* Function to add a BAM descriptor for a given fifo. |
| 365 | * bam : BAM instance to be used. |
| 366 | * data_ptr : Memory address for data transfer. |
| 367 | * data_len : Length of the data_ptr. |
| 368 | * flags : Flags to be set on the desc added. |
| 369 | * |
| 370 | * Note: This function does not notify the BAM about the added descriptor. |
| 371 | */ |
| 372 | int bam_add_one_desc(struct bam_instance *bam, |
| 373 | unsigned int pipe_num, |
| 374 | unsigned char* data_ptr, |
| 375 | uint32_t len, |
| 376 | uint8_t flags) |
| 377 | { |
| 378 | |
| 379 | struct bam_desc *desc = bam->pipe[pipe_num].fifo.current; |
| 380 | int bam_ret = BAM_RESULT_SUCCESS; |
| 381 | |
| 382 | if (data_ptr == NULL || len == 0) |
| 383 | { |
| 384 | dprintf(CRITICAL, "Wrong params for BAM transfer \n"); |
| 385 | bam_ret = BAM_RESULT_FAILURE; |
| 386 | goto bam_add_one_desc_error; |
| 387 | } |
| 388 | |
| 389 | /* Check if the FIFO is allocated for the pipe */ |
| 390 | if (!bam->pipe[pipe_num].initialized) |
| 391 | { |
| 392 | dprintf(CRITICAL, "Please allocate the FIFO for the BAM pipe %d\n", |
| 393 | bam->pipe[pipe_num].pipe_num); |
| 394 | bam_ret = BAM_RESULT_FAILURE; |
| 395 | goto bam_add_one_desc_error; |
| 396 | } |
| 397 | |
| 398 | if ((flags & BAM_DESC_LOCK_FLAG) && (flags & BAM_DESC_UNLOCK_FLAG)) |
| 399 | { |
| 400 | dprintf(CRITICAL, "Can't lock and unlock in the same desc\n"); |
| 401 | bam_ret = BAM_RESULT_FAILURE; |
| 402 | goto bam_add_one_desc_error; |
| 403 | } |
| 404 | |
| 405 | /* Setting EOT flag on a CMD desc is not valid */ |
| 406 | if ((flags & BAM_DESC_EOT_FLAG) && (flags & BAM_DESC_CMD_FLAG)) |
| 407 | { |
| 408 | dprintf(CRITICAL, "EOT flag set on the CMD desc\n"); |
| 409 | bam_ret = BAM_RESULT_FAILURE; |
| 410 | goto bam_add_one_desc_error; |
| 411 | } |
| 412 | |
| 413 | /* Check for the length of the desc. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 414 | if (len > bam->max_desc_len) |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 415 | { |
| 416 | dprintf(CRITICAL, "len of the desc exceeds max length" |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 417 | " %d > %d\n", len, bam->max_desc_len); |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 418 | bam_ret = BAM_RESULT_FAILURE; |
| 419 | goto bam_add_one_desc_error; |
| 420 | } |
| 421 | |
Deepa Dinamani | 62df2c7 | 2012-12-19 17:17:58 -0800 | [diff] [blame] | 422 | desc->flags = flags; |
| 423 | desc->addr = (uint32_t)data_ptr; |
| 424 | desc->size = (uint16_t)len; |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 425 | desc->reserved = 0; |
| 426 | |
Deepa Dinamani | 62df2c7 | 2012-12-19 17:17:58 -0800 | [diff] [blame] | 427 | arch_clean_invalidate_cache_range((addr_t) desc, BAM_DESC_SIZE); |
| 428 | |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 429 | /* Update the FIFO to point to the head */ |
| 430 | bam->pipe[pipe_num].fifo.current = fifo_getnext(&bam->pipe[pipe_num].fifo, desc); |
| 431 | |
| 432 | bam_add_one_desc_error: |
| 433 | return bam_ret; |
| 434 | } |
| 435 | |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 436 | struct cmd_element* bam_add_cmd_element(struct cmd_element *ptr, |
| 437 | uint32_t reg_addr, |
| 438 | uint32_t value, |
| 439 | enum bam_ce_cmd_t cmd_type) |
| 440 | { |
| 441 | /* Write cmd type. |
| 442 | * Also, write the register address. |
| 443 | */ |
Deepa Dinamani | e5ccd6c | 2012-08-16 11:41:06 -0700 | [diff] [blame] | 444 | ptr->addr_n_cmd = (reg_addr & ~(0xFF000000)) | (cmd_type << 24); |
Deepa Dinamani | 9d470af | 2012-06-29 18:27:17 -0700 | [diff] [blame] | 445 | |
| 446 | /* Do not mask any of the addr bits by default */ |
| 447 | ptr->reg_mask = 0xFFFFFFFF; |
| 448 | |
| 449 | /* Write the value to be written */ |
| 450 | ptr->reg_data = value; |
| 451 | |
| 452 | /* Return the address to add the next element to */ |
| 453 | return ptr + 1; |
| 454 | } |