Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 1 | /* |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Linux Foundation nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 42 | #define usb30_pipe_source_val 2 |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 43 | |
| 44 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 45 | |
| 46 | |
| 47 | /* Clock Operations */ |
Channagoud Kadabi | 52b92e2 | 2014-04-03 15:29:44 -0700 | [diff] [blame] | 48 | static struct clk_ops clk_ops_reset = |
| 49 | { |
| 50 | .reset = clock_lib2_reset_clk_reset, |
| 51 | }; |
| 52 | |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 53 | static struct clk_ops clk_ops_branch = |
| 54 | { |
| 55 | .enable = clock_lib2_branch_clk_enable, |
| 56 | .disable = clock_lib2_branch_clk_disable, |
| 57 | .set_rate = clock_lib2_branch_set_rate, |
Channagoud Kadabi | 52b92e2 | 2014-04-03 15:29:44 -0700 | [diff] [blame] | 58 | .reset = clock_lib2_branch_clk_reset, |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | static struct clk_ops clk_ops_rcg_mnd = |
| 62 | { |
| 63 | .enable = clock_lib2_rcg_enable, |
| 64 | .set_rate = clock_lib2_rcg_set_rate, |
| 65 | }; |
| 66 | |
| 67 | static struct clk_ops clk_ops_rcg = |
| 68 | { |
| 69 | .enable = clock_lib2_rcg_enable, |
| 70 | .set_rate = clock_lib2_rcg_set_rate, |
| 71 | }; |
| 72 | |
| 73 | static struct clk_ops clk_ops_cxo = |
| 74 | { |
| 75 | .enable = cxo_clk_enable, |
| 76 | .disable = cxo_clk_disable, |
| 77 | }; |
| 78 | |
| 79 | static struct clk_ops clk_ops_pll_vote = |
| 80 | { |
| 81 | .enable = pll_vote_clk_enable, |
| 82 | .disable = pll_vote_clk_disable, |
| 83 | .auto_off = pll_vote_clk_disable, |
| 84 | .is_enabled = pll_vote_clk_is_enabled, |
| 85 | }; |
| 86 | |
| 87 | static struct clk_ops clk_ops_vote = |
| 88 | { |
| 89 | .enable = clock_lib2_vote_clk_enable, |
| 90 | .disable = clock_lib2_vote_clk_disable, |
| 91 | }; |
| 92 | |
| 93 | /* Clock Sources */ |
| 94 | static struct fixed_clk cxo_clk_src = |
| 95 | { |
| 96 | .c = { |
| 97 | .rate = 19200000, |
| 98 | .dbg_name = "cxo_clk_src", |
| 99 | .ops = &clk_ops_cxo, |
| 100 | }, |
| 101 | }; |
| 102 | |
| 103 | static struct pll_vote_clk gpll0_clk_src = |
| 104 | { |
| 105 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 106 | .en_mask = BIT(0), |
| 107 | .status_reg = (void *) GPLL0_STATUS, |
Sundarajan Srinivasan | 7b39014 | 2013-10-29 12:32:50 -0700 | [diff] [blame] | 108 | .status_mask = BIT(30), |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 109 | .parent = &cxo_clk_src.c, |
| 110 | |
| 111 | .c = { |
| 112 | .rate = 600000000, |
| 113 | .dbg_name = "gpll0_clk_src", |
| 114 | .ops = &clk_ops_pll_vote, |
| 115 | }, |
| 116 | }; |
| 117 | |
| 118 | /* UART Clocks */ |
| 119 | |
| 120 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 121 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 122 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 123 | .en_mask = BIT(17), |
| 124 | |
| 125 | .c = { |
| 126 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 127 | .ops = &clk_ops_vote, |
| 128 | }, |
| 129 | }; |
| 130 | |
| 131 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 132 | { |
| 133 | F( 3686400, gpll0, 1, 96, 15625), |
| 134 | F( 7372800, gpll0, 1, 192, 15625), |
| 135 | F(14745600, gpll0, 1, 384, 15625), |
| 136 | F(16000000, gpll0, 5, 2, 15), |
| 137 | F(19200000, cxo, 1, 0, 0), |
| 138 | F(24000000, gpll0, 5, 1, 5), |
| 139 | F(32000000, gpll0, 1, 4, 75), |
| 140 | F(40000000, gpll0, 15, 0, 0), |
| 141 | F(46400000, gpll0, 1, 29, 375), |
| 142 | F(48000000, gpll0, 12.5, 0, 0), |
| 143 | F(51200000, gpll0, 1, 32, 375), |
| 144 | F(56000000, gpll0, 1, 7, 75), |
| 145 | F(58982400, gpll0, 1, 1536, 15625), |
| 146 | F(60000000, gpll0, 10, 0, 0), |
| 147 | F_END |
| 148 | }; |
| 149 | |
| 150 | static struct rcg_clk blsp1_uart1_apps_clk_src = |
| 151 | { |
| 152 | .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR, |
| 153 | .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR, |
| 154 | .m_reg = (uint32_t *) BLSP1_UART1_APPS_M, |
| 155 | .n_reg = (uint32_t *) BLSP1_UART1_APPS_N, |
| 156 | .d_reg = (uint32_t *) BLSP1_UART1_APPS_D, |
| 157 | |
| 158 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 159 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 160 | .current_freq = &rcg_dummy_freq, |
| 161 | |
| 162 | .c = { |
| 163 | .dbg_name = "blsp1_uart1_apps_clk", |
| 164 | .ops = &clk_ops_rcg_mnd, |
| 165 | }, |
| 166 | }; |
| 167 | |
| 168 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 169 | { |
| 170 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 171 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 172 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 173 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 174 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 175 | |
| 176 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 177 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 178 | .current_freq = &rcg_dummy_freq, |
| 179 | |
| 180 | .c = { |
| 181 | .dbg_name = "blsp1_uart2_apps_clk", |
| 182 | .ops = &clk_ops_rcg_mnd, |
| 183 | }, |
| 184 | }; |
| 185 | |
| 186 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
| 187 | { |
| 188 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 189 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 190 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 191 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 192 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
| 193 | |
| 194 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 195 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 196 | .current_freq = &rcg_dummy_freq, |
| 197 | |
| 198 | .c = { |
| 199 | .dbg_name = "blsp1_uart3_apps_clk", |
| 200 | .ops = &clk_ops_rcg_mnd, |
| 201 | }, |
| 202 | }; |
| 203 | |
| 204 | static struct branch_clk gcc_blsp1_uart1_apps_clk = |
| 205 | { |
| 206 | .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR, |
| 207 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 208 | |
| 209 | .c = { |
| 210 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 211 | .ops = &clk_ops_branch, |
| 212 | }, |
| 213 | }; |
| 214 | |
| 215 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 216 | { |
| 217 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 218 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 219 | |
| 220 | .c = { |
| 221 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 222 | .ops = &clk_ops_branch, |
| 223 | }, |
| 224 | }; |
| 225 | |
| 226 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
| 227 | { |
| 228 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 229 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 230 | |
| 231 | .c = { |
| 232 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 233 | .ops = &clk_ops_branch, |
| 234 | }, |
| 235 | }; |
| 236 | |
| 237 | /* USB Clocks */ |
| 238 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 239 | { |
| 240 | F(75000000, gpll0, 8, 0, 0), |
| 241 | F_END |
| 242 | }; |
| 243 | |
| 244 | static struct rcg_clk usb_hs_system_clk_src = |
| 245 | { |
| 246 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 247 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 248 | |
| 249 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 250 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 251 | .current_freq = &rcg_dummy_freq, |
| 252 | |
| 253 | .c = { |
| 254 | .dbg_name = "usb_hs_system_clk", |
| 255 | .ops = &clk_ops_rcg, |
| 256 | }, |
| 257 | }; |
| 258 | |
| 259 | static struct branch_clk gcc_usb_hs_system_clk = |
| 260 | { |
| 261 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 262 | .parent = &usb_hs_system_clk_src.c, |
| 263 | |
| 264 | .c = { |
| 265 | .dbg_name = "gcc_usb_hs_system_clk", |
| 266 | .ops = &clk_ops_branch, |
| 267 | }, |
| 268 | }; |
| 269 | |
| 270 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 271 | { |
| 272 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 273 | .has_sibling = 1, |
| 274 | |
| 275 | .c = { |
| 276 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 277 | .ops = &clk_ops_branch, |
| 278 | }, |
| 279 | }; |
| 280 | |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 281 | static struct clk_freq_tbl ftbl_gcc_usb30_pipe_clk[] = { |
| 282 | F( 19200000, cxo, 1, 0, 0), |
| 283 | F_EXT_SRC( 125000000, usb30_pipe, 1, 0, 0), |
| 284 | F_END |
| 285 | }; |
| 286 | |
| 287 | static struct rcg_clk usb30_pipe_clk_src = { |
| 288 | .cmd_reg = (uint32_t *) USB3_PIPE_CMD_RCGR, |
| 289 | .cfg_reg = (uint32_t *) USB3_PIPE_CFG_RCGR, |
| 290 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 291 | .freq_tbl = ftbl_gcc_usb30_pipe_clk, |
| 292 | .current_freq = &rcg_dummy_freq, |
| 293 | |
| 294 | .c = { |
| 295 | .dbg_name = "usb30_pipe_clk_src", |
| 296 | .ops = &clk_ops_rcg, |
| 297 | }, |
| 298 | }; |
| 299 | |
| 300 | static struct branch_clk gcc_usb30_pipe_clk = { |
Channagoud Kadabi | 52b92e2 | 2014-04-03 15:29:44 -0700 | [diff] [blame] | 301 | .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR, |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 302 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
| 303 | .parent = &usb30_pipe_clk_src.c, |
| 304 | .has_sibling = 0, |
| 305 | |
| 306 | .c = { |
| 307 | .dbg_name = "gcc_usb30_pipe_clk", |
| 308 | .ops = &clk_ops_branch, |
| 309 | }, |
| 310 | }; |
| 311 | |
| 312 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = |
| 313 | { |
| 314 | F(125000000, gpll0, 1, 5, 24), |
| 315 | F_END |
| 316 | }; |
| 317 | |
| 318 | static struct rcg_clk usb30_master_clk_src = |
| 319 | { |
| 320 | .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR, |
| 321 | .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR, |
| 322 | .m_reg = (uint32_t *) GCC_USB30_MASTER_M, |
| 323 | .n_reg = (uint32_t *) GCC_USB30_MASTER_N, |
| 324 | .d_reg = (uint32_t *) GCC_USB30_MASTER_D, |
| 325 | |
| 326 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 327 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 328 | .current_freq = &rcg_dummy_freq, |
| 329 | |
| 330 | .c = { |
| 331 | .dbg_name = "usb30_master_clk_src", |
| 332 | .ops = &clk_ops_rcg, |
| 333 | }, |
| 334 | }; |
| 335 | |
| 336 | |
| 337 | static struct branch_clk gcc_usb30_master_clk = |
| 338 | { |
| 339 | .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR, |
| 340 | .parent = &usb30_master_clk_src.c, |
| 341 | |
| 342 | .c = { |
| 343 | .dbg_name = "gcc_usb30_master_clk", |
| 344 | .ops = &clk_ops_branch, |
| 345 | }, |
| 346 | }; |
| 347 | |
| 348 | static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = { |
| 349 | F( 1000000, cxo, 1, 5, 96), |
| 350 | F_END |
| 351 | }; |
| 352 | |
| 353 | static struct rcg_clk usb30_aux_clk_src = { |
| 354 | .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR, |
| 355 | .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR, |
| 356 | .m_reg = (uint32_t *) USB3_AUX_M, |
| 357 | .n_reg = (uint32_t *) USB3_AUX_N, |
| 358 | .d_reg = (uint32_t *) USB3_AUX_D, |
| 359 | |
| 360 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 361 | .freq_tbl = ftbl_gcc_usb30_aux_clk, |
| 362 | .current_freq = &rcg_dummy_freq, |
| 363 | |
| 364 | .c = { |
| 365 | .dbg_name = "usb30_aux_clk_src", |
| 366 | .ops = &clk_ops_rcg_mnd, |
| 367 | }, |
| 368 | }; |
| 369 | |
| 370 | static struct branch_clk gcc_usb30_aux_clk = { |
| 371 | .cbcr_reg = (uint32_t *) USB3_AUX_CBCR, |
| 372 | .parent = &usb30_aux_clk_src.c, |
| 373 | |
| 374 | .c = { |
| 375 | .dbg_name = "gcc_usb30_aux_clk", |
| 376 | .ops = &clk_ops_branch, |
| 377 | }, |
| 378 | }; |
| 379 | |
| 380 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = |
| 381 | { |
| 382 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 383 | .has_sibling = 1, |
| 384 | |
| 385 | .c = { |
| 386 | .dbg_name = "gcc_sys_noc_usb3_axi_clk", |
| 387 | .ops = &clk_ops_branch, |
| 388 | }, |
| 389 | }; |
| 390 | |
| 391 | static struct branch_clk gcc_usb_phy_cfg_ahb_clk = { |
| 392 | .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR, |
| 393 | .has_sibling = 1, |
| 394 | |
| 395 | .c = { |
| 396 | .dbg_name = "gcc_usb_phy_cfg_ahb_clk", |
| 397 | .ops = &clk_ops_branch, |
| 398 | }, |
| 399 | }; |
| 400 | |
Channagoud Kadabi | 52b92e2 | 2014-04-03 15:29:44 -0700 | [diff] [blame] | 401 | static struct reset_clk gcc_usb30_phy_com_reset = { |
| 402 | .bcr_reg = (uint32_t *) USB3_PHY_COM_BCR, |
| 403 | |
| 404 | .c = { |
| 405 | .dbg_name = "usb30_phy_com_reset", |
| 406 | .ops = &clk_ops_reset, |
| 407 | }, |
| 408 | }; |
| 409 | |
| 410 | static struct reset_clk gcc_usb30_phy_reset = { |
| 411 | .bcr_reg = (uint32_t *) USB3_PHY_BCR, |
| 412 | |
| 413 | .c = { |
| 414 | .dbg_name = "usb30_phy_reset", |
| 415 | .ops = &clk_ops_reset, |
| 416 | }, |
| 417 | }; |
| 418 | |
| 419 | static struct branch_clk gcc_usb2b_phy_sleep_clk = { |
| 420 | .bcr_reg = (uint32_t *) USB2B_PHY_BCR, |
| 421 | .cbcr_reg = (uint32_t *) USB2B_PHY_SLEEP_CBCR, |
| 422 | .has_sibling = 1, |
| 423 | |
| 424 | .c = { |
| 425 | .dbg_name = "usb2b_phy_sleep_clk", |
| 426 | .ops = &clk_ops_branch, |
| 427 | }, |
| 428 | }; |
| 429 | |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 430 | /* Clock lookup table */ |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 431 | static struct clk_lookup mdm_9635_clocks[] = |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 432 | { |
| 433 | CLK_LOOKUP("uart_iface_clk", gcc_blsp1_ahb_clk.c), |
| 434 | CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c), |
| 435 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 436 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
| 437 | |
| 438 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 439 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 440 | |
| 441 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 442 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 443 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 444 | CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c), |
| 445 | |
Channagoud Kadabi | 52b92e2 | 2014-04-03 15:29:44 -0700 | [diff] [blame] | 446 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c), |
| 447 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 448 | CLK_LOOKUP("usb30_phy_com_reset", gcc_usb30_phy_com_reset.c), |
| 449 | |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 450 | CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c), |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 451 | }; |
| 452 | |
| 453 | |
| 454 | void platform_clock_init(void) |
| 455 | { |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 456 | clk_init(mdm_9635_clocks, ARRAY_SIZE(mdm_9635_clocks)); |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 457 | } |