Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
| 41 | #include <mdp5.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 42 | #include <scm.h> |
| 43 | |
| 44 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 45 | |
| 46 | static int mdp_rev; |
| 47 | |
| 48 | void mdp_set_revision(int rev) |
| 49 | { |
| 50 | mdp_rev = rev; |
| 51 | } |
| 52 | |
| 53 | int mdp_get_revision() |
| 54 | { |
| 55 | return mdp_rev; |
| 56 | } |
| 57 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 58 | uint32_t mdss_mdp_intf_offset() |
| 59 | { |
| 60 | uint32_t mdss_mdp_intf_off; |
| 61 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 62 | |
| 63 | if (mdss_mdp_rev > MDSS_MDP_HW_REV_100) |
| 64 | mdss_mdp_intf_off = 0; |
| 65 | else |
| 66 | mdss_mdp_intf_off = 0xEC00; |
| 67 | |
| 68 | return mdss_mdp_intf_off; |
| 69 | } |
| 70 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 71 | void mdp_clk_gating_ctrl(void) |
| 72 | { |
| 73 | writel(0x40000000, MDP_CLK_CTRL0); |
| 74 | udelay(20); |
| 75 | writel(0x40000040, MDP_CLK_CTRL0); |
| 76 | writel(0x40000000, MDP_CLK_CTRL1); |
| 77 | writel(0x00400000, MDP_CLK_CTRL3); |
| 78 | udelay(20); |
| 79 | writel(0x00404000, MDP_CLK_CTRL3); |
| 80 | writel(0x40000000, MDP_CLK_CTRL4); |
| 81 | } |
| 82 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 83 | static void mdss_rgb_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
| 84 | *pinfo, uint32_t pipe_base) |
| 85 | { |
| 86 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame^] | 87 | uint32_t fb_off = 0; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 88 | |
| 89 | /* write active region size*/ |
| 90 | src_size = (fb->height << 16) + fb->width; |
| 91 | out_size = src_size; |
| 92 | |
| 93 | if (pinfo->lcdc.dual_pipe) { |
| 94 | out_size = (fb->height << 16) + (fb->width / 2); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame^] | 95 | if ((pinfo->lcdc.pipe_swap == TRUE) && (pipe_base == |
| 96 | MDP_VP_0_RGB_0_BASE)) |
| 97 | fb_off = (pinfo->xres / 2); |
| 98 | else if ((pinfo->lcdc.pipe_swap != TRUE) && (pipe_base == |
| 99 | MDP_VP_0_RGB_1_BASE)) |
| 100 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | stride = (fb->stride * fb->bpp/8); |
| 104 | |
| 105 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 106 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 107 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 108 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 109 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame^] | 110 | writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 111 | writel(0x00, pipe_base + PIPE_SSPP_OUT_XY); |
| 112 | |
| 113 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 114 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 115 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
| 116 | writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
| 117 | } |
| 118 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 119 | static void mdss_vbif_setup() |
| 120 | { |
| 121 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 122 | |
| 123 | /* TZ returns an errornous ret val even if the VBIF registers were |
| 124 | * successfully unlocked. Ignore TZ return value till it's fixed */ |
| 125 | if (!access_secure || 1) { |
| 126 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
| 127 | |
| 128 | /* Force VBIF Clocks on */ |
| 129 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 130 | |
| 131 | if (readl(MDP_HW_REV) == MDSS_MDP_HW_REV_100) { |
| 132 | /* Configure DDR burst length */ |
| 133 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 134 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 135 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 136 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 137 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 138 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 139 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
| 140 | } |
| 141 | } |
| 142 | } |
| 143 | |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 144 | void mdss_smp_setup(struct msm_panel_info *pinfo) |
| 145 | { |
| 146 | uint32_t smp_cnt = 0, reg_rgb0 = 0, reg_rgb1 = 0, shift = 0; |
| 147 | uint32_t xres, bpp; |
| 148 | |
| 149 | xres = pinfo->xres; |
| 150 | bpp = pinfo->bpp; |
| 151 | |
| 152 | if (pinfo->lcdc.dual_pipe) { |
| 153 | /* Each pipe driving half the screen */ |
| 154 | xres /= 2; |
| 155 | } |
| 156 | |
| 157 | smp_cnt = ((xres) * (bpp / 8) * 2) + |
| 158 | MMSS_MDP_MAX_SMP_SIZE - 1; |
| 159 | |
| 160 | smp_cnt /= MMSS_MDP_MAX_SMP_SIZE; |
| 161 | |
| 162 | if (smp_cnt > 4) { |
| 163 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 164 | smp_cnt); |
| 165 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 166 | } |
| 167 | |
| 168 | writel(smp_cnt * 0x40, RGB0_REQPRIORITY_FIFO_WATERMARK0); |
| 169 | writel(smp_cnt * 0x80, RGB0_REQPRIORITY_FIFO_WATERMARK1); |
| 170 | writel(smp_cnt * 0xc0, RGB0_REQPRIORITY_FIFO_WATERMARK2); |
| 171 | |
| 172 | if (pinfo->lcdc.dual_pipe) { |
| 173 | writel(smp_cnt * 0x40, RGB1_REQPRIORITY_FIFO_WATERMARK0); |
| 174 | writel(smp_cnt * 0x80, RGB1_REQPRIORITY_FIFO_WATERMARK1); |
| 175 | writel(smp_cnt * 0xc0, RGB1_REQPRIORITY_FIFO_WATERMARK2); |
| 176 | } |
| 177 | |
| 178 | while((smp_cnt > 0) && !(shift > 16)) { |
| 179 | reg_rgb0 |= ((MMSS_MDP_CLIENT_ID_RGB0) << (shift)); |
| 180 | reg_rgb1 |= ((MMSS_MDP_CLIENT_ID_RGB1) << (shift)); |
| 181 | smp_cnt--; |
| 182 | shift += 8; |
| 183 | } |
| 184 | |
| 185 | /* Allocate SMP blocks */ |
| 186 | writel(reg_rgb0, MMSS_MDP_SMP_ALLOC_W_0); |
| 187 | writel(reg_rgb0, MMSS_MDP_SMP_ALLOC_R_0); |
| 188 | |
| 189 | if (pinfo->lcdc.dual_pipe) { |
| 190 | writel(reg_rgb1, MMSS_MDP_SMP_ALLOC_W_1); |
| 191 | writel(reg_rgb1, MMSS_MDP_SMP_ALLOC_R_1); |
| 192 | } |
| 193 | } |
| 194 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 195 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 196 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 197 | uint32_t hsync_period, vsync_period; |
| 198 | uint32_t hsync_start_x, hsync_end_x; |
| 199 | uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 200 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 201 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 202 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 203 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 204 | |
| 205 | if (pinfo == NULL) |
| 206 | return ERR_INVALID_ARGS; |
| 207 | |
| 208 | lcdc = &(pinfo->lcdc); |
| 209 | if (lcdc == NULL) |
| 210 | return ERR_INVALID_ARGS; |
| 211 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 212 | adjust_xres = pinfo->xres; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 213 | if (pinfo->lcdc.dual_pipe) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 214 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 215 | if (intf_base == MDP_INTF_1_BASE) { |
| 216 | writel(BIT(8), MDP_TG_SINK); |
| 217 | writel(0x0, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 218 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 223 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 224 | hsync_period = lcdc->h_pulse_width + |
| 225 | lcdc->h_back_porch + |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 226 | adjust_xres + lcdc->xres_pad + lcdc->h_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 227 | vsync_period = (lcdc->v_pulse_width + |
| 228 | lcdc->v_back_porch + |
| 229 | pinfo->yres + lcdc->yres_pad + |
| 230 | lcdc->v_front_porch); |
| 231 | |
| 232 | hsync_start_x = |
| 233 | lcdc->h_pulse_width + |
| 234 | lcdc->h_back_porch; |
| 235 | hsync_end_x = |
| 236 | hsync_period - lcdc->h_front_porch - 1; |
| 237 | |
| 238 | display_vstart = (lcdc->v_pulse_width + |
| 239 | lcdc->v_back_porch) |
| 240 | * hsync_period + lcdc->hsync_skew; |
| 241 | display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period) |
| 242 | +lcdc->hsync_skew - 1; |
| 243 | |
| 244 | hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width; |
| 245 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 246 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 247 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 248 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 249 | mdss_mdp_intf_off); |
| 250 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
| 251 | writel(lcdc->v_pulse_width*hsync_period, |
| 252 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 253 | mdss_mdp_intf_off); |
| 254 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 255 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 256 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 257 | mdss_mdp_intf_off); |
| 258 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 259 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 260 | mdss_mdp_intf_off); |
| 261 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 262 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 263 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 264 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 265 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 266 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 267 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 268 | |
| 269 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 270 | |
| 271 | } |
| 272 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 273 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 274 | *pinfo) |
| 275 | { |
| 276 | uint32_t mdp_rgb_size, height, width; |
| 277 | |
| 278 | height = (fb->height << 16); |
| 279 | width = fb->width; |
| 280 | |
| 281 | if (pinfo->lcdc.dual_pipe) |
| 282 | width /= 2; |
| 283 | |
| 284 | /* write active region size*/ |
| 285 | mdp_rgb_size = (height << 16) | width; |
| 286 | |
| 287 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 288 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 289 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 290 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 291 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 292 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 293 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 294 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 295 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 296 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 297 | |
| 298 | /* Baselayer for layer mixer 0 */ |
| 299 | writel(0x0000200, MDP_CTL_0_BASE + CTL_LAYER_0); |
| 300 | |
| 301 | if (pinfo->lcdc.dual_pipe) { |
| 302 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 303 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 304 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 305 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 306 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 307 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 308 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 309 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 310 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 311 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 312 | |
| 313 | /* Baselayer for layer mixer 0 */ |
| 314 | writel(0x04000, MDP_CTL_1_BASE + CTL_LAYER_1); |
| 315 | } |
| 316 | } |
| 317 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 318 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 319 | struct fbcon_config *fb) |
| 320 | { |
| 321 | int ret = NO_ERROR; |
| 322 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 323 | uint32_t intf_sel = 0x100; |
| 324 | |
| 325 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
| 326 | |
| 327 | if (pinfo->mipi.dual_dsi) |
| 328 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 329 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 330 | mdp_clk_gating_ctrl(); |
| 331 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 332 | mdss_vbif_setup(); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 333 | mdss_smp_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 334 | |
| 335 | writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0); |
| 336 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 337 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); |
| 338 | if (pinfo->lcdc.dual_pipe) |
| 339 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 340 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 341 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 342 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 343 | writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 344 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 345 | if (pinfo->mipi.dual_dsi) { |
| 346 | writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 347 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 348 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 349 | |
| 350 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 351 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 352 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 353 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 354 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 355 | |
| 356 | return 0; |
| 357 | } |
| 358 | |
| 359 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 360 | struct fbcon_config *fb) |
| 361 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 362 | int ret = NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 363 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 364 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 365 | uint32_t mdss_mdp_intf_off = 0; |
| 366 | |
| 367 | if (pinfo == NULL) |
| 368 | return ERR_INVALID_ARGS; |
| 369 | |
| 370 | lcdc = &(pinfo->lcdc); |
| 371 | if (lcdc == NULL) |
| 372 | return ERR_INVALID_ARGS; |
| 373 | |
| 374 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 375 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 376 | mdp_clk_gating_ctrl(); |
| 377 | |
| 378 | writel(0x0100, MDP_DISP_INTF_SEL); |
| 379 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 380 | mdss_vbif_setup(); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 381 | mdss_smp_setup(pinfo); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 382 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 383 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 384 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 385 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 386 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 387 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 388 | writel(0x20020, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 389 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 390 | return ret; |
| 391 | } |
| 392 | |
| 393 | int mdp_dsi_video_on(void) |
| 394 | { |
| 395 | int ret = NO_ERROR; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 396 | writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH); |
| 397 | writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 398 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 399 | return ret; |
| 400 | } |
| 401 | |
| 402 | int mdp_dsi_video_off() |
| 403 | { |
| 404 | if(!target_cont_splash_screen()) |
| 405 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 406 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 407 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 408 | mdelay(60); |
| 409 | /* Ping-Pong done Tear Check Read/Write */ |
| 410 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 411 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 412 | } |
| 413 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 414 | writel(0x00000000, MDP_INTR_EN); |
| 415 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 416 | return NO_ERROR; |
| 417 | } |
| 418 | |
| 419 | int mdp_dsi_cmd_off() |
| 420 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 421 | if(!target_cont_splash_screen()) |
| 422 | { |
| 423 | /* Ping-Pong done Tear Check Read/Write */ |
| 424 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 425 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 426 | } |
| 427 | writel(0x00000000, MDP_INTR_EN); |
| 428 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 429 | return NO_ERROR; |
| 430 | } |
| 431 | |
| 432 | int mdp_dma_on(void) |
| 433 | { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 434 | writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH); |
| 435 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 436 | return NO_ERROR; |
| 437 | } |
| 438 | |
| 439 | void mdp_disable(void) |
| 440 | { |
| 441 | |
| 442 | } |