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gerrit-public.fairphone.software / kernel / lk / 74ed8350469de1a4dcd45d0a6b8dd51740a02add / . / platform / msm_shared / include / sdhci.h
blob: ff618681699cd5e006d4b2485c705a6485d23565 [file] [log] [blame]
Channagoud Kadabi74ed8352013-03-11 13:12:05 -0700[diff] [blame^]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __PLATFORM_SDHCI_H_
30#define __PLATFORM_SDHCI_H_
31
32#include <reg.h>
33#include <bits.h>
34
35/*
36 * Capabilities for the host controller
37 * These values are read from the capabilities
38 * register in the controller
39 */
40struct host_caps {
41 uint32_t base_clk_rate; /* Max clock rate supported */
42 uint32_t max_blk_len; /* Max block len supported */
43 uint8_t bus_width_8bit; /* 8 Bit mode supported */
44 uint8_t adma_support; /* Adma support */
45 uint8_t voltage; /* Supported voltage */
46 uint8_t sdr_support; /* Single Data rate */
47 uint8_t ddr_support; /* Dual Data rate */
48 uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
49};
50
51/*
52 * sdhci host structure, holding information about host
53 * controller parameters
54 */
55struct sdhci_host {
56 uint32_t base; /* Base address for the host */
57 uint32_t cur_clk_rate; /* Running clock rate */
58 struct host_caps caps; /* Host capabilities */
59};
60
61/*
62 * Data pointer to be read/written
63 */
64struct mmc_data {
65 void *data_ptr; /* Points to stream of data */
66 uint32_t num_blocks; /* num of blocks, each always of size SDHCI_MMC_BLK_SZ */
67};
68
69/*
70 * mmc command structure as per the spec
71 */
72struct mmc_command {
73 uint16_t cmd_index; /* Command index */
74 uint32_t argument; /* Command argument */
75 uint8_t data_present; /* Command has data */
76 uint8_t cmd_type; /* command type */
77 uint16_t resp_type; /* Response type of the command */
78 uint32_t resp[4]; /* 128 bit response value */
79 uint32_t trans_mode; /* Transfer mode, read/write */
80 uint32_t cmd_retry; /* Retry the command, if card is busy */
81 struct mmc_data data; /* Data pointer */
82};
83
84/*
85 * Descriptor table for adma
86 */
87struct desc_entry {
88 uint16_t tran_att; /* Attribute for transfer data */
89 uint16_t len; /* Length of data */
90 void *addr; /* Address of the data */
91};
92
93/*
94 * Command types for sdhci
95 */
96enum {
97 SDHCI_CMD_TYPE_NORMAL = 0,
98 SDHCI_CMD_TYPE_SUSPEND,
99 SDHCI_CMD_TYPE_RESUME,
100 SDHCI_CMD_TYPE_ABORT,
101} sdhci_cmd_type;
102
103/*
104 * Response type values for sdhci
105 */
106enum {
107 SDHCI_CMD_RESP_NONE = 0,
108 SDHCI_CMD_RESP_136,
109 SDHCI_CMD_RESP_48,
110 SDHCI_CMD_RESP_48_BUSY,
111} sdhci_resp_type;
112
113
114/*
115 * Helper macros for writing byte, word & long registers
116 */
117#define REG_READ8(host, a) readb(host->base + a);
118#define REG_WRITE8(host, v, a) writeb(v, (host->base + a))
119
120#define REG_READ32(host, a) readl(host->base + a)
121#define REG_WRITE32(host, v, a) writel(v, (host->base + a))
122
123#define REG_READ16(host, a) readhw(host->base + a)
124#define REG_WRITE16(host, v, a) writehw(v, (host->base + a))
125
126/*
127 * SDHCI registers, as per the host controller spec v 3.0
128 */
129#define SDHCI_ARG2_REG (0x000)
130#define SDHCI_BLKSZ_REG (0x004)
131#define SDHCI_BLK_CNT_REG (0x006)
132#define SDHCI_ARGUMENT_REG (0x008)
133#define SDHCI_TRANS_MODE_REG (0x00C)
134#define SDHCI_CMD_REG (0x00E)
135#define SDHCI_RESP_REG (0x010)
136#define SDHCI_PRESENT_STATE_REG (0x024)
137#define SDHCI_HOST_CTRL1_REG (0x028)
138#define SDHCI_PWR_CTRL_REG (0x029)
139#define SDHCI_CLK_CTRL_REG (0x02C)
140#define SDHCI_TIMEOUT_REG (0x02E)
141#define SDHCI_RESET_REG (0x02F)
142#define SDHCI_NRML_INT_STS_REG (0x030)
143#define SDHCI_ERR_INT_STS_REG (0x032)
144#define SDHCI_NRML_INT_STS_EN_REG (0x034)
145#define SDHCI_ERR_INT_STS_EN_REG (0x036)
146#define SDHCI_NRML_INT_SIG_EN_REG (0x038)
147#define SDHCI_ERR_INT_SIG_EN_REG (0x03A)
148#define SDHCI_HOST_CTRL2_REG (0x03E)
149#define SDHCI_CAPS_REG1 (0x040)
150#define SDHCI_CAPS_REG2 (0x044)
151#define SDHCI_ADM_ADDR_REG (0x058)
152
153/*
154 * Helper macros for register writes
155 */
156#define SDHCI_SOFT_RESET BIT(0)
157#define SOFT_RESET_CMD BIT(1)
158#define SOFT_RESET_DATA BIT(2)
159#define SDHCI_1_8_VOL_SET BIT(3)
160
161/*
162 * Interrupt related
163 */
164#define SDHCI_NRML_INT_STS_EN 0x000B
165#define SDHCI_ERR_INT_STS_EN 0xFFFF
166#define SDHCI_NRML_INT_SIG_EN 0x000B
167#define SDHCI_ERR_INT_SIG_EN 0xFFFF
168
169#define SDCC_HC_INT_CARD_REMOVE BIT(7)
170#define SDCC_HC_INT_CARD_INSERT BIT(6)
171
172/*
173 * HC mode enable/disable
174 */
175#define SDHCI_HC_MODE_EN BIT(0)
176#define SDHCI_HC_MODE_DIS (0 << 1)
177
178/*
179 * Clk control related
180 */
181#define SDHCI_CLK_MAX_DIV 2046
182#define SDHCI_SDCLK_FREQ_SEL 8
183#define SDHCI_SDCLK_UP_BIT_SEL 6
184#define SDHCI_SDCLK_FREQ_MASK 0xFF
185#define SDHC_SDCLK_UP_BIT_MASK 0x300
186#define SDHCI_INT_CLK_EN BIT(0)
187#define SDHCI_CLK_STABLE_MASK BIT(1)
188#define SDHCI_CLK_STABLE BIT(1)
189#define SDHCI_CLK_EN BIT(2)
190#define SDHCI_CLK_DIS (0 << 2)
191#define SDHCI_CLK_RATE_MASK 0x0000FF00
192#define SDHCI_CLK_RATE_BIT 8
193
194#define SDHCI_CMD_ACT BIT(0)
195#define SDHCI_DAT_ACT BIT(1)
196
197/*
198 * Bus voltage related macros
199 */
200#define SDHCI_BUS_VOL_SEL 1
201#define SDHCI_BUS_PWR_EN BIT(0)
202#define SDHCI_VOL_1_8 5
203#define SDHCI_VOL_3_0 6
204#define SDHCI_VOL_3_3 7
205#define SDHCI_3_3_VOL_MASK 0x01000000
206#define SDHCI_3_0_VOL_MASK 0x02000000
207#define SDHCI_1_8_VOL_MASK 0x04000000
208
209/*
210 * Bus width related macros
211 */
212#define SDHCI_8BIT_WIDTH_MASK 0x00040000
213
214#define SDHCI_BUS_WITDH_1BIT (0)
215#define SDHCI_BUS_WITDH_4BIT BIT(1)
216#define SDHCI_BUS_WITDH_8BIT BIT(5)
217
218/*
219 * Adma related macros
220 */
221#define SDHCI_BLK_LEN_MASK 0x00030000
222#define SDHCI_BLK_LEN_BIT 16
223#define SDHCI_BLK_ADMA_MASK 0x00080000
224#define SDHCI_INT_STS_TRANS_COMPLETE BIT(1)
225#define SDHCI_STATE_CMD_DAT_MASK 0x0003
226#define SDHCI_INT_STS_CMD_COMPLETE BIT(0)
227#define SDHCI_ERR_INT_STAT_MASK 0x8000
228#define SDHCI_ADMA_DESC_LINE_SZ 65536
229#define SDHCI_ADMA_MAX_TRANS_SZ (65535 * 512)
230#define SDHCI_ADMA_TRANS_VALID BIT(0)
231#define SDHCI_ADMA_TRANS_END BIT(1)
232#define SDHCI_ADMA_TRANS_DATA BIT(5)
233#define SDHCI_MMC_BLK_SZ 512
234#define SDHCI_MMC_CUR_BLK_CNT_BIT 16
235#define SDHCI_MMC_BLK_SZ_BIT 0
236#define SDHCI_TRANS_MULTI BIT(5)
237#define SDHCI_TRANS_SINGLE (0 << 5)
238#define SDHCI_BLK_CNT_EN BIT(1)
239#define SDHCI_DMA_EN BIT(0)
240#define SDHCI_AUTO_CMD23_EN BIT(3)
241#define SDHCI_ADMA_32BIT BIT(4)
242
243/*
244 * Command related macros
245 */
246#define SDHCI_CMD_RESP_TYPE_SEL_BIT 0
247#define SDHCI_CMD_CRC_CHECK_BIT 3
248#define SDHCI_CMD_IDX_CHECK_BIT 4
249#define SDHCI_CMD_DATA_PRESENT_BIT 5
250#define SDHCI_CMD_CMD_TYPE_BIT 6
251#define SDHCI_CMD_CMD_IDX_BIT 8
252#define SDHCI_CMD_TIMEOUT_MASK BIT(0)
253#define SDHCI_CMD_CRC_MASK BIT(1)
254#define SDHCI_CMD_END_BIT_MASK BIT(2)
255#define SDHCI_CMD_IDX_MASK BIT(3)
256#define SDHCI_DAT_TIMEOUT_MASK BIT(4)
257#define SDHCI_DAT_CRC_MASK BIT(5)
258#define SDHCI_DAT_END_BIT_MASK BIT(6)
259#define SDHCI_CUR_LIM_MASK BIT(7)
260#define SDHCI_AUTO_CMD12_MASK BIT(8)
261#define SDHCI_ADMA_MASK BIT(9)
262#define SDHCI_READ_MODE BIT(4)
263#define SDHCI_SWITCH_CMD 6
264#define SDHCI_CMD_TIMEOUT 0xE
265#define SDHCI_MAX_CMD_RETRY 10000
266#define SDHCI_MAX_TRANS_RETRY 100000
267
268#define SDHCI_PREP_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
269
270/*
271 * command response related
272 */
273#define SDHCI_RESP_LSHIFT 8
274#define SDHCI_RESP_RSHIFT 24
275
276/*
277 * Power control relatd macros
278 */
279#define SDHCI_SOFT_RESET_MASK (BIT(0) | BIT(1) | BIT(2))
280#define SDCC_HC_PWR_CTRL_INT 0xF
281#define SDCC_HC_BUS_ON BIT(0)
282#define SDCC_HC_BUS_OFF BIT(1)
283#define SDCC_HC_BUS_ON_OFF_SUCC BIT(0)
284#define SDCC_HC_IO_SIG_LOW BIT(2)
285#define SDCC_HC_IO_SIG_HIGH BIT(3)
286#define SDCC_HC_IO_SIG_SUCC BIT(2)
287
288/*
289 * Command response
290 */
291#define SDHCI_CMD_RESP_NONE 0
292#define SDHCI_CMD_RESP_R1 BIT(0)
293#define SDHCI_CMD_RESP_R1B BIT(1)
294#define SDHCI_CMD_RESP_R2 BIT(2)
295#define SDHCI_CMD_RESP_R3 BIT(3)
296#define SDHCI_CMD_RESP_R6 BIT(6)
297#define SDHCI_CMD_RESP_R7 BIT(7)
298
299/*
300 * Clock Divider values
301 */
302#define SDHCI_CLK_400KHZ 400000
303#define SDHCI_CLK_25MHZ 25000000
304#define SDHCI_CLK_50MHZ 50000000
305#define SDHCI_CLK_100MHZ 100000000
306#define SDHCI_CLK_200MHZ 200000000
307
308/* DDR mode related macros */
309#define SDHCI_DDR_MODE_EN 0x0004
310#define SDHCI_DDR_MODE_MASK BIT(2)
311
312/* HS200/SDR50 mode related macros */
313#define SDHCI_SDR50_MODE_MASK BIT(0)
314#define SDHCI_SDR50_MODE_EN 0x0002
315
316/*
317 * APIs and macros exposed for mmc/sd drivers
318 */
319#define SDHCI_MMC_WRITE 0
320#define SDHCI_MMC_READ 1
321
322#define DATA_BUS_WIDTH_1BIT 0
323#define DATA_BUS_WIDTH_4BIT 1
324#define DATA_BUS_WIDTH_8BIT 2
325#define DATA_DDR_BUS_WIDTH_4BIT 5
326#define DATA_DDR_BUS_WIDTH_8BIT 6
327
328/* API: to initialize the controller */
329void sdhci_init(struct sdhci_host *);
330/* API: Send the command & transfer data using adma */
331uint32_t sdhci_send_command(struct sdhci_host *, struct mmc_command *);
332/* API: Set the bus width for the contoller */
333uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t);
334/* API: Clock supply for the controller */
335uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t);
336/* API: Enable DDR mode */
337void sdhci_set_ddr_mode(struct sdhci_host *);
338/* API: To enable SDR mode */
339void sdhci_set_sdr_mode(struct sdhci_host *);
340#endif