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gerrit-public.fairphone.software / kernel / lk / 78ae67578356709ac9fea23196e8fdc2efc6c6bb / . / platform / msm_shared / include / mipi_dsi.h
blob: f6c7e73cc5c04ae2fbab38193b5e9bdf0f42487e [file] [log] [blame]
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700[diff] [blame^]1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_
31#define _PLATFORM_MSM_SHARED_MIPI_DSI_H_
32
33#define PASS 0
34#define FAIL 1
35
36#define DSI_CLKOUT_TIMING_CTRL (0x047000C0)
37#define MMSS_DSI_PIXEL_MD (0x04000134)
38#define MMSS_DSI_PIXEL_NS (0x04000138)
39#define MMSS_DSI_PIXEL_CC (0x04000130)
40#define MMSS_DSI_CC (0x0400004C)
41#define MMSS_DSI_MD (0x04000050)
42#define MMSS_DSI_NS (0x04000054)
43#define MMSS_MISC_CC2 (0x0400005C)
44#define MMSS_MISC_CC (0x04000058)
45#define DSI_PHY_SW_RESET (0x04700128)
46#define DSI_SOFT_RESET (0x04700114)
47#define DSI_CAL_CTRL (0x047000F4)
48
49#define DSIPHY_REGULATOR_CTRL_0 (0x047002CC)
50#define DSIPHY_REGULATOR_CTRL_1 (0x047002D0)
51#define DSIPHY_REGULATOR_CTRL_2 (0x047002D4)
52#define DSIPHY_REGULATOR_CTRL_3 (0x047002D8)
53
54#define DSIPHY_TIMING_CTRL_0 (0x04700260)
55#define DSIPHY_TIMING_CTRL_1 (0x04700264)
56#define DSIPHY_TIMING_CTRL_2 (0x04700268)
57#define DSIPHY_TIMING_CTRL_3 (0x0470026C)
58#define DSIPHY_TIMING_CTRL_4 (0x04700270)
59#define DSIPHY_TIMING_CTRL_5 (0x04700274)
60#define DSIPHY_TIMING_CTRL_6 (0x04700278)
61#define DSIPHY_TIMING_CTRL_7 (0x0470027C)
62#define DSIPHY_TIMING_CTRL_8 (0x04700280)
63#define DSIPHY_TIMING_CTRL_9 (0x04700284)
64#define DSIPHY_TIMING_CTRL_10 (0x04700288)
65
66#define DSIPHY_CTRL_0 (0x04700290)
67#define DSIPHY_CTRL_1 (0x04700294)
68#define DSIPHY_CTRL_2 (0x04700298)
69#define DSIPHY_CTRL_3 (0x0470029C)
70
71#define DSIPHY_STRENGTH_CTRL_0 (0x047002A0)
72#define DSIPHY_STRENGTH_CTRL_1 (0x047002A4)
73#define DSIPHY_STRENGTH_CTRL_2 (0x047002A8)
74#define DSIPHY_STRENGTH_CTRL_3 (0x047002AC)
75
76#define DSIPHY_PLL_CTRL_0 (0x04700200)
77#define DSIPHY_PLL_CTRL_1 (0x04700204)
78#define DSIPHY_PLL_CTRL_2 (0x04700208)
79#define DSIPHY_PLL_CTRL_3 (0x0470020C)
80#define DSIPHY_PLL_CTRL_4 (0x04700210)
81#define DSIPHY_PLL_CTRL_5 (0x04700214)
82#define DSIPHY_PLL_CTRL_6 (0x04700218)
83#define DSIPHY_PLL_CTRL_7 (0x0470021C)
84#define DSIPHY_PLL_CTRL_8 (0x04700220)
85#define DSIPHY_PLL_CTRL_9 (0x04700224)
86#define DSIPHY_PLL_CTRL_10 (0x04700228)
87#define DSIPHY_PLL_CTRL_11 (0x0470022C)
88#define DSIPHY_PLL_CTRL_12 (0x04700230)
89#define DSIPHY_PLL_CTRL_13 (0x04700234)
90#define DSIPHY_PLL_CTRL_14 (0x04700238)
91#define DSIPHY_PLL_CTRL_15 (0x0470023C)
92#define DSIPHY_PLL_CTRL_16 (0x04700240)
93#define DSIPHY_PLL_CTRL_17 (0x04700244)
94#define DSIPHY_PLL_CTRL_18 (0x04700248)
95#define DSIPHY_PLL_CTRL_19 (0x0470024C)
96
97#define DSI_CMD_DMA_MEM_START_ADDR_PANEL (0x46000000)
98
99#define DSI_CLK_CTRL (0x04700118)
100#define DSI_TRIG_CTRL (0x04700080)
101#define DSI_CTRL (0x04700000)
102#define DSI_COMMAND_MODE_DMA_CTRL (0x04700038)
103#define DSI_DMA_CMD_OFFSET (0x04700044)
104#define DSI_DMA_CMD_LENGTH (0x04700048)
105#define DSI_COMMAND_MODE_DMA_CTRL (0x04700038)
106#define DSI_ERR_INT_MASK0 (0x04700108)
107#define DSI_INT_CTRL (0x0470010C)
108
109#define DSI_VIDEO_MODE_ACTIVE_H (0x04700020)
110#define DSI_VIDEO_MODE_ACTIVE_V (0x04700024)
111#define DSI_VIDEO_MODE_TOTAL (0x04700028)
112#define DSI_VIDEO_MODE_HSYNC (0x0470002C)
113#define DSI_VIDEO_MODE_VSYNC (0x04700030)
114#define DSI_VIDEO_MODE_VSYNC_VPOS (0x04700034)
115
116#define DSI_MISR_VIDEO_CTRL (0x047000A0)
117#define DSI_EOT_PACKET_CTRL (0x047000C8)
118#define DSI_VIDEO_MODE_CTRL (0x0470000C)
119#define DSI_CAL_STRENGTH_CTRL (0x04700100)
120#define DSI_CMD_MODE_DMA_SW_TRIGGER (0x0470008C)
121
122#define MDP_AXI_RDMASTER_CONFIG (0x05100028)
123#define MDP_AXI_WRMASTER_CONFIG (0x05100030)
124#define MDP_MAX_RD_PENDING_CMD_CONFIG (0x0510004C)
125#define MDP_DISP_INTF_SEL (0x05100038)
126#define MDP_OVERLAYPROC0_CFG (0x05110004)
127#define MDP_DMA_P_CONFIG (0x05190000)
128#define MDP_DMA_P_OUT_XY (0x05190010)
129#define MDP_DMA_P_SIZE (0x05190004)
130#define MDP_DMA_P_BUF_ADDR (0x05190008)
131#define MDP_DMA_P_BUF_Y_STRIDE (0x0519000C)
132#define MDP_DMA_P_OP_MODE (0x05190070)
133#define MDP_DSI_VIDEO_EN (0x051E0000)
134#define MDP_DSI_VIDEO_HSYNC_CTL (0x051E0004)
135#define MDP_DSI_VIDEO_VSYNC_PERIOD (0x051E0008)
136#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH (0x051E000C)
137#define MDP_DSI_VIDEO_DISPLAY_HCTL (0x051E0010)
138#define MDP_DSI_VIDEO_DISPLAY_V_START (0x051E0014)
139#define MDP_DSI_VIDEO_DISPLAY_V_END (0x051E0018)
140#define MDP_DSI_VIDEO_BORDER_CLR (0x051E0028)
141#define MDP_DSI_VIDEO_HSYNC_SKEW (0x051E0030)
142#define MDP_DSI_VIDEO_CTL_POLARITY (0x051E0038)
143#define MDP_DSI_VIDEO_TEST_CTL (0x051E0034)
144
145#define MDP_TEST_MODE_CLK (0x051F0000)
146#define MDP_INTR_STATUS (0x05100054)
147#define MMSS_SFPB_GPREG (0x05700058)
148
149//BEGINNING OF Tochiba Config- video mode
150
151static const unsigned char dsi_toshiba_display_config_MCAP_off[8] = {
152 0x02, 0x00, 0x29, 0xc0,
153 0xb2, 0x00, 0xff, 0xff
154};
155
156static const unsigned char dsi_toshiba_display_config_ena_test_reg[8] = {
157 0x03, 0x00, 0x29, 0xc0,
158 0xEF, 0x01, 0x01, 0xff
159};
160
161static const unsigned char dsi_toshiba_display_config_ena_test_reg_wvga[8] = {
162 0x03, 0x00, 0x29, 0xc0,
163 0xEF, 0x01, 0x01, 0xff
164};
165
166static const unsigned char dsi_toshiba_display_config_num_of_2lane[8] = {
167 0x03, 0x00, 0x29, 0xc0, // 63:2lane
168 0xEF, 0x60, 0x63, 0xff
169};
170
171static const unsigned char dsi_toshiba_display_config_num_of_1lane[8] = {
172 0x03, 0x00, 0x29, 0xc0, // 62:1lane
173 0xEF, 0x60, 0x62, 0xff
174};
175
176static const unsigned char dsi_toshiba_display_config_non_burst_sync_pulse[8] = {
177 0x03, 0x00, 0x29, 0xc0,
178 0xef, 0x61, 0x09, 0xff
179};
180
181static const unsigned char dsi_toshiba_display_config_set_DMODE_WQVGA[8] = {
182 0x02, 0x00, 0x29, 0xc0,
183 0xB3, 0x01, 0xFF, 0xff
184};
185
186static const unsigned char dsi_toshiba_display_config_set_DMODE_WVGA[8] = {
187 0x02, 0x00, 0x29, 0xc0,
188 0xB3, 0x00, 0xFF, 0xff
189};
190
191static const unsigned char dsi_toshiba_display_config_set_intern_WR_clk1_wvga[8]
192 = {
193
194 0x03, 0x00, 0x29, 0xC0, // 1 last packet
195 0xef, 0x2f, 0xcc, 0xff,
196};
197
198static const unsigned char dsi_toshiba_display_config_set_intern_WR_clk2_wvga[8]
199 = {
200
201 0x03, 0x00, 0x29, 0xC0, // 1 last packet
202 0xef, 0x6e, 0xdd, 0xff,
203};
204
205static const unsigned char
206 dsi_toshiba_display_config_set_intern_WR_clk1_wqvga[8] = {
207
208 0x03, 0x00, 0x29, 0xC0, // 1 last packet
209 0xef, 0x2f, 0x22, 0xff,
210};
211
212static const unsigned char
213 dsi_toshiba_display_config_set_intern_WR_clk2_wqvga[8] = {
214
215 0x03, 0x00, 0x29, 0xC0, // 1 last packet
216 0xef, 0x6e, 0x33, 0xff,
217};
218
219static const unsigned char dsi_toshiba_display_config_set_hor_addr_2A_wvga[12] = {
220
221 0x05, 0x00, 0x39, 0xC0, // 1 last packet
222 // 0x2A, 0x00, 0x08, 0x00,//100 = 64h
223 // 0x6b, 0xFF, 0xFF, 0xFF,
224 0x2A, 0x00, 0x00, 0x01, // 0X1DF = 480-1 0X13F = 320-1
225 0xdf, 0xFF, 0xFF, 0xFF,
226};
227
228static const unsigned char dsi_toshiba_display_config_set_hor_addr_2B_wvga[12] = {
229
230 0x05, 0x00, 0x39, 0xC0, // 1 last packet
231 // 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1
232 // 0x6b, 0xFF, 0xFF, 0xFF,
233 0x2B, 0x00, 0x00, 0x03, // 0X355 = 854-1; 0X1DF = 480-1
234 0x55, 0xFF, 0xFF, 0xFF,
235};
236
237static const unsigned char dsi_toshiba_display_config_set_hor_addr_2A_wqvga[12]
238 = {
239
240 0x05, 0x00, 0x39, 0xC0, // 1 last packet
241 0x2A, 0x00, 0x00, 0x00, // 0XEF = 240-1
242 0xef, 0xFF, 0xFF, 0xFF,
243};
244
245static const unsigned char dsi_toshiba_display_config_set_hor_addr_2B_wqvga[12]
246 = {
247
248 0x05, 0x00, 0x39, 0xC0, // 1 last packet
249 0x2B, 0x00, 0x00, 0x01, // 0X1aa = 427-1;
250 0xaa, 0xFF, 0xFF, 0xFF,
251};
252
253static const unsigned char dsi_toshiba_display_config_IFSEL[8] = {
254 0x02, 0x00, 0x29, 0xc0,
255 0x53, 0x01, 0xff, 0xff
256};
257
258static const unsigned char dsi_toshiba_display_config_IFSEL_cmd_mode[8] = {
259 0x02, 0x00, 0x29, 0xc0,
260 0x53, 0x00, 0xff, 0xff
261};
262
263static const unsigned char dsi_toshiba_display_config_exit_sleep[4] = {
264 0x11, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
265 // params
266};
267
268static const unsigned char dsi_toshiba_display_config_display_on[4] = {
269 // 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1
270 // params
271 0x29, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
272 // params
273};
274
275//color mode off
276static const unsigned char dsi_display_config_color_mode_off[4] = {
277 0x00, 0x00, 0x02, 0x80,
278};
279
280//color mode on
281static const unsigned char dsi_display_config_color_mode_on[4] = {
282 0x00, 0x00, 0x12, 0x80,
283};
284
285//the end OF Tochiba Config- video mode
286
287#endif