| Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifndef _PLATFORM_MSM_SHARED_MDP_5_H_ |
| 31 | #define _PLATFORM_MSM_SHARED_MDP_5_H_ |
| 32 | |
| 33 | #include <msm_panel.h> |
| 34 | |
| 35 | #define MDP_VP_0_RGB_0_SSPP_SRC0_ADDR REG_MDP(0x1E14) |
| 36 | #define MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE REG_MDP(0x1E24) |
| 37 | #define MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE REG_MDP(0x1E04) |
| 38 | #define MDP_VP_0_RGB_0_SSPP_SRC_SIZE REG_MDP(0x1E00) |
| 39 | #define MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE REG_MDP(0x1E0C) |
| 40 | #define MDP_VP_0_RGB_0_SSPP_SRC_XY REG_MDP(0x1E08) |
| 41 | #define MDP_VP_0_RGB_0_SSPP_OUT_XY REG_MDP(0x1E10) |
| 42 | #define MDP_VP_0_RGB_0_SSPP_SRC_FORMAT REG_MDP(0x1E30) |
| 43 | #define MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN REG_MDP(0x1E34) |
| 44 | #define MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE REG_MDP(0x1E38) |
| 45 | |
| 46 | #define MDP_VP_0_LAYER_0_OUT_SIZE REG_MDP(0x3204) |
| 47 | #define MDP_VP_0_LAYER_0_OP_MODE REG_MDP(0x3200) |
| 48 | #define MDP_VP_0_LAYER_0_BLEND_OP REG_MDP(0x3220) |
| 49 | #define MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA REG_MDP(0x3224) |
| 50 | #define MDP_VP_0_LAYER_1_BLEND_OP REG_MDP(0x3250) |
| 51 | #define MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA REG_MDP(0x3254) |
| 52 | #define MDP_VP_0_LAYER_2_BLEND_OP REG_MDP(0x3280) |
| 53 | #define MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA REG_MDP(0x3284) |
| 54 | #define MDP_VP_0_LAYER_3_BLEND_OP REG_MDP(0x32B0) |
| 55 | #define MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA REG_MDP(0x32B4) |
| 56 | |
| 57 | #define MDP_INTR_EN REG_MDP(0x0110) |
| 58 | #define MDP_INTR_CLEAR REG_MDP(0x0118) |
| 59 | #define MDP_HIST_INTR_EN REG_MDP(0x011C) |
| 60 | |
| 61 | #define MDP_DISP_INTF_SEL REG_MDP(0x0104) |
| 62 | #define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x03E0) |
| 63 | #define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x02EC) |
| 64 | #define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x04F8) |
| 65 | |
| 66 | #define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x21300) |
| 67 | |
| 68 | #define MDP_CTL_0_LAYER_0 REG_MDP(0x600) |
| 69 | #define MDP_CTL_0_TOP REG_MDP(0x614) |
| 70 | #define MDP_CTL_0_FLUSH REG_MDP(0x618) |
| 71 | |
| 72 | #define MDP_INTF_1_HSYNC_CTL REG_MDP(0x21308) |
| 73 | #define MDP_INTF_1_VSYNC_PERIOD_F0 REG_MDP(0x2130C) |
| 74 | #define MDP_INTF_1_VSYNC_PERIOD_F1 REG_MDP(0x21310) |
| 75 | #define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 REG_MDP(0x21314) |
| 76 | #define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 REG_MDP(0x21318) |
| 77 | #define MDP_INTF_1_DISPLAY_HCTL REG_MDP(0x2133C) |
| 78 | #define MDP_INTF_1_DISPLAY_V_START_F0 REG_MDP(0x2131C) |
| 79 | #define MDP_INTF_1_DISPLAY_V_START_F1 REG_MDP(0x21320) |
| 80 | #define MDP_INTF_1_DISPLAY_V_END_F0 REG_MDP(0x21324) |
| 81 | #define MDP_INTF_1_DISPLAY_V_END_F1 REG_MDP(0x21328) |
| 82 | #define MDP_INTF_1_ACTIVE_HCTL REG_MDP(0x21340) |
| 83 | #define MDP_INTF_1_ACTIVE_V_START_F0 REG_MDP(0x2132C) |
| 84 | #define MDP_INTF_1_ACTIVE_V_START_F1 REG_MDP(0x21330) |
| 85 | #define MDP_INTF_1_ACTIVE_V_END_F0 REG_MDP(0x21334) |
| 86 | #define MDP_INTF_1_ACTIVE_V_END_F1 REG_MDP(0x21338) |
| 87 | #define MDP_INTF_1_UNDERFFLOW_COLOR REG_MDP(0x21348) |
| 88 | #define MDP_INTF_1_PANEL_FORMAT REG_MDP(0x21390) |
| 89 | |
| 90 | #define MDP_CLK_CTRL0 REG_MDP(0x03AC) |
| 91 | #define MDP_CLK_CTRL1 REG_MDP(0x03B4) |
| 92 | #define MDP_CLK_CTRL2 REG_MDP(0x03BC) |
| 93 | #define MDP_CLK_CTRL3 REG_MDP(0x04A8) |
| 94 | #define MDP_CLK_CTRL4 REG_MDP(0x04B0) |
| 95 | |
| 96 | #define MMSS_MDP_SMP_ALLOC_W_0 REG_MDP(0x0180) |
| 97 | #define MMSS_MDP_SMP_ALLOC_W_1 REG_MDP(0x0184) |
| 98 | #define MMSS_MDP_SMP_ALLOC_R_0 REG_MDP(0x0230) |
| 99 | #define MMSS_MDP_SMP_ALLOC_R_1 REG_MDP(0x0234) |
| 100 | |
| 101 | #define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0x240D8) |
| 102 | |
| 103 | void mdp_set_revision(int rev); |
| 104 | int mdp_get_revision(); |
| 105 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb); |
| 106 | int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 107 | unsigned short num_of_lanes); |
| 108 | int mdp_dsi_video_on(void); |
| 109 | int mdp_dma_on(void); |
| 110 | void mdp_disable(void); |
| 111 | |
| 112 | #endif |