Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
| 34 | #include <target/display.h> |
| 35 | |
| 36 | #define MIPI_FB_ADDR 0x43E00000 |
| 37 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 38 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 39 | static struct fbcon_config mipi_fb_cfg = { |
| 40 | .height = TSH_MIPI_FB_HEIGHT, |
| 41 | .width = TSH_MIPI_FB_WIDTH, |
| 42 | .stride = TSH_MIPI_FB_WIDTH, |
| 43 | .format = FB_FORMAT_RGB888, |
| 44 | .bpp = 24, |
| 45 | .update_start = NULL, |
| 46 | .update_done = NULL, |
| 47 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 48 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 49 | static struct fbcon_config mipi_fb_cfg = { |
| 50 | .height = NOV_MIPI_FB_HEIGHT, |
| 51 | .width = NOV_MIPI_FB_WIDTH, |
| 52 | .stride = NOV_MIPI_FB_WIDTH, |
| 53 | .format = FB_FORMAT_RGB888, |
| 54 | .bpp = 24, |
| 55 | .update_start = NULL, |
| 56 | .update_done = NULL, |
| 57 | }; |
| 58 | #else |
| 59 | static struct fbcon_config mipi_fb_cfg = { |
| 60 | .height = 0, |
| 61 | .width = 0, |
| 62 | .stride = 0, |
| 63 | .format = 0, |
| 64 | .bpp = 0, |
| 65 | .update_start = NULL, |
| 66 | .update_done = NULL, |
| 67 | }; |
| 68 | #endif |
| 69 | |
| 70 | static int cmd_mode_status = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 71 | |
| 72 | void configure_dsicore_dsiclk() |
| 73 | { |
| 74 | unsigned char mnd_mode, root_en, clk_en; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 75 | unsigned long src_sel = 0x3; // dsi_phy_pll0_src |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 76 | unsigned long pre_div_func = 0x00; // predivide by 1 |
| 77 | unsigned long pmxo_sel; |
| 78 | |
| 79 | writel(pre_div_func << 14 | src_sel, MMSS_DSI_NS); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 80 | mnd_mode = 0; // Bypass MND |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 81 | root_en = 1; |
| 82 | clk_en = 1; |
| 83 | pmxo_sel = 0; |
| 84 | |
| 85 | writel((pmxo_sel << 8) | (mnd_mode << 6), MMSS_DSI_CC); |
| 86 | writel(readl(MMSS_DSI_CC) | root_en << 2, MMSS_DSI_CC); |
| 87 | writel(readl(MMSS_DSI_CC) | clk_en, MMSS_DSI_CC); |
| 88 | } |
| 89 | |
| 90 | void configure_dsicore_byteclk(void) |
| 91 | { |
| 92 | writel(0x00400401, MMSS_MISC_CC2); // select pxo |
| 93 | } |
| 94 | |
| 95 | void configure_dsicore_pclk(void) |
| 96 | { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 97 | unsigned char mnd_mode, root_en, clk_en; |
| 98 | unsigned long src_sel = 0x3; // dsi_phy_pll0_src |
| 99 | unsigned long pre_div_func = 0x01; // predivide by 2 |
| 100 | |
| 101 | writel(pre_div_func << 12 | src_sel, MMSS_DSI_PIXEL_NS); |
| 102 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 103 | mnd_mode = 0; // Bypass MND |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 104 | root_en = 1; |
| 105 | clk_en = 1; |
| 106 | writel(mnd_mode << 6, MMSS_DSI_PIXEL_CC); |
| 107 | writel(readl(MMSS_DSI_PIXEL_CC) | root_en << 2, MMSS_DSI_PIXEL_CC); |
| 108 | writel(readl(MMSS_DSI_PIXEL_CC) | clk_en, MMSS_DSI_PIXEL_CC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 111 | int mipi_dsi_phy_ctrl_config(struct mipi_dsi_panel_config *pinfo) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 112 | { |
| 113 | |
| 114 | unsigned char lane_1 = 1; |
| 115 | unsigned char lane_2 = 2; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 116 | unsigned i; |
| 117 | unsigned off = 0; |
| 118 | struct mipi_dsi_phy_ctrl *pd; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 119 | |
| 120 | writel(0x00000001, DSI_PHY_SW_RESET); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 121 | mdelay(50); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 122 | writel(0x00000000, DSI_PHY_SW_RESET); |
| 123 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 124 | pd = (pinfo->dsi_phy_config); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 125 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 126 | off = 0x02cc; /* regulator ctrl 0 */ |
| 127 | for (i = 0; i < 4; i++) { |
| 128 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 129 | off += 4; |
| 130 | } |
| 131 | |
| 132 | off = 0x0260; /* phy timig ctrl 0 */ |
| 133 | for (i = 0; i < 11; i++) { |
| 134 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 135 | off += 4; |
| 136 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 137 | |
| 138 | // T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing length should > |
| 139 | // data lane HS timing length |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 140 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 141 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 142 | off = 0x0290; /* ctrl 0 */ |
| 143 | for (i = 0; i < 4; i++) { |
| 144 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 145 | off += 4; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 146 | } |
| 147 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 148 | off = 0x02a0; /* strength 0 */ |
| 149 | for (i = 0; i < 4; i++) { |
| 150 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 151 | off += 4; |
| 152 | } |
| 153 | |
| 154 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 155 | for (i = 1; i < 21; i++) { |
| 156 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 157 | off += 4; |
| 158 | } |
| 159 | |
| 160 | /* pll ctrl 0 */ |
| 161 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 162 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 163 | |
| 164 | return (0); |
| 165 | } |
| 166 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 167 | struct mipi_dsi_panel_config *get_panel_info(void) |
| 168 | { |
| 169 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
| 170 | return &toshiba_panel_info; |
| 171 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 172 | return &novatek_panel_info; |
| 173 | #endif |
| 174 | return NULL; |
| 175 | |
| 176 | } |
| 177 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 178 | int dsi_cmd_dma_trigger_for_panel() |
| 179 | { |
| 180 | unsigned long ReadValue; |
| 181 | unsigned long count = 0; |
| 182 | int status = 0; |
| 183 | |
| 184 | writel(0x03030303, DSI_INT_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 185 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 186 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 187 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 188 | while (ReadValue != 0x00000001) { |
| 189 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 190 | count++; |
| 191 | if (count > 0xffff) { |
| 192 | status = FAIL; |
| 193 | printf("\n\nThis command mode dma test is failed"); |
| 194 | return status; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 199 | printf |
| 200 | ("\n\nThis command mode is tested successfully, continue on next command mode test"); |
| 201 | return status; |
| 202 | } |
| 203 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 204 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 205 | { |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 206 | int ret = 0; |
| 207 | struct mipi_dsi_cmd *cm; |
| 208 | int i = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 209 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 210 | cm = cmds; |
| 211 | for (i = 0; i < count; i++) { |
| 212 | memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, (cm->payload), cm->size); |
| 213 | writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET); |
| 214 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 215 | ret += dsi_cmd_dma_trigger_for_panel(); |
| 216 | mdelay(10); |
| 217 | cm++; |
| 218 | } |
| 219 | return ret; |
| 220 | } |
| 221 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 222 | /* |
| 223 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 224 | * per transaction since it only have 4 32bits reigsters |
| 225 | * to hold data. |
| 226 | * therefore Maximum Return Packet Size need to be set to 16. |
| 227 | * any return data more than MRPS need to be break down |
| 228 | * to multiple transactions. |
| 229 | */ |
| 230 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 231 | { |
| 232 | uint32_t *lp, data; |
| 233 | char * dp; |
| 234 | int i, off, cnt; |
| 235 | int rlen, res; |
| 236 | |
| 237 | if(len <= 2) |
| 238 | rlen = 4; /* short read */ |
| 239 | else |
| 240 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 241 | |
| 242 | if (rlen > MIPI_DSI_REG_LEN) { |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | res = rlen & 0x03; |
| 247 | |
| 248 | rlen += res; /* 4 byte align */ |
| 249 | lp = (uint32_t *)(*rp); |
| 250 | |
| 251 | cnt = rlen; |
| 252 | cnt += 3; |
| 253 | cnt >>=2; |
| 254 | |
| 255 | if (cnt > 4) |
| 256 | cnt = 4; /* 4 x 32 bits registers only */ |
| 257 | |
| 258 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 259 | off += ((cnt - 1) * 4); |
| 260 | |
| 261 | for (i = 0; i < cnt; i++) { |
| 262 | data = (uint32_t)readl(MIPI_DSI_BASE + off); |
| 263 | *lp++ = ntohl(data); /* to network byte order */ |
| 264 | off -= 4; |
| 265 | } |
| 266 | |
| 267 | if(len > 2) |
| 268 | { |
| 269 | /*First 4 bytes + paded bytes will be header next len bytes would be payload*/ |
| 270 | for(i = 0; i < len; i++) |
| 271 | { |
| 272 | dp = *rp; |
| 273 | dp[i] = dp[4 + res + i]; |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | return len; |
| 278 | } |
| 279 | |
| 280 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 281 | { |
| 282 | uint32_t data; |
| 283 | int cnt = 0; |
| 284 | int err = 0; |
| 285 | |
| 286 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 287 | while (cnt < 10000) { |
| 288 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS*/ |
| 289 | if ((data & 0x0010) == 0) |
| 290 | break; |
| 291 | cnt++; |
| 292 | } |
| 293 | if(cnt == 10000) |
| 294 | err = 1; |
| 295 | return err; |
| 296 | } |
| 297 | |
| 298 | static uint32_t mipi_novatek_manufacture_id(void) |
| 299 | { |
| 300 | char rec_buf[24]; |
| 301 | char *rp = rec_buf; |
| 302 | uint32_t *lp, data; |
| 303 | |
| 304 | mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1); |
| 305 | mipi_dsi_cmds_rx(&rp, 3); |
| 306 | |
| 307 | lp = (uint32_t *)rp; |
| 308 | data = (uint32_t)*lp; |
| 309 | data = ntohl(data); |
| 310 | data = data >> 8; |
| 311 | return data; |
| 312 | } |
| 313 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 314 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 315 | { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 316 | unsigned char DMA_STREAM1 = 0; // for mdp display processor path |
| 317 | unsigned char EMBED_MODE1 = 1; // from frame buffer |
| 318 | unsigned char POWER_MODE2 = 1; // from frame buffer |
| 319 | unsigned char PACK_TYPE1 = 1; // long packet |
| 320 | unsigned char VC1 = 0; |
| 321 | unsigned char DT1 = 0; // non embedded mode |
| 322 | unsigned short WC1 = 0; // for non embedded mode only |
| 323 | int status = 0; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 324 | unsigned char DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 325 | unsigned char lane_1 = 1; |
| 326 | unsigned char lane_2 = 2; |
| 327 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 328 | switch (pinfo->num_of_lanes) { |
| 329 | default: |
| 330 | case 1: |
| 331 | DLNx_EN = 1; // 1 lane |
| 332 | break; |
| 333 | case 2: |
| 334 | DLNx_EN = 3; // 2 lane |
| 335 | break; |
| 336 | case 3: |
| 337 | DLNx_EN = 7; // 3 lane |
| 338 | break; |
| 339 | } |
| 340 | |
| 341 | writel(0x0001, DSI_SOFT_RESET); |
| 342 | writel(0x0000, DSI_SOFT_RESET); |
| 343 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 344 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); // reg:0x118 |
| 345 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 346 | // trigger 0x4; dma stream1 |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 347 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 348 | // build |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 349 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 350 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 351 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 352 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 353 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 354 | |
| 355 | return status; |
| 356 | } |
| 357 | |
| 358 | int config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height, |
| 359 | unsigned short img_width, unsigned short img_height, |
| 360 | unsigned short hsync_porch0_fp, |
| 361 | unsigned short hsync_porch0_bp, |
| 362 | unsigned short vsync_porch0_fp, |
| 363 | unsigned short vsync_porch0_bp, |
| 364 | unsigned short hsync_width, |
| 365 | unsigned short vsync_width, unsigned short dst_format, |
| 366 | unsigned short traffic_mode, |
| 367 | unsigned short datalane_num) |
| 368 | { |
| 369 | |
| 370 | unsigned char DST_FORMAT; |
| 371 | unsigned char TRAFIC_MODE; |
| 372 | unsigned char DLNx_EN; |
| 373 | // video mode data ctrl |
| 374 | int status = 0; |
| 375 | unsigned long low_pwr_stop_mode = 0; |
| 376 | unsigned char eof_bllp_pwr = 0x9; |
| 377 | unsigned char interleav = 0; |
| 378 | |
| 379 | // disable mdp first |
| 380 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
| 381 | |
| 382 | writel(0x00000000, DSI_CLK_CTRL); |
| 383 | writel(0x00000000, DSI_CLK_CTRL); |
| 384 | writel(0x00000000, DSI_CLK_CTRL); |
| 385 | writel(0x00000000, DSI_CLK_CTRL); |
| 386 | writel(0x00000002, DSI_CLK_CTRL); |
| 387 | writel(0x00000006, DSI_CLK_CTRL); |
| 388 | writel(0x0000000e, DSI_CLK_CTRL); |
| 389 | writel(0x0000001e, DSI_CLK_CTRL); |
| 390 | writel(0x0000003e, DSI_CLK_CTRL); |
| 391 | |
| 392 | writel(0, DSI_CTRL); |
| 393 | |
| 394 | writel(0, DSI_ERR_INT_MASK0); |
| 395 | |
| 396 | DST_FORMAT = 0; // RGB565 |
| 397 | printf("\nDSI_Video_Mode - Dst Format: RGB565"); |
| 398 | |
| 399 | DLNx_EN = 1; // 1 lane with clk programming |
| 400 | printf("\nData Lane: 1 lane\n"); |
| 401 | |
| 402 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 403 | printf("\nTraffic mode: non burst mode with sync pulses\n"); |
| 404 | |
| 405 | writel(0x02020202, DSI_INT_CTRL); |
| 406 | |
| 407 | writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 408 | DSI_VIDEO_MODE_ACTIVE_H); |
| 409 | |
| 410 | writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 411 | DSI_VIDEO_MODE_ACTIVE_V); |
| 412 | |
| 413 | writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16) |
| 414 | | img_width + hsync_porch0_fp + hsync_porch0_bp, |
| 415 | DSI_VIDEO_MODE_TOTAL); |
| 416 | |
| 417 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 418 | |
| 419 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 420 | |
| 421 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 422 | |
| 423 | writel(1, DSI_EOT_PACKET_CTRL); |
| 424 | |
| 425 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 426 | |
| 427 | writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8 |
| 428 | | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 429 | |
| 430 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 431 | |
| 432 | writel(0x80006711, DSI_CAL_CTRL); |
| 433 | |
| 434 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 435 | |
| 436 | writel(0x00010100, DSI_INT_CTRL); |
| 437 | writel(0x02010202, DSI_INT_CTRL); |
| 438 | |
| 439 | writel(0x02030303, DSI_INT_CTRL); |
| 440 | |
| 441 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 |
| 442 | | 0x103, DSI_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 443 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 444 | |
| 445 | return status; |
| 446 | } |
| 447 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 448 | int config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height, |
| 449 | unsigned short img_width, unsigned short img_height, |
| 450 | unsigned short dst_format, |
| 451 | unsigned short traffic_mode, |
| 452 | unsigned short datalane_num) |
| 453 | { |
| 454 | unsigned char DST_FORMAT; |
| 455 | unsigned char TRAFIC_MODE; |
| 456 | unsigned char DLNx_EN; |
| 457 | // video mode data ctrl |
| 458 | int status = 0; |
| 459 | unsigned long low_pwr_stop_mode = 0; |
| 460 | unsigned char eof_bllp_pwr = 0x9; |
| 461 | unsigned char interleav = 0; |
| 462 | unsigned char ystride = 0x03; |
| 463 | // disable mdp first |
| 464 | |
| 465 | writel(0x00000000, DSI_CLK_CTRL); |
| 466 | writel(0x00000000, DSI_CLK_CTRL); |
| 467 | writel(0x00000000, DSI_CLK_CTRL); |
| 468 | writel(0x00000000, DSI_CLK_CTRL); |
| 469 | writel(0x00000002, DSI_CLK_CTRL); |
| 470 | writel(0x00000006, DSI_CLK_CTRL); |
| 471 | writel(0x0000000e, DSI_CLK_CTRL); |
| 472 | writel(0x0000001e, DSI_CLK_CTRL); |
| 473 | writel(0x0000003e, DSI_CLK_CTRL); |
| 474 | |
| 475 | writel(0x10000000, DSI_ERR_INT_MASK0); |
| 476 | |
| 477 | // writel(0, DSI_CTRL); |
| 478 | |
| 479 | // writel(0, DSI_ERR_INT_MASK0); |
| 480 | |
| 481 | DST_FORMAT = 8; // RGB888 |
| 482 | printf("\nDSI_Cmd_Mode - Dst Format: RGB888"); |
| 483 | |
| 484 | DLNx_EN = 3; // 2 lane with clk programming |
| 485 | printf("\nData Lane: 2 lane\n"); |
| 486 | |
| 487 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 488 | printf("\nTraffic mode: non burst mode with sync pulses\n"); |
| 489 | |
| 490 | writel(0x02020202, DSI_INT_CTRL); |
| 491 | |
| 492 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 493 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 494 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 495 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 496 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 497 | writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 498 | writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 499 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 500 | writel(0x80000000, DSI_CAL_CTRL); |
| 501 | writel(0x40, DSI_TRIG_CTRL); |
| 502 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 503 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 504 | DSI_CTRL); |
| 505 | mdelay(10); |
| 506 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 507 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 508 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 509 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 510 | // writel(0x0, MDP_OVERLAYPROC0_START); |
| 511 | writel(0x00000001, MDP_DMA_P_START); |
| 512 | mdelay(10); |
| 513 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 514 | |
| 515 | status = 1; |
| 516 | return status; |
| 517 | } |
| 518 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 519 | int mdp_setup_dma_p_video_mode(unsigned short disp_width, |
| 520 | unsigned short disp_height, |
| 521 | unsigned short img_width, |
| 522 | unsigned short img_height, |
| 523 | unsigned short hsync_porch0_fp, |
| 524 | unsigned short hsync_porch0_bp, |
| 525 | unsigned short vsync_porch0_fp, |
| 526 | unsigned short vsync_porch0_bp, |
| 527 | unsigned short hsync_width, |
| 528 | unsigned short vsync_width, |
| 529 | unsigned long input_img_addr, |
| 530 | unsigned short img_width_full_size, |
| 531 | unsigned short pack_pattern, |
| 532 | unsigned char ystride) |
| 533 | { |
| 534 | |
| 535 | // unsigned long mdp_intr_status; |
| 536 | int status = FAIL; |
| 537 | unsigned long hsync_period; |
| 538 | unsigned long vsync_period; |
| 539 | unsigned long vsync_period_intmd; |
| 540 | |
| 541 | printf("\nHi setup MDP4.1 for DSI Video Mode\n"); |
| 542 | |
| 543 | hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1; |
| 544 | vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1; |
| 545 | vsync_period = vsync_period_intmd * hsync_period; |
| 546 | |
| 547 | // ----- programming MDP_AXI_RDMASTER_CONFIG -------- |
| 548 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's |
| 549 | the only port connected */ |
| 550 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 551 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 552 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 553 | writel(0x00000049, MDP_DISP_INTF_SEL); |
| 554 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
| 555 | |
| 556 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 557 | writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
| 558 | |
| 559 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 560 | writel(img_height << 16 | img_width, MDP_DMA_P_SIZE); |
| 561 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
| 562 | writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
| 563 | writel(0x00ff0000, MDP_DMA_P_OP_MODE); |
| 564 | writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL); |
| 565 | writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD); |
| 566 | writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH); |
| 567 | writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp, |
| 568 | MDP_DSI_VIDEO_DISPLAY_HCTL); |
| 569 | writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START); |
| 570 | writel((img_height + vsync_porch0_bp) * hsync_period, |
| 571 | MDP_DSI_VIDEO_DISPLAY_V_END); |
| 572 | writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR); |
| 573 | writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW); |
| 574 | writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY); |
| 575 | // end of cmd mdp |
| 576 | |
| 577 | writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE |
| 578 | |
| 579 | status = PASS; |
| 580 | return status; |
| 581 | } |
| 582 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 583 | int mipi_dsi_video_config(unsigned short num_of_lanes) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 584 | { |
| 585 | |
| 586 | int status = 0; |
| 587 | unsigned long ReadValue; |
| 588 | unsigned long count = 0; |
| 589 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 590 | // bit16, high spd mode 0x0 |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 591 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 592 | // let cmd mode eng send packets in hs |
| 593 | // or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 594 | unsigned short display_wd = mipi_fb_cfg.width; |
| 595 | unsigned short display_ht = mipi_fb_cfg.height; |
| 596 | unsigned short image_wd = mipi_fb_cfg.width; |
| 597 | unsigned short image_ht = mipi_fb_cfg.height; |
| 598 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 599 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 600 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 601 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 602 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 603 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 604 | unsigned short dst_format = 0; |
| 605 | unsigned short traffic_mode = 0; |
| 606 | unsigned short pack_pattern = 0x12; |
| 607 | unsigned char ystride = 3; |
| 608 | |
| 609 | low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 610 | // bit24:HFP, bit28:PULSE MODE, need enough |
| 611 | // time for swithc from LP to HS |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 612 | eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 613 | // packets in hs or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 614 | |
| 615 | status += config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 616 | hsync_porch_fp, hsync_porch_bp, |
| 617 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 618 | vsync_width, dst_format, traffic_mode, |
| 619 | num_of_lanes); |
| 620 | |
| 621 | status += |
| 622 | mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 623 | hsync_porch_fp, hsync_porch_bp, |
| 624 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 625 | vsync_width, MIPI_FB_ADDR, image_wd, |
| 626 | pack_pattern, ystride); |
| 627 | |
| 628 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 629 | while (ReadValue != 0x00010000) { |
| 630 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 631 | count++; |
| 632 | if (count > 0xffff) { |
| 633 | status = FAIL; |
| 634 | printf("\nToshiba Video 565 pulse 1 lane test is failed\n"); |
| 635 | return status; |
| 636 | } |
| 637 | } |
| 638 | |
| 639 | printf("\nToshiba Video 565 pulse 1 lane is tested successfully \n"); |
| 640 | return status; |
| 641 | } |
| 642 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 643 | int mipi_dsi_cmd_config(unsigned short num_of_lanes) |
| 644 | { |
| 645 | |
| 646 | int status = 0; |
| 647 | unsigned long ReadValue; |
| 648 | unsigned long count = 0; |
| 649 | unsigned long input_img_addr = MIPI_FB_ADDR; |
| 650 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
| 651 | // bit16, high spd mode 0x0 |
| 652 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
| 653 | // let cmd mode eng send packets in hs |
| 654 | // or lp mode |
| 655 | unsigned short display_wd = mipi_fb_cfg.width; |
| 656 | unsigned short display_ht = mipi_fb_cfg.height; |
| 657 | unsigned short image_wd = mipi_fb_cfg.width; |
| 658 | unsigned short image_ht = mipi_fb_cfg.height; |
| 659 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 660 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 661 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 662 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 663 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 664 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 665 | unsigned short dst_format = 0; |
| 666 | unsigned short traffic_mode = 0; |
| 667 | unsigned short pack_pattern = 0x12; |
| 668 | unsigned char ystride = 3; |
| 669 | |
| 670 | writel(0x03ffffff, MDP_INTR_ENABLE); |
| 671 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
| 672 | |
| 673 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 674 | writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
| 675 | |
| 676 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 677 | writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE); |
| 678 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
| 679 | |
| 680 | writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
| 681 | |
| 682 | writel(0x00000000, MDP_DMA_P_OP_MODE); |
| 683 | |
| 684 | writel(0x10, MDP_DSI_CMD_MODE_ID_MAP); |
| 685 | writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN); |
| 686 | |
| 687 | writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG); |
| 688 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 689 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 690 | writel(0x8a, MDP_DISP_INTF_SEL); |
| 691 | |
| 692 | return status; |
| 693 | } |
| 694 | |
| 695 | int is_cmd_mode_enabled(void) |
| 696 | { |
| 697 | return cmd_mode_status; |
| 698 | } |
| 699 | |
| 700 | void mipi_dsi_cmd_mode_trigger(void) |
| 701 | { |
| 702 | int status = 0; |
| 703 | unsigned short display_wd = mipi_fb_cfg.width; |
| 704 | unsigned short display_ht = mipi_fb_cfg.height; |
| 705 | unsigned short image_wd = mipi_fb_cfg.width; |
| 706 | unsigned short image_ht = mipi_fb_cfg.height; |
| 707 | unsigned short dst_format = 0; |
| 708 | unsigned short traffic_mode = 0; |
| 709 | struct mipi_dsi_panel_config *panel_info = &novatek_panel_info; |
| 710 | status += mipi_dsi_cmd_config(panel_info->num_of_lanes); |
| 711 | mdelay(50); |
| 712 | config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht, |
| 713 | dst_format, traffic_mode, |
| 714 | panel_info->num_of_lanes /* num_of_lanes */ ); |
| 715 | } |
| 716 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 717 | void mipi_dsi_shutdown(void) |
| 718 | { |
Ajay Dudani | 8fb3609 | 2011-01-27 18:09:50 -0800 | [diff] [blame^] | 719 | writel(0x01010101, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 720 | writel(0x00000001, DSI_PHY_SW_RESET); |
Ajay Dudani | 8fb3609 | 2011-01-27 18:09:50 -0800 | [diff] [blame^] | 721 | writel(0, DSIPHY_PLL_CTRL_0); |
| 722 | writel(0, DSI_CLK_CTRL); |
| 723 | writel(0, DSI_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 724 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
| 725 | } |
| 726 | |
| 727 | struct fbcon_config *mipi_init(void) |
| 728 | { |
| 729 | int status = 0; |
| 730 | unsigned char num_of_lanes = 1; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 731 | struct mipi_dsi_panel_config *panel_info = get_panel_info(); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 732 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 733 | configure_dsicore_dsiclk(); |
| 734 | configure_dsicore_byteclk(); |
| 735 | configure_dsicore_pclk(); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 736 | mipi_dsi_phy_ctrl_config(panel_info); |
| 737 | status += mipi_dsi_panel_initialize(panel_info); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 738 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 739 | mipi_dsi_cmd_bta_sw_trigger(); |
| 740 | mipi_novatek_manufacture_id(); |
| 741 | #endif |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 742 | mipi_fb_cfg.base = MIPI_FB_ADDR; |
| 743 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 744 | if (panel_info->mode == MIPI_VIDEO_MODE) |
| 745 | status += mipi_dsi_video_config(panel_info->num_of_lanes); |
| 746 | |
| 747 | if (panel_info->mode == MIPI_CMD_MODE) |
| 748 | cmd_mode_status = 1; |
| 749 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 750 | return &mipi_fb_cfg; |
| 751 | } |