Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
| 2 |
|
| 3 | * Redistribution and use in source and binary forms, with or without
|
| 4 | * modification, are permitted provided that the following conditions are
|
| 5 | * met:
|
| 6 | * * Redistributions of source code must retain the above copyright
|
| 7 | * notice, this list of conditions and the following disclaimer.
|
| 8 | * * Redistributions in binary form must reproduce the above
|
| 9 | * copyright notice, this list of conditions and the following
|
| 10 | * disclaimer in the documentation and/or other materials provided
|
| 11 | * with the distribution.
|
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its
|
| 13 | * contributors may be used to endorse or promote products derived
|
| 14 | * from this software without specific prior written permission.
|
| 15 | *
|
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
|
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
|
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 | */
|
| 28 |
|
| 29 | #include <string.h>
|
| 30 | #include <stdlib.h>
|
| 31 | #include <debug.h>
|
| 32 | #include <reg.h>
|
| 33 | #include "mmc.h"
|
| 34 | #include <platform/iomap.h>
|
| 35 |
|
| 36 | #ifndef NULL
|
| 37 | #define NULL 0
|
| 38 | #endif
|
| 39 |
|
Subbaraman Narayanamurthy | c95b5b1 | 2010-08-31 13:19:48 -0700 | [diff] [blame] | 40 | #define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
|
| 41 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 42 | /* data access time unit in ns */
|
| 43 | static const unsigned int taac_unit[] =
|
| 44 | { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 };
|
| 45 | /* data access time value x 10 */
|
| 46 | static const unsigned int taac_value[] =
|
| 47 | { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
|
| 48 |
|
| 49 | /* data transfer rate in kbit/s */
|
| 50 | static const unsigned int xfer_rate_unit[] =
|
| 51 | { 100, 1000, 10000, 100000, 0, 0, 0, 0 };
|
| 52 | /* data transfer rate value x 10*/
|
| 53 | static const unsigned int xfer_rate_value[] =
|
| 54 | { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 };
|
| 55 |
|
Shashank Mittal | 920798e | 2010-10-04 17:17:37 -0700 | [diff] [blame^] | 56 | char *ext3_partitions[] = {"system", "userdata", "persist"};
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 57 | unsigned int ext3_count = 0;
|
| 58 |
|
| 59 | static unsigned mmc_sdc_clk[] = { SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
|
| 60 | static unsigned mmc_sdc_pclk[] = { SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
|
| 61 |
|
Subbaraman Narayanamurthy | 4b43c35 | 2010-09-24 13:20:52 -0700 | [diff] [blame] | 62 | unsigned char mmc_slot = 0;
|
| 63 | unsigned int mmc_boot_mci_base = 0;
|
| 64 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 65 | int mmc_clock_enable_disable(unsigned id, unsigned enable);
|
| 66 | int mmc_clock_get_rate(unsigned id);
|
| 67 | int mmc_clock_set_rate(unsigned id, unsigned rate);
|
| 68 | void mdelay(unsigned msecs);
|
| 69 |
|
| 70 | struct mmc_boot_host mmc_host;
|
| 71 | struct mmc_boot_card mmc_card;
|
| 72 | struct mbr_entry mbr[MAX_PARTITIONS];
|
| 73 | unsigned mmc_partition_count = 0;
|
| 74 | static void mbr_fill_name (struct mbr_entry *mbr_ent, unsigned int type);
|
| 75 | unsigned int mmc_read (unsigned long long data_addr, unsigned int* out, unsigned int data_len);
|
| 76 |
|
| 77 |
|
| 78 | unsigned int SWAP_ENDIAN(unsigned int val)
|
| 79 | {
|
| 80 | return ((val & 0xFF) << 24) |
|
| 81 | (((val >> 8) & 0xFF) << 16) |
|
| 82 | (((val >> 16) & 0xFF) << 8) |
|
| 83 | (val >> 24);
|
| 84 | }
|
| 85 |
|
| 86 | /*
|
| 87 | * Function to enable and set master and peripheral clock for
|
| 88 | * MMC card.
|
| 89 | */
|
| 90 | static unsigned int mmc_boot_enable_clock( struct mmc_boot_host* host,
|
| 91 | unsigned int mclk)
|
| 92 | {
|
| 93 | unsigned int mmc_clk = 0;
|
| 94 |
|
| 95 | #ifndef PLATFORM_MSM8X60
|
| 96 | int mmc_signed_ret = 0;
|
Subbaraman Narayanamurthy | 4b43c35 | 2010-09-24 13:20:52 -0700 | [diff] [blame] | 97 | unsigned SDC_CLK = mmc_sdc_clk[mmc_slot - 1];
|
| 98 | unsigned SDC_PCLK = mmc_sdc_pclk[mmc_slot - 1];
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 99 |
|
| 100 | if( host == NULL )
|
| 101 | {
|
| 102 | return MMC_BOOT_E_INVAL;
|
| 103 | }
|
| 104 |
|
| 105 | if( !host->clk_enabled )
|
| 106 | {
|
| 107 | /* set clock */
|
| 108 | if( mmc_clock_enable_disable(SDC_PCLK, MMC_CLK_ENABLE) < 0 )
|
| 109 | {
|
| 110 | dprintf(CRITICAL, "Failure enabling PCLK!\n");
|
| 111 | goto error_pclk;
|
| 112 | }
|
| 113 |
|
| 114 | if( mmc_clock_enable_disable(SDC_CLK, MMC_CLK_ENABLE) < 0 )
|
| 115 | {
|
| 116 | dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
|
| 117 | goto error;
|
| 118 | }
|
| 119 | host->clk_enabled = 1;
|
| 120 | }
|
| 121 | if( host->mclk_rate != mclk )
|
| 122 | {
|
| 123 | if( mmc_clock_set_rate(SDC_CLK, mclk) < 0 )
|
| 124 | {
|
| 125 | dprintf(CRITICAL, "Failure setting clock rate for MCLK - clk_rate: %d\n!", mclk );
|
| 126 | goto error_mclk;
|
| 127 | }
|
| 128 |
|
| 129 | if( ( mmc_signed_ret = mmc_clock_get_rate(SDC_CLK) ) < 0 )
|
| 130 | {
|
| 131 | dprintf(CRITICAL, "Failure getting clock rate for MCLK - clk_rate: %d\n!", host->mclk_rate );
|
| 132 | goto error_mclk;
|
| 133 | }
|
| 134 |
|
| 135 | host->mclk_rate = (unsigned int)mmc_signed_ret;
|
| 136 | }
|
| 137 |
|
| 138 | if( ( mmc_signed_ret = mmc_clock_get_rate(SDC_PCLK) ) < 0 )
|
| 139 | {
|
| 140 | dprintf(CRITICAL, "Failure getting clock rate for PCLK - clk_rate: %d\n!", host->pclk_rate );
|
| 141 | goto error_pclk;
|
| 142 | }
|
| 143 |
|
| 144 | host->pclk_rate = ( unsigned int )mmc_signed_ret;
|
| 145 | dprintf(INFO, "Clock rate - mclk: %dHz pclk: %dHz\n", host->mclk_rate, host->pclk_rate );
|
| 146 | #else
|
| 147 | clock_set_enable(mclk);
|
| 148 | host->mclk_rate = mclk;
|
| 149 | host->pclk_rate = mclk;
|
| 150 | host->clk_enabled = 1;
|
| 151 | #endif
|
| 152 | //enable mci clock
|
| 153 | mmc_clk |= MMC_BOOT_MCI_CLK_ENABLE;
|
| 154 | //enable flow control
|
| 155 | mmc_clk |= MMC_BOOT_MCI_CLK_ENA_FLOW;
|
| 156 | //latch data and command using feedback clock
|
| 157 | mmc_clk |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
|
| 158 | writel( mmc_clk, MMC_BOOT_MCI_CLK );
|
| 159 | return MMC_BOOT_E_SUCCESS;
|
| 160 |
|
| 161 | #ifndef PLATFORM_MSM8X60
|
| 162 | error_pclk:
|
| 163 | mmc_clock_enable_disable(SDC_PCLK, MMC_CLK_DISABLE);
|
| 164 | error_mclk:
|
| 165 | mmc_clock_enable_disable(SDC_CLK, MMC_CLK_DISABLE);
|
| 166 | error:
|
| 167 | return MMC_BOOT_E_CLK_ENABLE_FAIL;
|
| 168 | #endif
|
| 169 | }
|
| 170 |
|
| 171 |
|
| 172 | /* Sets a timeout for read operation.
|
| 173 | */
|
| 174 | static unsigned int mmc_boot_set_read_timeout( struct mmc_boot_host* host,
|
| 175 | struct mmc_boot_card* card )
|
| 176 | {
|
| 177 | unsigned int timeout_ns = 0;
|
| 178 |
|
| 179 | if( ( host == NULL ) || ( card == NULL ) )
|
| 180 | {
|
| 181 | return MMC_BOOT_E_INVAL;
|
| 182 | }
|
| 183 |
|
| 184 | if( card->type == MMC_BOOT_TYPE_SDHC )
|
| 185 | {
|
| 186 | card->rd_timeout_ns = 100000000;
|
| 187 | }
|
| 188 | else if( card->type == MMC_BOOT_TYPE_STD_SD )
|
| 189 | {
|
| 190 | timeout_ns = 10 * ( (card->csd.taac_ns ) +
|
| 191 | ( card->csd.nsac_clk_cycle / (host->mclk_rate/1000000000)));
|
| 192 | }
|
| 193 | else
|
| 194 | {
|
| 195 | return MMC_BOOT_E_NOT_SUPPORTED;
|
| 196 | }
|
| 197 |
|
| 198 | dprintf(INFO, " Read timeout set: %d ns\n", card->rd_timeout_ns );
|
| 199 |
|
| 200 | return MMC_BOOT_E_SUCCESS;
|
| 201 | }
|
| 202 |
|
| 203 | /* Sets a timeout for write operation.
|
| 204 | */
|
| 205 | static unsigned int mmc_boot_set_write_timeout( struct mmc_boot_host* host,
|
| 206 | struct mmc_boot_card* card )
|
| 207 | {
|
| 208 | unsigned int timeout_ns = 0;
|
| 209 |
|
| 210 | if( ( host == NULL ) || ( card == NULL ) )
|
| 211 | {
|
| 212 | return MMC_BOOT_E_INVAL;
|
| 213 | }
|
| 214 |
|
| 215 | if( card->type == MMC_BOOT_TYPE_SDHC )
|
| 216 | {
|
| 217 | card->wr_timeout_ns = 100000000;
|
| 218 | }
|
| 219 | else if( card->type == MMC_BOOT_TYPE_STD_SD )
|
| 220 | {
|
| 221 | timeout_ns = 10 * ( ( card->csd.taac_ns ) +
|
| 222 | ( card->csd.nsac_clk_cycle / ( host->mclk_rate/1000000000 ) ) );
|
| 223 | timeout_ns = timeout_ns << card->csd.r2w_factor;
|
| 224 | }
|
| 225 | else
|
| 226 | {
|
| 227 | return MMC_BOOT_E_NOT_SUPPORTED;
|
| 228 | }
|
| 229 |
|
| 230 | dprintf(INFO, " Write timeout set: %d ns\n", card->wr_timeout_ns );
|
| 231 |
|
| 232 | return MMC_BOOT_E_SUCCESS;
|
| 233 | }
|
| 234 |
|
| 235 |
|
| 236 | /*
|
| 237 | * Decodes CSD response received from the card. Note that we have defined only
|
| 238 | * few of the CSD elements in csd structure. We'll only decode those values.
|
| 239 | */
|
| 240 | static unsigned int mmc_boot_decode_and_save_csd( struct mmc_boot_card* card,
|
| 241 | unsigned int* raw_csd )
|
| 242 | {
|
| 243 | unsigned int mmc_sizeof = 0;
|
| 244 | unsigned int mmc_unit = 0;
|
| 245 | unsigned int mmc_value = 0;
|
| 246 | unsigned int mmc_temp = 0;
|
| 247 |
|
| 248 | struct mmc_boot_csd mmc_csd;
|
| 249 |
|
| 250 | if( ( card == NULL ) || ( raw_csd == NULL ) )
|
| 251 | {
|
| 252 | return MMC_BOOT_E_INVAL;
|
| 253 | }
|
| 254 |
|
| 255 | /* CSD register is little bit differnet for CSD version 2.0 High Capacity
|
| 256 | * and CSD version 1.0/2.0 Standard memory cards. In Version 2.0 some of
|
| 257 | * the fields have fixed values and it's not necessary for host to refer
|
| 258 | * these fields in CSD sent by card */
|
| 259 |
|
| 260 | mmc_sizeof = sizeof(unsigned int) * 8;
|
| 261 |
|
| 262 | mmc_csd.cmmc_structure = UNPACK_BITS( raw_csd, 126, 2, mmc_sizeof );
|
| 263 |
|
| 264 | /* cmmc_structure- 0: Version 1.0 1: Version 2.0 */
|
| 265 | if( mmc_csd.cmmc_structure )
|
| 266 | {
|
| 267 | mmc_csd.card_cmd_class = UNPACK_BITS( raw_csd, 84, 12, mmc_sizeof );
|
| 268 | mmc_csd.write_blk_len = 512; /* Fixed value is 9 = 2^9 = 512 */
|
| 269 | mmc_csd.read_blk_len = 512; /* Fixed value is 9 = 512 */
|
| 270 | mmc_csd.r2w_factor = UNPACK_BITS( raw_csd, 26, 3, mmc_sizeof ); /* Fixed value: 010b */
|
| 271 | mmc_csd.c_size_mult = 0; /* not there in version 2.0 */
|
| 272 | mmc_csd.c_size = UNPACK_BITS( raw_csd, 62, 12, mmc_sizeof );
|
| 273 | mmc_csd.nsac_clk_cycle = UNPACK_BITS( raw_csd, 104, 8, mmc_sizeof) * 100;
|
| 274 |
|
| 275 | mmc_unit = UNPACK_BITS( raw_csd, 112, 3, mmc_sizeof );
|
| 276 | mmc_value = UNPACK_BITS( raw_csd, 115, 4, mmc_sizeof );
|
| 277 | mmc_csd.taac_ns = ( taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
|
| 278 |
|
| 279 | mmc_csd.erase_blk_len = 1;
|
| 280 | mmc_csd.read_blk_misalign = 0;
|
| 281 | mmc_csd.write_blk_misalign = 0;
|
| 282 | mmc_csd.read_blk_partial = 0;
|
| 283 | mmc_csd.write_blk_partial = 0;
|
| 284 |
|
| 285 | mmc_unit = UNPACK_BITS( raw_csd, 96, 3, mmc_sizeof );
|
| 286 | mmc_value = UNPACK_BITS( raw_csd, 99, 4, mmc_sizeof );
|
| 287 | mmc_csd.tran_speed = ( xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10;
|
| 288 |
|
| 289 | /* Calculate card capcity now itself */
|
| 290 | card->capacity = ( 1 + mmc_csd.c_size ) * 512000;
|
| 291 | }
|
| 292 | else
|
| 293 | {
|
| 294 | mmc_csd.card_cmd_class = UNPACK_BITS( raw_csd, 84, 12, mmc_sizeof );
|
| 295 |
|
| 296 | mmc_temp = UNPACK_BITS( raw_csd, 22, 4, mmc_sizeof );
|
| 297 | mmc_csd.write_blk_len = ( mmc_temp > 8 && mmc_temp < 12 )? ( 1 << mmc_temp ) : 512;
|
| 298 |
|
| 299 | mmc_temp = UNPACK_BITS( raw_csd, 80, 4, mmc_sizeof );
|
| 300 | mmc_csd.read_blk_len = ( mmc_temp > 8 && mmc_temp < 12 )? ( 1 << mmc_temp ) : 512;
|
| 301 |
|
| 302 | mmc_unit = UNPACK_BITS( raw_csd, 112, 3, mmc_sizeof );
|
| 303 | mmc_value = UNPACK_BITS( raw_csd, 115, 4, mmc_sizeof );
|
| 304 | mmc_csd.taac_ns = ( taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
|
| 305 |
|
| 306 | mmc_unit = UNPACK_BITS( raw_csd, 96, 3, mmc_sizeof );
|
| 307 | mmc_value = UNPACK_BITS( raw_csd, 99, 4, mmc_sizeof );
|
| 308 | mmc_csd.tran_speed = ( xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10;
|
| 309 |
|
| 310 | mmc_csd.nsac_clk_cycle = UNPACK_BITS( raw_csd, 104, 8, mmc_sizeof ) * 100;
|
| 311 |
|
| 312 | mmc_csd.r2w_factor = UNPACK_BITS( raw_csd, 26, 3, mmc_sizeof );
|
| 313 | mmc_csd.sector_size = UNPACK_BITS( raw_csd, 39, 7, mmc_sizeof ) + 1;
|
| 314 |
|
| 315 | mmc_csd.erase_blk_len = UNPACK_BITS( raw_csd, 46, 1, mmc_sizeof );
|
| 316 | mmc_csd.read_blk_misalign = UNPACK_BITS( raw_csd, 77, 1, mmc_sizeof );
|
| 317 | mmc_csd.write_blk_misalign = UNPACK_BITS( raw_csd, 78, 1, mmc_sizeof );
|
| 318 | mmc_csd.read_blk_partial = UNPACK_BITS( raw_csd, 79, 1, mmc_sizeof );
|
| 319 | mmc_csd.write_blk_partial = UNPACK_BITS( raw_csd, 21, 1, mmc_sizeof );
|
| 320 |
|
| 321 | mmc_csd.c_size_mult = UNPACK_BITS( raw_csd, 47, 3, mmc_sizeof );
|
| 322 | mmc_csd.c_size = UNPACK_BITS( raw_csd, 62, 12, mmc_sizeof );
|
| 323 | mmc_temp = ( 1 << ( mmc_csd.c_size_mult + 2 ) ) * ( mmc_csd.c_size + 1 );
|
| 324 | card->capacity = mmc_temp * mmc_csd.read_blk_len;
|
| 325 | }
|
| 326 |
|
| 327 | /* save the information in card structure */
|
| 328 | memcpy( (struct mmc_boot_csd *)&card->csd, (struct mmc_boot_csd *)&mmc_csd,
|
| 329 | sizeof(struct mmc_boot_csd) );
|
| 330 |
|
| 331 | dprintf(INFO, "Decoded CSD fields:\n" );
|
| 332 | dprintf(INFO, "cmmc_structure: %d\n", mmc_csd.cmmc_structure );
|
| 333 | dprintf(INFO, "card_cmd_class: %x\n", mmc_csd.card_cmd_class );
|
| 334 | dprintf(INFO, "write_blk_len: %d\n", mmc_csd.write_blk_len );
|
| 335 | dprintf(INFO, "read_blk_len: %d\n", mmc_csd.read_blk_len );
|
| 336 | dprintf(INFO, "r2w_factor: %d\n", mmc_csd.r2w_factor );
|
| 337 | dprintf(INFO, "sector_size: %d\n", mmc_csd.sector_size );
|
| 338 | dprintf(INFO, "c_size_mult:%d\n", mmc_csd.c_size_mult );
|
| 339 | dprintf(INFO, "c_size: %d\n", mmc_csd.c_size );
|
| 340 | dprintf(INFO, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle );
|
| 341 | dprintf(INFO, "taac_ns: %d\n", mmc_csd.taac_ns );
|
| 342 | dprintf(INFO, "tran_speed: %d kbps\n", mmc_csd.tran_speed );
|
| 343 | dprintf(INFO, "erase_blk_len: %d\n", mmc_csd.erase_blk_len );
|
| 344 | dprintf(INFO, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign );
|
| 345 | dprintf(INFO, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign );
|
| 346 | dprintf(INFO, "read_blk_partial: %d\n", mmc_csd.read_blk_partial );
|
| 347 | dprintf(INFO, "write_blk_partial: %d\n", mmc_csd.write_blk_partial );
|
| 348 | dprintf(INFO, "Card Capacity: %d Bytes\n", card->capacity );
|
| 349 |
|
| 350 | return MMC_BOOT_E_SUCCESS;
|
| 351 |
|
| 352 | }
|
| 353 |
|
| 354 | /*
|
| 355 | * Decode CID sent by the card.
|
| 356 | */
|
| 357 | static unsigned int mmc_boot_decode_and_save_cid( struct mmc_boot_card* card,
|
| 358 | unsigned int* raw_cid )
|
| 359 | {
|
| 360 | struct mmc_boot_cid mmc_cid;
|
| 361 | unsigned int mmc_sizeof = 0;
|
| 362 | int i = 0;
|
| 363 |
|
| 364 | if( ( card == NULL ) || ( raw_cid == NULL ) )
|
| 365 | {
|
| 366 | return MMC_BOOT_E_INVAL;
|
| 367 | }
|
| 368 |
|
| 369 | mmc_sizeof = sizeof( unsigned int ) * 8;
|
| 370 | mmc_cid.mid = UNPACK_BITS( raw_cid, 120, 8, mmc_sizeof );
|
| 371 | mmc_cid.oid = UNPACK_BITS( raw_cid, 104, 16, mmc_sizeof );
|
| 372 |
|
| 373 | for( i = 0; i < 6; i++ )
|
| 374 | {
|
| 375 | mmc_cid.pnm[i] = (unsigned char) UNPACK_BITS(raw_cid, \
|
| 376 | (104 - 8 * (i+1)), 8, mmc_sizeof );
|
| 377 | }
|
| 378 | mmc_cid.pnm[6] = 0;
|
| 379 |
|
| 380 | mmc_cid.prv = UNPACK_BITS( raw_cid, 48, 8, mmc_sizeof );
|
| 381 | mmc_cid.psn = UNPACK_BITS( raw_cid, 16, 32, mmc_sizeof );
|
| 382 | mmc_cid.month = UNPACK_BITS( raw_cid, 12, 4, mmc_sizeof );
|
| 383 | mmc_cid.year = UNPACK_BITS( raw_cid, 8, 4, mmc_sizeof );
|
| 384 |
|
| 385 | /* save it in card database */
|
| 386 | memcpy( ( struct mmc_boot_cid * )&card->cid, \
|
| 387 | ( struct mmc_boot_cid * )&mmc_cid, \
|
| 388 | sizeof( struct mmc_boot_cid ) );
|
| 389 |
|
| 390 | dprintf(INFO, "Decoded CID fields:\n" );
|
| 391 | dprintf(INFO, "Manufacturer ID: %x\n", mmc_cid.mid );
|
| 392 | dprintf(INFO, "OEM ID: 0x%x\n", mmc_cid.oid );
|
| 393 | dprintf(INFO, "Product Name: %s\n", mmc_cid.pnm );
|
| 394 | dprintf(INFO, "Product revision: %d.%d\n", (mmc_cid.prv >> 4), (mmc_cid.prv & 0xF) );
|
| 395 | dprintf(INFO, "Product serial number: %X\n", mmc_cid.psn );
|
| 396 | dprintf(INFO, "Manufacturing date: %d %d\n", mmc_cid.month, mmc_cid.year + 1997 );
|
| 397 |
|
| 398 | return MMC_BOOT_E_SUCCESS;
|
| 399 | }
|
| 400 |
|
| 401 | /*
|
| 402 | * Sends specified command to a card and waits for a response.
|
| 403 | */
|
| 404 | static unsigned int mmc_boot_send_command( struct mmc_boot_command* cmd )
|
| 405 | {
|
| 406 | unsigned int mmc_cmd = 0;
|
| 407 | unsigned int mmc_status = 0;
|
| 408 | unsigned int mmc_resp = 0;
|
| 409 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
|
| 410 | unsigned int cmd_index = 0;
|
| 411 | int i = 0;
|
| 412 |
|
| 413 | /* basic check */
|
| 414 | if( cmd == NULL )
|
| 415 | {
|
| 416 | return MMC_BOOT_E_INVAL;
|
| 417 | }
|
| 418 |
|
| 419 | /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */
|
| 420 | writel( cmd->argument, MMC_BOOT_MCI_ARGUMENT );
|
| 421 |
|
| 422 | /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */
|
| 423 | /* 2a. Write command index in CMD_INDEX field */
|
| 424 | cmd_index = cmd->cmd_index;
|
| 425 | mmc_cmd |= cmd->cmd_index;
|
| 426 | /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 */
|
| 427 | if( cmd_index != CMD0_GO_IDLE_STATE )
|
| 428 | {
|
| 429 | mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE;
|
| 430 | }
|
| 431 |
|
| 432 | /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */
|
| 433 | if( IS_RESP_136_BITS(cmd->resp_type) )
|
| 434 | {
|
| 435 | mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP;
|
| 436 | }
|
| 437 |
|
| 438 | /* 2d. Set INTERRUPT bit to 1 to disable command timeout */
|
| 439 |
|
| 440 | /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream
|
| 441 | mode data transfer*/
|
| 442 | if( cmd->xfer_mode == MMC_BOOT_XFER_MODE_STREAM )
|
| 443 | {
|
| 444 | mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING;
|
| 445 | }
|
| 446 |
|
| 447 | /* 2f. Set ENABLE bit to 1 */
|
| 448 | mmc_cmd |= MMC_BOT_MCI_CMD_ENABLE;
|
| 449 |
|
| 450 | /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of
|
| 451 | write data transfer */
|
| 452 | if( ( cmd_index == CMD12_STOP_TRANSMISSION ||
|
| 453 | cmd_index == CMD13_SEND_STATUS ) && cmd->prg_enabled )
|
| 454 | {
|
| 455 | mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA;
|
| 456 | }
|
| 457 |
|
| 458 | /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */
|
| 459 | /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal
|
| 460 | of CE-ATA device is enabled */
|
| 461 |
|
| 462 | /* 2j. clear all static status bits */
|
| 463 | writel( MMC_BOOT_MCI_STATIC_STATUS, MMC_BOOT_MCI_CLEAR );
|
| 464 |
|
| 465 | /* 2k. Write to MMC_BOOT_MCI_CMD register */
|
| 466 | writel( mmc_cmd, MMC_BOOT_MCI_CMD );
|
| 467 |
|
| 468 | dprintf(INFO, "Command sent: CMD%d MCI_CMD_REG:%x MCI_ARG:%x\n",
|
| 469 | cmd_index, mmc_cmd, cmd->argument );
|
| 470 |
|
| 471 | /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS
|
| 472 | register */
|
| 473 | do{
|
| 474 | /* 3a. Read MCI_STATUS register */
|
| 475 | while(readl( MMC_BOOT_MCI_STATUS ) \
|
| 476 | & MMC_BOOT_MCI_STAT_CMD_ACTIVE);
|
| 477 |
|
| 478 | mmc_status = readl( MMC_BOOT_MCI_STATUS );
|
| 479 |
|
| 480 | /* 3b. CMD_SENT bit supposed to be set to 1 only after CMD0 is sent -
|
| 481 | no response required. */
|
| 482 | if( ( cmd->resp_type == MMC_BOOT_RESP_NONE ) &&
|
| 483 | (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT ) )
|
| 484 | {
|
| 485 | break;
|
| 486 | }
|
| 487 |
|
| 488 | /* 3c. If CMD_TIMEOUT bit is set then no response was received */
|
| 489 | else if( mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT )
|
| 490 | {
|
| 491 | mmc_return = MMC_BOOT_E_TIMEOUT;
|
| 492 | break;
|
| 493 | }
|
| 494 |
|
| 495 | /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's response was
|
| 496 | received and CRC check passed
|
| 497 | Spcial case for ACMD41: it seems to always fail CRC even if
|
| 498 | the response is valid
|
| 499 | */
|
| 500 | else if (( mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END ) || (cmd_index == CMD1_SEND_OP_COND))
|
| 501 | {
|
| 502 | /* 3i. Read MCI_RESP_CMD register to verify that response index is
|
| 503 | equal to command index */
|
| 504 | mmc_resp = readl( MMC_BOOT_MCI_RESP_CMD ) & 0x3F;
|
| 505 |
|
| 506 | /* However, long response does not contain the command index field.
|
| 507 | * In that case, response index field must be set to 111111b (0x3F) */
|
| 508 | if( ( mmc_resp == cmd_index ) ||
|
| 509 | ( cmd->resp_type == MMC_BOOT_RESP_R2 ||
|
| 510 | cmd->resp_type == MMC_BOOT_RESP_R3 ||
|
| 511 | cmd->resp_type == MMC_BOOT_RESP_R6 ) )
|
| 512 | {
|
| 513 | /* 3j. If resp index is equal to cmd index, read command resp
|
| 514 | from MCI_RESPn registers
|
| 515 | - MCI_RESP0/1/2/3 for CMD2/9/10
|
| 516 | - MCI_RESP0 for all other registers */
|
| 517 | if( IS_RESP_136_BITS( cmd->resp_type ) )
|
| 518 | {
|
| 519 | for( i = 0; i < 4; i++ )
|
| 520 | {
|
| 521 | cmd->resp[3-i] = readl( MMC_BOOT_MCI_RESP_0 + ( i * 4 ) );
|
| 522 |
|
| 523 | }
|
| 524 | }
|
| 525 | else
|
| 526 | {
|
| 527 | cmd->resp[0] = readl( MMC_BOOT_MCI_RESP_0 );
|
| 528 | }
|
| 529 | }
|
| 530 | else
|
| 531 | {
|
| 532 | /* command index mis-match */
|
| 533 | mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH;
|
| 534 | }
|
| 535 |
|
| 536 | dprintf(INFO, "Command response received: %X\n", cmd->resp[0] );
|
| 537 | break;
|
| 538 | }
|
| 539 |
|
| 540 | /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response was recvd,
|
| 541 | but CRC check failed. */
|
| 542 | else if( ( mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL ) )
|
| 543 | {
|
| 544 | mmc_return = MMC_BOOT_E_CRC_FAIL;
|
| 545 | break;
|
| 546 | }
|
| 547 |
|
| 548 | }while(1);
|
| 549 |
|
| 550 | return mmc_return;
|
| 551 | }
|
| 552 |
|
| 553 | /*
|
| 554 | * Reset all the cards to idle condition (CMD 0)
|
| 555 | */
|
| 556 | static unsigned int mmc_boot_reset_cards( void )
|
| 557 | {
|
| 558 | struct mmc_boot_command cmd;
|
| 559 |
|
| 560 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 561 | sizeof(struct mmc_boot_command) );
|
| 562 |
|
| 563 | cmd.cmd_index = CMD0_GO_IDLE_STATE;
|
| 564 | cmd.argument = 0; // stuff bits - ignored
|
| 565 | cmd.cmd_type = MMC_BOOT_CMD_BCAST;
|
| 566 | cmd.resp_type = MMC_BOOT_RESP_NONE;
|
| 567 |
|
| 568 | /* send command */
|
| 569 | return mmc_boot_send_command( &cmd );
|
| 570 | }
|
| 571 |
|
| 572 | /*
|
| 573 | * Send CMD1 to know whether the card supports host VDD profile or not.
|
| 574 | */
|
| 575 | static unsigned int mmc_boot_send_op_cond( struct mmc_boot_host* host,
|
| 576 | struct mmc_boot_card* card )
|
| 577 | {
|
| 578 | struct mmc_boot_command cmd;
|
| 579 | unsigned int mmc_resp = 0;
|
| 580 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 581 |
|
| 582 | /* basic check */
|
| 583 | if( ( host == NULL ) || ( card == NULL ) )
|
| 584 | {
|
| 585 | return MMC_BOOT_E_INVAL;
|
| 586 | }
|
| 587 |
|
| 588 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 589 | sizeof(struct mmc_boot_command) );
|
| 590 |
|
| 591 | /* CMD1 format:
|
| 592 | * [31] Busy bit
|
| 593 | * [30:29] Access mode
|
| 594 | * [28:24] reserved
|
| 595 | * [23:15] 2.7-3.6
|
| 596 | * [14:8] 2.0-2.6
|
| 597 | * [7] 1.7-1.95
|
| 598 | * [6:0] reserved
|
| 599 | */
|
| 600 |
|
| 601 | cmd.cmd_index = CMD1_SEND_OP_COND;
|
| 602 | cmd.argument = host->ocr;
|
| 603 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
|
| 604 | cmd.resp_type = MMC_BOOT_RESP_R3;
|
| 605 |
|
| 606 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 607 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 608 | {
|
| 609 | return mmc_ret;
|
| 610 | }
|
| 611 |
|
| 612 | /* Now it's time to examine response */
|
| 613 | mmc_resp = cmd.resp[0];
|
| 614 |
|
| 615 | /* Response contains card's ocr. Update card's information */
|
| 616 | card->ocr = mmc_resp;
|
| 617 |
|
| 618 | /* Check the response for busy status */
|
| 619 | if( !( mmc_resp & MMC_BOOT_OCR_BUSY ) )
|
| 620 | {
|
| 621 | return MMC_BOOT_E_CARD_BUSY;
|
| 622 | }
|
| 623 |
|
| 624 | return MMC_BOOT_E_SUCCESS;
|
| 625 | }
|
| 626 |
|
| 627 | /*
|
| 628 | * Request any card to send its uniquie card identification (CID) number (CMD2).
|
| 629 | */
|
| 630 | static unsigned int mmc_boot_all_send_cid( struct mmc_boot_card* card )
|
| 631 | {
|
| 632 | struct mmc_boot_command cmd;
|
| 633 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 634 |
|
| 635 | /* basic check */
|
| 636 | if( card == NULL )
|
| 637 | {
|
| 638 | return MMC_BOOT_E_INVAL;
|
| 639 | }
|
| 640 |
|
| 641 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 642 | sizeof(struct mmc_boot_command) );
|
| 643 |
|
| 644 | /* CMD2 Format:
|
| 645 | * [31:0] stuff bits
|
| 646 | */
|
| 647 | cmd.cmd_index = CMD2_ALL_SEND_CID;
|
| 648 | cmd.argument = 0;
|
| 649 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
|
| 650 | cmd.resp_type = MMC_BOOT_RESP_R2;
|
| 651 |
|
| 652 | /* send command */
|
| 653 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 654 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 655 | {
|
| 656 | return mmc_ret;
|
| 657 | }
|
| 658 |
|
| 659 | /* Response contains card's 128 bits CID register */
|
| 660 | mmc_ret = mmc_boot_decode_and_save_cid( card, cmd.resp );
|
| 661 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 662 | {
|
| 663 | return mmc_ret;
|
| 664 | }
|
| 665 | return MMC_BOOT_E_SUCCESS;
|
| 666 | }
|
| 667 |
|
| 668 | /*
|
| 669 | * Ask any card to send it's relative card address (RCA).This RCA number is
|
| 670 | * shorter than CID and is used by the host to address the card in future (CMD3)
|
| 671 | */
|
| 672 | static unsigned int mmc_boot_send_relative_address( struct mmc_boot_card* card )
|
| 673 | {
|
| 674 | struct mmc_boot_command cmd;
|
| 675 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 676 |
|
| 677 | /* basic check */
|
| 678 | if( card == NULL )
|
| 679 | {
|
| 680 | return MMC_BOOT_E_INVAL;
|
| 681 | }
|
| 682 |
|
| 683 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 684 | sizeof(struct mmc_boot_command) );
|
| 685 |
|
| 686 | /* CMD3 Format:
|
| 687 | * [31:0] stuff bits
|
| 688 | */
|
| 689 | cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
|
| 690 | cmd.argument = (MMC_RCA << 16);
|
| 691 | card->rca = (cmd.argument >> 16);
|
| 692 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 693 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 694 |
|
| 695 | /* send command */
|
| 696 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 697 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 698 | {
|
| 699 | return mmc_ret;
|
| 700 | }
|
| 701 |
|
| 702 | return MMC_BOOT_E_SUCCESS;
|
| 703 | }
|
| 704 |
|
| 705 | /*
|
| 706 | * Requests card to send it's CSD register's contents. (CMD9)
|
| 707 | */
|
| 708 | static unsigned int mmc_boot_send_csd( struct mmc_boot_card* card )
|
| 709 | {
|
| 710 | struct mmc_boot_command cmd;
|
| 711 | unsigned int mmc_arg = 0;
|
| 712 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 713 |
|
| 714 | /* basic check */
|
| 715 | if( card == NULL )
|
| 716 | {
|
| 717 | return MMC_BOOT_E_INVAL;
|
| 718 | }
|
| 719 |
|
| 720 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 721 | sizeof(struct mmc_boot_command) );
|
| 722 |
|
| 723 | /* CMD9 Format:
|
| 724 | * [31:16] RCA
|
| 725 | * [15:0] stuff bits
|
| 726 | */
|
| 727 | mmc_arg |= card->rca << 16;
|
| 728 |
|
| 729 | cmd.cmd_index = CMD9_SEND_CSD;
|
| 730 | cmd.argument = mmc_arg;
|
| 731 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 732 | cmd.resp_type = MMC_BOOT_RESP_R2;
|
| 733 |
|
| 734 | /* send command */
|
| 735 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 736 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 737 | {
|
| 738 | return mmc_ret;
|
| 739 | }
|
| 740 |
|
| 741 | /* Response contains card's 128 bits CSD register */
|
| 742 | /* Decode and save the register */
|
| 743 | mmc_ret = mmc_boot_decode_and_save_csd( card, cmd.resp );
|
| 744 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 745 | {
|
| 746 | return mmc_ret;
|
| 747 | }
|
| 748 |
|
| 749 | return MMC_BOOT_E_SUCCESS;
|
| 750 | }
|
| 751 |
|
| 752 | /*
|
| 753 | * Selects a card by sending CMD7 to the card with its RCA.
|
| 754 | * If RCA field is set as 0 ( or any other address ),
|
| 755 | * the card will be de-selected. (CMD7)
|
| 756 | */
|
| 757 | static unsigned int mmc_boot_select_card( struct mmc_boot_card* card,
|
| 758 | unsigned int rca )
|
| 759 | {
|
| 760 | struct mmc_boot_command cmd;
|
| 761 | unsigned int mmc_arg = 0;
|
| 762 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 763 |
|
| 764 | /* basic check */
|
| 765 | if( card == NULL )
|
| 766 | {
|
| 767 | return MMC_BOOT_E_INVAL;
|
| 768 | }
|
| 769 |
|
| 770 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 771 | sizeof(struct mmc_boot_command) );
|
| 772 |
|
| 773 | /* CMD7 Format:
|
| 774 | * [31:16] RCA
|
| 775 | * [15:0] stuff bits
|
| 776 | */
|
| 777 | mmc_arg |= rca << 16;
|
| 778 |
|
| 779 | cmd.cmd_index = CMD7_SELECT_DESELECT_CARD;
|
| 780 | cmd.argument = mmc_arg;
|
| 781 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 782 | /* If we are deselecting card, we do not get response */
|
| 783 | if( rca == card->rca && rca)
|
| 784 | {
|
| 785 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 786 | }
|
| 787 | else
|
| 788 | {
|
| 789 | cmd.resp_type = MMC_BOOT_RESP_NONE;
|
| 790 | }
|
| 791 |
|
| 792 | /* send command */
|
| 793 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 794 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 795 | {
|
| 796 | return mmc_ret;
|
| 797 | }
|
| 798 |
|
| 799 | /* As of now no need to look into a response. If it's required
|
| 800 | * we'll explore later on */
|
| 801 |
|
| 802 | return MMC_BOOT_E_SUCCESS;
|
| 803 | }
|
| 804 |
|
| 805 | /*
|
| 806 | * Send command to set block length.
|
| 807 | */
|
| 808 | static unsigned int mmc_boot_set_block_len( struct mmc_boot_card* card,
|
| 809 | unsigned int block_len )
|
| 810 | {
|
| 811 | struct mmc_boot_command cmd;
|
| 812 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 813 |
|
| 814 | /* basic check */
|
| 815 | if( card == NULL )
|
| 816 | {
|
| 817 | return MMC_BOOT_E_INVAL;
|
| 818 | }
|
| 819 |
|
| 820 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 821 | sizeof(struct mmc_boot_command) );
|
| 822 |
|
| 823 | /* CMD16 Format:
|
| 824 | * [31:0] block length
|
| 825 | */
|
| 826 |
|
| 827 | cmd.cmd_index = CMD16_SET_BLOCKLEN;
|
| 828 | cmd.argument = block_len;
|
| 829 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 830 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 831 |
|
| 832 | /* send command */
|
| 833 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 834 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 835 | {
|
| 836 | return mmc_ret;
|
| 837 | }
|
| 838 |
|
| 839 | /* If blocklength is larger than 512 bytes,
|
| 840 | * the card sets BLOCK_LEN_ERROR bit. */
|
| 841 | if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
|
| 842 | {
|
| 843 | return MMC_BOOT_E_BLOCKLEN_ERR;
|
| 844 | }
|
| 845 | return MMC_BOOT_E_SUCCESS;
|
| 846 | }
|
| 847 |
|
| 848 | /*
|
| 849 | * Requests the card to stop transmission of data.
|
| 850 | */
|
| 851 | static unsigned int mmc_boot_send_stop_transmission( struct mmc_boot_card* card,
|
| 852 | unsigned int prg_enabled )
|
| 853 | {
|
| 854 | struct mmc_boot_command cmd;
|
| 855 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 856 |
|
| 857 | /* basic check */
|
| 858 | if( card == NULL )
|
| 859 | {
|
| 860 | return MMC_BOOT_E_INVAL;
|
| 861 | }
|
| 862 |
|
| 863 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 864 | sizeof(struct mmc_boot_command) );
|
| 865 |
|
| 866 | /* CMD12 Format:
|
| 867 | * [31:0] stuff bits
|
| 868 | */
|
| 869 |
|
| 870 | cmd.cmd_index = CMD12_STOP_TRANSMISSION;
|
| 871 | cmd.argument = 0;
|
| 872 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 873 | cmd.resp_type = MMC_BOOT_RESP_R1B;
|
| 874 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
|
| 875 | cmd.prg_enabled = prg_enabled;
|
| 876 |
|
| 877 | /* send command */
|
| 878 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 879 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 880 | {
|
| 881 | return mmc_ret;
|
| 882 | }
|
| 883 | return MMC_BOOT_E_SUCCESS;
|
| 884 | }
|
| 885 |
|
| 886 | /*
|
| 887 | * Get the card's current status
|
| 888 | */
|
| 889 | static unsigned int mmc_boot_get_card_status( struct mmc_boot_card* card,
|
| 890 | unsigned int prg_enabled )
|
| 891 | {
|
| 892 | struct mmc_boot_command cmd;
|
| 893 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 894 |
|
| 895 | /* basic check */
|
| 896 | if( card == NULL )
|
| 897 | {
|
| 898 | return MMC_BOOT_E_INVAL;
|
| 899 | }
|
| 900 |
|
| 901 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 902 | sizeof(struct mmc_boot_command) );
|
| 903 |
|
| 904 | /* CMD13 Format:
|
| 905 | * [31:16] RCA
|
| 906 | * [15:0] stuff bits
|
| 907 | */
|
| 908 | cmd.cmd_index = CMD13_SEND_STATUS;
|
| 909 | cmd.argument = card->rca << 16;
|
| 910 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 911 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 912 | cmd.prg_enabled = prg_enabled;
|
| 913 |
|
| 914 | /* send command */
|
| 915 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 916 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 917 | {
|
| 918 | return mmc_ret;
|
| 919 | }
|
| 920 |
|
| 921 | return MMC_BOOT_E_SUCCESS;
|
| 922 | }
|
| 923 | /*
|
| 924 | * Send ext csd command.
|
| 925 | */
|
| 926 | static unsigned int mmc_boot_send_ext_cmd (struct mmc_boot_card* card)
|
| 927 | {
|
| 928 | struct mmc_boot_command cmd;
|
| 929 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 930 | unsigned int mmc_reg = 0;
|
| 931 | unsigned char buf[512];
|
| 932 | unsigned int mmc_status = 0;
|
| 933 | unsigned int* mmc_ptr = (unsigned int *)buf;
|
| 934 | unsigned int mmc_count = 0;
|
| 935 |
|
| 936 | // start from the back
|
| 937 | mmc_ptr += ( (512/sizeof(int)) - 1 );
|
| 938 |
|
| 939 | /* basic check */
|
| 940 | if( card == NULL )
|
| 941 | {
|
| 942 | return MMC_BOOT_E_INVAL;
|
| 943 | }
|
| 944 |
|
| 945 | /* set block len */
|
| 946 | mmc_ret = mmc_boot_set_block_len( card, 512);
|
| 947 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 948 | {
|
| 949 | dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
|
| 950 | mmc_ret, (char *)(card->rca) );
|
| 951 | return mmc_ret;
|
| 952 | }
|
| 953 |
|
| 954 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
|
| 955 | mmc_reg = readl( MMC_BOOT_MCI_CLK );
|
| 956 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
|
| 957 | writel( mmc_reg, MMC_BOOT_MCI_CLK );
|
| 958 |
|
| 959 | /* Write data timeout period to MCI_DATA_TIMER register. */
|
| 960 | /* Data timeout period should be in card bus clock periods */
|
| 961 | mmc_reg =0xFFFFFFFF;
|
| 962 | writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
|
| 963 | writel( 512, MMC_BOOT_MCI_DATA_LENGTH );
|
| 964 |
|
| 965 | /* Set appropriate fields and write the MCI_DATA_CTL register. */
|
| 966 | /* Set ENABLE bit to 1 to enable the data transfer. */
|
| 967 | mmc_reg = MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (512 << MMC_BOOT_MCI_BLKSIZE_POS);
|
| 968 | writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
|
| 969 |
|
| 970 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 971 | sizeof(struct mmc_boot_command) );
|
| 972 | /* CMD8 */
|
| 973 | cmd.cmd_index = CMD8_SEND_EXT_CSD;
|
| 974 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 975 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 976 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
|
| 977 |
|
| 978 | /* send command */
|
| 979 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 980 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 981 | {
|
| 982 | return mmc_ret;
|
| 983 | }
|
| 984 |
|
| 985 | do
|
| 986 | {
|
| 987 | mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 988 | mmc_status = readl( MMC_BOOT_MCI_STATUS );
|
| 989 |
|
| 990 | /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
|
| 991 | card/device during the data transfer */
|
| 992 | if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
|
| 993 | {
|
| 994 | mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
|
| 995 | break;
|
| 996 | }
|
| 997 | /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
|
| 998 | the data timeout period without completing the transfer */
|
| 999 | else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
|
| 1000 | {
|
| 1001 | mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
|
| 1002 | break;
|
| 1003 | }
|
| 1004 | /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
|
| 1005 | the card before empty storage for new received data was available.
|
| 1006 | Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
|
| 1007 | else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
|
| 1008 | {
|
| 1009 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
|
| 1010 | for now */
|
| 1011 | mmc_ret = MMC_BOOT_E_RX_OVRRUN;
|
| 1012 | break;
|
| 1013 | }
|
| 1014 |
|
| 1015 | if( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL )
|
| 1016 | {
|
| 1017 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
|
| 1018 | *mmc_ptr = SWAP_ENDIAN(readl( MMC_BOOT_MCI_FIFO +
|
| 1019 | ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) ));
|
| 1020 | mmc_ptr--;
|
| 1021 |
|
| 1022 | /* increase mmc_count by word size */
|
| 1023 | mmc_count += sizeof( unsigned int );
|
| 1024 |
|
| 1025 | /* quit if we have read enough of data */
|
| 1026 | if (mmc_count >= 512)
|
| 1027 | break;
|
| 1028 | }
|
| 1029 | else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_END )
|
| 1030 | {
|
| 1031 | break;
|
| 1032 | }
|
| 1033 |
|
| 1034 | }while(1);
|
| 1035 |
|
| 1036 | return MMC_BOOT_E_SUCCESS;
|
| 1037 |
|
| 1038 | }
|
| 1039 |
|
| 1040 |
|
| 1041 |
|
| 1042 | /*
|
| 1043 | * Switch command
|
| 1044 | */
|
| 1045 | static unsigned int mmc_boot_switch_cmd (struct mmc_boot_card* card,
|
| 1046 | unsigned access,
|
| 1047 | unsigned index,
|
| 1048 | unsigned value)
|
| 1049 | {
|
| 1050 |
|
| 1051 | struct mmc_boot_command cmd;
|
| 1052 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1053 |
|
| 1054 | /* basic check */
|
| 1055 | if( card == NULL )
|
| 1056 | {
|
| 1057 | return MMC_BOOT_E_INVAL;
|
| 1058 | }
|
| 1059 |
|
| 1060 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 1061 | sizeof(struct mmc_boot_command) );
|
| 1062 |
|
| 1063 | /* CMD6 Format:
|
| 1064 | * [31:26] set to 0
|
| 1065 | * [25:24] access
|
| 1066 | * [23:16] index
|
| 1067 | * [15:8] value
|
| 1068 | * [7:3] set to 0
|
| 1069 | * [2:0] cmd set
|
| 1070 | */
|
| 1071 | cmd.cmd_index = CMD6_SWITCH_FUNC;
|
| 1072 | cmd.argument |= (access << 24);
|
| 1073 | cmd.argument |= (index << 16);
|
| 1074 | cmd.argument |= (value << 8);
|
| 1075 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 1076 | cmd.resp_type = MMC_BOOT_RESP_R1B;
|
| 1077 |
|
| 1078 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 1079 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1080 | {
|
| 1081 | return mmc_ret;
|
| 1082 | }
|
| 1083 |
|
| 1084 | return MMC_BOOT_E_SUCCESS;
|
| 1085 | }
|
| 1086 |
|
| 1087 | /*
|
| 1088 | * A command to set the data bus width for card. Set width to either
|
| 1089 | */
|
| 1090 | static unsigned int mmc_boot_set_bus_width( struct mmc_boot_card* card,
|
| 1091 | unsigned int width )
|
| 1092 | {
|
| 1093 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1094 | unsigned int mmc_reg = 0;
|
| 1095 | unsigned int mmc_width = 0;
|
| 1096 |
|
| 1097 | if( width != MMC_BOOT_BUS_WIDTH_1_BIT)
|
| 1098 | {
|
| 1099 | mmc_width = width-1;
|
| 1100 | }
|
| 1101 |
|
| 1102 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, MMC_BOOT_EXT_CMMC_BUS_WIDTH, mmc_width);
|
| 1103 |
|
| 1104 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1105 | {
|
| 1106 | return mmc_ret;
|
| 1107 | }
|
| 1108 |
|
| 1109 | /* set MCI_CLK accordingly */
|
| 1110 | mmc_reg = readl( MMC_BOOT_MCI_CLK );
|
| 1111 | mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE;
|
| 1112 | if ( width == MMC_BOOT_BUS_WIDTH_1_BIT )
|
| 1113 | {
|
| 1114 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT;
|
| 1115 | }
|
| 1116 | else if (width == MMC_BOOT_BUS_WIDTH_4_BIT )
|
| 1117 | {
|
| 1118 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT;
|
| 1119 | }
|
| 1120 | else if (width == MMC_BOOT_BUS_WIDTH_8_BIT )
|
| 1121 | {
|
| 1122 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT;
|
| 1123 | }
|
| 1124 | writel( mmc_reg, MMC_BOOT_MCI_CLK );
|
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 1125 |
|
| 1126 | mdelay(10); // Giving some time to card to stabilize.
|
| 1127 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1128 | return MMC_BOOT_E_SUCCESS;
|
| 1129 | }
|
| 1130 |
|
| 1131 |
|
| 1132 | /*
|
| 1133 | * A command to start data read from card. Either a single block or
|
| 1134 | * multiple blocks can be read. Multiple blocks read will continuously
|
| 1135 | * transfer data from card to host unless requested to stop by issuing
|
| 1136 | * CMD12 - STOP_TRANSMISSION.
|
| 1137 | */
|
| 1138 | static unsigned int mmc_boot_send_read_command( struct mmc_boot_card* card,
|
| 1139 | unsigned int xfer_type,
|
| 1140 | unsigned int data_addr )
|
| 1141 | {
|
| 1142 | struct mmc_boot_command cmd;
|
| 1143 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1144 |
|
| 1145 | /* basic check */
|
| 1146 | if( card == NULL )
|
| 1147 | {
|
| 1148 | return MMC_BOOT_E_INVAL;
|
| 1149 | }
|
| 1150 |
|
| 1151 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 1152 | sizeof(struct mmc_boot_command) );
|
| 1153 |
|
| 1154 | /* CMD17/18 Format:
|
| 1155 | * [31:0] Data Address
|
| 1156 | */
|
| 1157 | if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
|
| 1158 | {
|
| 1159 | cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK;
|
| 1160 | }
|
| 1161 | else
|
| 1162 | {
|
| 1163 | cmd.cmd_index = CMD17_READ_SINGLE_BLOCK;
|
| 1164 | }
|
| 1165 |
|
| 1166 | cmd.argument = data_addr;
|
| 1167 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 1168 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 1169 |
|
| 1170 | /* send command */
|
| 1171 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 1172 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1173 | {
|
| 1174 | return mmc_ret;
|
| 1175 | }
|
| 1176 |
|
| 1177 | /* Response contains 32 bit Card status. Here we'll check
|
| 1178 | BLOCK_LEN_ERROR and ADDRESS_ERROR */
|
| 1179 | if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
|
| 1180 | {
|
| 1181 | return MMC_BOOT_E_BLOCKLEN_ERR;
|
| 1182 | }
|
| 1183 | /* Misaligned address not matching block length */
|
| 1184 | if( cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR )
|
| 1185 | {
|
| 1186 | return MMC_BOOT_E_ADDRESS_ERR;
|
| 1187 | }
|
| 1188 |
|
| 1189 | return MMC_BOOT_E_SUCCESS;
|
| 1190 | }
|
| 1191 |
|
| 1192 | /*
|
| 1193 | * A command to start data write to card. Either a single block or
|
| 1194 | * multiple blocks can be written. Multiple block write will continuously
|
| 1195 | * transfer data from host to card unless requested to stop by issuing
|
| 1196 | * CMD12 - STOP_TRANSMISSION.
|
| 1197 | */
|
| 1198 | static unsigned int mmc_boot_send_write_command( struct mmc_boot_card* card,
|
| 1199 | unsigned int xfer_type,
|
| 1200 | unsigned int data_addr )
|
| 1201 | {
|
| 1202 | struct mmc_boot_command cmd;
|
| 1203 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1204 |
|
| 1205 | /* basic check */
|
| 1206 | if( card == NULL )
|
| 1207 | {
|
| 1208 | return MMC_BOOT_E_INVAL;
|
| 1209 | }
|
| 1210 |
|
| 1211 | memset( (struct mmc_boot_command *)&cmd, 0,
|
| 1212 | sizeof(struct mmc_boot_command) );
|
| 1213 |
|
| 1214 | /* CMD24/25 Format:
|
| 1215 | * [31:0] Data Address
|
| 1216 | */
|
| 1217 | if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
|
| 1218 | {
|
| 1219 | cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK;
|
| 1220 | }
|
| 1221 | else
|
| 1222 | {
|
| 1223 | cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK;
|
| 1224 | }
|
| 1225 |
|
| 1226 | cmd.argument = data_addr;
|
| 1227 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
|
| 1228 | cmd.resp_type = MMC_BOOT_RESP_R1;
|
| 1229 |
|
| 1230 | /* send command */
|
| 1231 | mmc_ret = mmc_boot_send_command( &cmd );
|
| 1232 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1233 | {
|
| 1234 | return mmc_ret;
|
| 1235 | }
|
| 1236 |
|
| 1237 | /* Response contains 32 bit Card status. Here we'll check
|
| 1238 | BLOCK_LEN_ERROR and ADDRESS_ERROR */
|
| 1239 | if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
|
| 1240 | {
|
| 1241 | return MMC_BOOT_E_BLOCKLEN_ERR;
|
| 1242 | }
|
| 1243 | /* Misaligned address not matching block length */
|
| 1244 | if( cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR )
|
| 1245 | {
|
| 1246 | return MMC_BOOT_E_ADDRESS_ERR;
|
| 1247 | }
|
| 1248 |
|
| 1249 | return MMC_BOOT_E_SUCCESS;
|
| 1250 | }
|
| 1251 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1252 | /*
|
| 1253 | * Decode type of error caused during read and write
|
| 1254 | */
|
| 1255 | static unsigned int mmc_boot_status_error(unsigned mmc_status)
|
| 1256 | {
|
| 1257 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1258 |
|
| 1259 | /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
|
| 1260 | card/device during the data transfer */
|
| 1261 | if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
|
| 1262 | {
|
| 1263 | mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
|
| 1264 | }
|
| 1265 | /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
|
| 1266 | the data timeout period without completing the transfer */
|
| 1267 | else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
|
| 1268 | {
|
| 1269 | mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
|
| 1270 | }
|
| 1271 | /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
|
| 1272 | the card before empty storage for new received data was available.
|
| 1273 | Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
|
| 1274 | else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
|
| 1275 | {
|
| 1276 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
|
| 1277 | for now */
|
| 1278 | mmc_ret = MMC_BOOT_E_RX_OVRRUN;
|
| 1279 | }
|
| 1280 | /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to
|
| 1281 | the card before new data for sending was available. Verify that bit
|
| 1282 | FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
|
| 1283 | else if( mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN )
|
| 1284 | {
|
| 1285 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now*/
|
| 1286 | mmc_ret = MMC_BOOT_E_RX_OVRRUN;
|
| 1287 | }
|
| 1288 | return mmc_ret;
|
| 1289 | }
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1290 |
|
| 1291 | /*
|
| 1292 | * Write data_len data to address specified by data_addr. data_len is
|
| 1293 | * multiple of blocks for block data transfer.
|
| 1294 | */
|
| 1295 | static unsigned int mmc_boot_write_to_card( struct mmc_boot_host* host,
|
| 1296 | struct mmc_boot_card* card,
|
| 1297 | unsigned long long data_addr,
|
| 1298 | unsigned int data_len,
|
| 1299 | unsigned int* in )
|
| 1300 | {
|
| 1301 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1302 | unsigned int mmc_status = 0;
|
| 1303 | unsigned int* mmc_ptr = in;
|
| 1304 | unsigned int mmc_count = 0;
|
| 1305 | unsigned int mmc_reg = 0;
|
| 1306 | unsigned int addr;
|
| 1307 | unsigned int xfer_type;
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1308 | unsigned int write_error;
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1309 |
|
| 1310 | if( ( host == NULL ) || ( card == NULL ) )
|
| 1311 | {
|
| 1312 | return MMC_BOOT_E_INVAL;
|
| 1313 | }
|
| 1314 |
|
| 1315 | /* Set block length. High Capacity MMC card uses fixed 512 bytes block
|
| 1316 | length. So no need to send CMD16. */
|
| 1317 | if( card->type != MMC_BOOT_TYPE_SDHC )
|
| 1318 | {
|
| 1319 | mmc_ret = mmc_boot_set_block_len( card, card->wr_block_len );
|
| 1320 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1321 | {
|
| 1322 | dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card\
|
| 1323 | (RCA:%s)\n", mmc_ret, (char *)(card->rca) );
|
| 1324 | return mmc_ret;
|
| 1325 | }
|
| 1326 | }
|
| 1327 |
|
| 1328 | /* use multi-block mode to transfer for data larger than a block */
|
| 1329 | xfer_type = (data_len > card->rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
|
| 1330 | MMC_BOOT_XFER_SINGLE_BLOCK;
|
| 1331 |
|
| 1332 | /* For SDHC data address is specified in unit of 512B */
|
| 1333 | addr = ( card->type != MMC_BOOT_TYPE_SDHC ) ? (unsigned int) data_addr :
|
| 1334 | (unsigned int) (data_addr / 512);
|
| 1335 |
|
| 1336 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
|
| 1337 | mmc_reg = readl( MMC_BOOT_MCI_CLK );
|
| 1338 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
|
| 1339 | writel( mmc_reg, MMC_BOOT_MCI_CLK );
|
| 1340 |
|
| 1341 | /* Write data timeout period to MCI_DATA_TIMER register */
|
| 1342 | /* Data timeout period should be in card bus clock periods */
|
| 1343 | /*TODO: Fix timeout value*/
|
| 1344 | mmc_reg = 0xFFFFFFFF;
|
| 1345 | writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
|
| 1346 |
|
| 1347 | /* Write the total size of the transfer data to MCI_DATA_LENGTH register */
|
| 1348 | writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
|
| 1349 |
|
| 1350 | /* Send command to the card/device in order to start the write data xfer.
|
| 1351 | The possible commands are CMD24/25/53/60/61 */
|
| 1352 | mmc_ret = mmc_boot_send_write_command( card, xfer_type, addr );
|
| 1353 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1354 | {
|
| 1355 | dprintf(CRITICAL, "Error No.%d: Failure sending write command to the\
|
| 1356 | Card(RCA:%x)\n", mmc_ret, card->rca );
|
| 1357 | return mmc_ret;
|
| 1358 | }
|
| 1359 |
|
| 1360 | /* Set appropriate fields and write the MCI_DATA_CTL register */
|
| 1361 | /* Set ENABLE bit to 1 to enable the data transfer. */
|
| 1362 | mmc_reg = 0;
|
| 1363 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
|
| 1364 | /* Clear DIRECTION bit to 0 to enable transfer from host to card */
|
| 1365 | /* Clear MODE bit to 0 to enable block oriented data transfer. For
|
| 1366 | MMC cards only, if stream data transfer mode is desired, set
|
| 1367 | MODE bit to 1. */
|
| 1368 | /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */
|
| 1369 | /* Write size of block to be used during the data transfer to
|
| 1370 | BLOCKSIZE field */
|
| 1371 | mmc_reg |= card->wr_block_len << MMC_BOOT_MCI_BLKSIZE_POS;
|
| 1372 | writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
|
| 1373 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1374 | write_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
|
| 1375 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | \
|
| 1376 | MMC_BOOT_MCI_STAT_TX_UNDRUN;
|
| 1377 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1378 | /* Write the transfer data to SDCC3 FIFO */
|
| 1379 | /* If Data Mover is used for data transfer, prepare a command list entry
|
| 1380 | and enable the Data Mover to work with SDCC2 */
|
| 1381 | /* If Data Mover is NOT used for data xfer: */
|
| 1382 | do
|
| 1383 | {
|
| 1384 | mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1385 | mmc_status = readl( MMC_BOOT_MCI_STATUS );
|
| 1386 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1387 | if( mmc_status & write_error )
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1388 | {
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1389 | mmc_ret = mmc_boot_status_error(mmc_status);
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1390 | break;
|
| 1391 | }
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1392 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1393 | /* Write the data in MCI_FIFO register as long as TXFIFO_FULL bit of
|
| 1394 | MCI_STATUS register is 0. Continue the writes until the whole
|
| 1395 | transfer data is written. */
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1396 | if (((data_len-mmc_count) >= MMC_BOOT_MCI_FIFO_SIZE/2) &&
|
| 1397 | ( mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_HFULL ))
|
| 1398 | {
|
| 1399 | for (int i=0; i < MMC_BOOT_MCI_HFIFO_COUNT; i++ )
|
| 1400 | {
|
| 1401 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
|
| 1402 | writel( *mmc_ptr, MMC_BOOT_MCI_FIFO +
|
| 1403 | ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
|
| 1404 | mmc_ptr++;
|
| 1405 | /* increase mmc_count by word size */
|
| 1406 | mmc_count += sizeof( unsigned int );
|
| 1407 | }
|
| 1408 |
|
| 1409 | }
|
| 1410 | else if( !( mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_FULL ) && (mmc_count != data_len))
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1411 | {
|
| 1412 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
|
| 1413 | writel( *mmc_ptr, MMC_BOOT_MCI_FIFO +
|
| 1414 | ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
|
| 1415 | mmc_ptr++;
|
| 1416 | /* increase mmc_count by word size */
|
| 1417 | mmc_count += sizeof( unsigned int );
|
| 1418 | }
|
| 1419 | else if((mmc_status & MMC_BOOT_MCI_STAT_DATA_END))
|
| 1420 | {
|
| 1421 | break; //success
|
| 1422 | }
|
| 1423 |
|
| 1424 | } while(1);
|
| 1425 |
|
| 1426 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1427 | {
|
| 1428 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
|
| 1429 | Card(RCA:%x)\n", mmc_ret, card->rca );
|
| 1430 | return mmc_ret;
|
| 1431 | }
|
| 1432 |
|
| 1433 | /* Send command to the card/device in order to poll the de-assertion of
|
| 1434 | card/device BUSY condition. It is important to set PROG_ENA bit in
|
| 1435 | MCI_CLK register before sending the command. Possible commands are
|
| 1436 | CMD12/13. */
|
| 1437 | if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
|
| 1438 | {
|
| 1439 | mmc_ret = mmc_boot_send_stop_transmission( card, 1 );
|
| 1440 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1441 | {
|
| 1442 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
|
| 1443 | command to the Card(RCA:%x)\n", mmc_ret, card->rca );
|
| 1444 | return mmc_ret;
|
| 1445 | }
|
| 1446 | }
|
| 1447 | else
|
| 1448 | {
|
| 1449 | mmc_ret = mmc_boot_get_card_status( card, 1 );
|
| 1450 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1451 | {
|
| 1452 | dprintf(CRITICAL, "Error No.%d: Failure getting card status of Card(RCA:%x)\n",
|
| 1453 | mmc_ret, card->rca );
|
| 1454 | return mmc_ret;
|
| 1455 | }
|
| 1456 | }
|
| 1457 |
|
| 1458 | /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. If
|
| 1459 | PROG_DONE bit is set to 1 it means that the card finished it programming
|
| 1460 | and stopped driving DAT0 line to 0 */
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1461 | do
|
| 1462 | {
|
| 1463 | mmc_status = readl( MMC_BOOT_MCI_STATUS );
|
| 1464 | if( mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE )
|
| 1465 | {
|
| 1466 | break;
|
| 1467 | }
|
| 1468 | } while(1);
|
| 1469 |
|
| 1470 | return MMC_BOOT_E_SUCCESS;
|
| 1471 | }
|
| 1472 |
|
| 1473 |
|
| 1474 | /*
|
| 1475 | * Adjust the interface speed to optimal speed
|
| 1476 | */
|
| 1477 | static unsigned int mmc_boot_adjust_interface_speed( struct mmc_boot_host* host,
|
| 1478 | struct mmc_boot_card* card )
|
| 1479 | {
|
| 1480 | int mmc_ret;
|
| 1481 |
|
| 1482 | mmc_boot_send_ext_cmd (card);
|
| 1483 |
|
| 1484 | /* Setting HS_TIMING in EXT_CSD (CMD6) */
|
| 1485 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, MMC_BOOT_EXT_CMMC_HS_TIMING, 1);
|
| 1486 |
|
| 1487 | mmc_boot_send_ext_cmd (card);
|
| 1488 | if(mmc_ret!= MMC_BOOT_E_SUCCESS)
|
| 1489 | {
|
| 1490 | return mmc_ret;
|
| 1491 | }
|
| 1492 | #ifdef PLATFORM_MSM8X60
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1493 | mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_48MHZ);
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1494 | #else
|
| 1495 | mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_50MHZ);
|
| 1496 | #endif
|
| 1497 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1498 | {
|
| 1499 | return MMC_BOOT_E_CLK_ENABLE_FAIL;
|
| 1500 | }
|
| 1501 | return MMC_BOOT_E_SUCCESS;
|
| 1502 | }
|
| 1503 |
|
| 1504 | /*
|
| 1505 | * Reads a data of data_len from the address specified. data_len
|
| 1506 | * should be multiple of block size for block data transfer.
|
| 1507 | */
|
| 1508 | static unsigned int mmc_boot_read_from_card( struct mmc_boot_host* host,
|
| 1509 | struct mmc_boot_card* card,
|
| 1510 | unsigned long long data_addr,
|
| 1511 | unsigned int data_len,
|
| 1512 | unsigned int* out )
|
| 1513 | {
|
| 1514 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1515 | unsigned int mmc_status = 0;
|
| 1516 | unsigned int* mmc_ptr = out;
|
| 1517 | unsigned int mmc_count = 0;
|
| 1518 | unsigned int mmc_reg = 0;
|
| 1519 | unsigned int xfer_type;
|
| 1520 | unsigned int addr = 0;
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1521 | unsigned int read_error;
|
| 1522 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1523 | if( ( host == NULL ) || ( card == NULL ) )
|
| 1524 | {
|
| 1525 | return MMC_BOOT_E_INVAL;
|
| 1526 | }
|
| 1527 |
|
| 1528 | /* Set block length. High Capacity MMC card uses fixed 512 bytes block
|
| 1529 | length. So no need to send CMD16. */
|
| 1530 | if( card->type != MMC_BOOT_TYPE_SDHC )
|
| 1531 | {
|
| 1532 | mmc_ret = mmc_boot_set_block_len( card, card->rd_block_len );
|
| 1533 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1534 | {
|
| 1535 | dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
|
| 1536 | mmc_ret, (char *)(card->rca) );
|
| 1537 | return mmc_ret;
|
| 1538 | }
|
| 1539 | }
|
| 1540 |
|
| 1541 | /* use multi-block mode to transfer for data larger than a block */
|
| 1542 | xfer_type = (data_len > card->rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
|
| 1543 | MMC_BOOT_XFER_SINGLE_BLOCK;
|
| 1544 |
|
| 1545 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
|
| 1546 | /* Note: It's already enabled */
|
| 1547 |
|
| 1548 | /* If Data Mover is used for data transfer then prepare Command
|
| 1549 | List Entry and enable the Data mover to work with SDCC2 */
|
| 1550 | /* Note: Data Mover not used */
|
| 1551 |
|
| 1552 | /* Write data timeout period to MCI_DATA_TIMER register. */
|
| 1553 | /* Data timeout period should be in card bus clock periods */
|
| 1554 | mmc_reg = (unsigned long)(card->rd_timeout_ns / 1000000) *
|
| 1555 | (host->mclk_rate / 1000);
|
| 1556 | mmc_reg += 1000; // add some extra clock cycles to be safe
|
| 1557 | mmc_reg = mmc_reg/2;
|
| 1558 | writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
|
| 1559 |
|
| 1560 | /* Write the total size of the transfer data to MCI_DATA_LENGTH
|
| 1561 | register. For block xfer it must be multiple of the block
|
| 1562 | size. */
|
| 1563 | writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
|
| 1564 |
|
| 1565 | /* For SDHC data address is specified in unit of 512B */
|
| 1566 | addr = ( card->type != MMC_BOOT_TYPE_SDHC ) ? (unsigned int) data_addr :
|
| 1567 | (unsigned int) (data_addr / 512);
|
| 1568 |
|
| 1569 | /* Set appropriate fields and write the MCI_DATA_CTL register. */
|
| 1570 | /* Set ENABLE bit to 1 to enable the data transfer. */
|
| 1571 | mmc_reg = 0;
|
| 1572 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
|
| 1573 | /* Clear DIRECTION bit to 1 to enable transfer from card to host */
|
| 1574 | mmc_reg |= MMC_BOOT_MCI_DATA_DIR;
|
| 1575 | /* Clear MODE bit to 0 to enable block oriented data transfer. For
|
| 1576 | MMC cards only, if stream data transfer mode is desired, set
|
| 1577 | MODE bit to 1. */
|
| 1578 | /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */
|
| 1579 | /* Write size of block to be used during the data transfer to
|
| 1580 | BLOCKSIZE field */
|
| 1581 | mmc_reg |= (card->rd_block_len << MMC_BOOT_MCI_BLKSIZE_POS);
|
| 1582 | writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
|
| 1583 |
|
| 1584 | /* Send command to the card/device in order to start the read data
|
| 1585 | transfer. Possible commands: CMD17/18/53/60/61. */
|
| 1586 | mmc_ret = mmc_boot_send_read_command( card, xfer_type, addr );
|
| 1587 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1588 | {
|
| 1589 | dprintf(CRITICAL, "Error No.%d: Failure sending read command to the Card(RCA:%x)\n",
|
| 1590 | mmc_ret, card->rca );
|
| 1591 | return mmc_ret;
|
| 1592 | }
|
| 1593 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1594 | read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
|
| 1595 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | \
|
| 1596 | MMC_BOOT_MCI_STAT_RX_OVRRUN;
|
| 1597 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1598 | /* Read the transfer data from SDCC2 FIFO. If Data Mover is not used
|
| 1599 | read the data from the MCI_FIFO register as long as RXDATA_AVLBL
|
| 1600 | bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
|
| 1601 | DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
|
| 1602 | Continue the reads until the whole transfer data is received */
|
| 1603 |
|
| 1604 | do
|
| 1605 | {
|
| 1606 | mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1607 | mmc_status = readl( MMC_BOOT_MCI_STATUS );
|
| 1608 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1609 | if( mmc_status & read_error )
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1610 | {
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1611 | mmc_ret = mmc_boot_status_error(mmc_status);
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1612 | break;
|
| 1613 | }
|
| 1614 |
|
| 1615 | if( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL )
|
| 1616 | {
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1617 | unsigned read_count = 1;
|
| 1618 | if ( mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL)
|
| 1619 | {
|
| 1620 | read_count = MMC_BOOT_MCI_HFIFO_COUNT;
|
| 1621 | }
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1622 |
|
Shashank Mittal | 7afbf28 | 2010-06-02 19:48:31 -0700 | [diff] [blame] | 1623 | for (int i=0; i<read_count; i++)
|
| 1624 | {
|
| 1625 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
|
| 1626 | *mmc_ptr = readl( MMC_BOOT_MCI_FIFO +
|
| 1627 | ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
|
| 1628 | mmc_ptr++;
|
| 1629 | /* increase mmc_count by word size */
|
| 1630 | mmc_count += sizeof( unsigned int );
|
| 1631 | }
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 1632 | /* quit if we have read enough of data */
|
| 1633 | if (mmc_count == data_len)
|
| 1634 | break;
|
| 1635 | }
|
| 1636 | else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_END )
|
| 1637 | {
|
| 1638 | break;
|
| 1639 | }
|
| 1640 | }while(1);
|
| 1641 |
|
| 1642 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1643 | {
|
| 1644 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
|
| 1645 | Card(RCA:%x)\n", mmc_ret, card->rca );
|
| 1646 | return mmc_ret;
|
| 1647 | }
|
| 1648 |
|
| 1649 | /* In case a multiple block transfer was performed, send CMD12 to the
|
| 1650 | card/device in order to indicate the end of read data transfer */
|
| 1651 | if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
|
| 1652 | {
|
| 1653 | mmc_ret = mmc_boot_send_stop_transmission( card, 0 );
|
| 1654 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1655 | {
|
| 1656 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
|
| 1657 | command to the Card(RCA:%x)\n", mmc_ret, card->rca );
|
| 1658 | return mmc_ret;
|
| 1659 | }
|
| 1660 | }
|
| 1661 |
|
| 1662 | return MMC_BOOT_E_SUCCESS;
|
| 1663 | }
|
| 1664 |
|
| 1665 | /*
|
| 1666 | * Initialize host structure, set and enable clock-rate and power mode.
|
| 1667 | */
|
| 1668 | unsigned int mmc_boot_init( struct mmc_boot_host* host )
|
| 1669 | {
|
| 1670 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 1671 | unsigned int mmc_pwr = 0;
|
| 1672 |
|
| 1673 |
|
| 1674 | host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE;
|
| 1675 | host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY;
|
| 1676 | host->clk_enabled = 0;
|
| 1677 |
|
| 1678 | /* clock frequency should be less than 400KHz in identification mode */
|
| 1679 | mmc_ret = mmc_boot_enable_clock( host, MMC_CLK_400KHZ);
|
| 1680 |
|
| 1681 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 1682 | {
|
| 1683 | return MMC_BOOT_E_CLK_ENABLE_FAIL;
|
| 1684 | }
|
| 1685 |
|
| 1686 | /* set power mode*/
|
| 1687 | /* give some time to reach minimum voltate */
|
| 1688 | mdelay(2);
|
| 1689 | mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP;
|
| 1690 | mmc_pwr |= MMC_BOOT_MCI_PWR_ON;
|
| 1691 | mmc_pwr |= MMC_BOOT_MCI_PWR_UP;
|
| 1692 | writel( mmc_pwr, MMC_BOOT_MCI_POWER );
|
| 1693 | /* some more time to stabilize voltage */
|
| 1694 | mdelay(2);
|
| 1695 |
|
| 1696 | return MMC_BOOT_E_SUCCESS;
|
| 1697 | }
|
| 1698 |
|
| 1699 | /*
|
| 1700 | * Performs card identification process by getting card's unique identification
|
| 1701 | * number (CID) and relative card address (RCA). After that card will be in
|
| 1702 | * stand-by state.
|
| 1703 | */
|
| 1704 | static unsigned int mmc_boot_identify_card( struct mmc_boot_host* host,
|
| 1705 | struct mmc_boot_card* card)
|
| 1706 | {
|
| 1707 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
|
| 1708 |
|
| 1709 | /* basic check */
|
| 1710 | if( ( host == NULL ) || ( card == NULL ) )
|
| 1711 | {
|
| 1712 | return MMC_BOOT_E_INVAL;
|
| 1713 | }
|
| 1714 |
|
| 1715 | /* Ask card to send its unique card identification (CID) number (CMD2) */
|
| 1716 | mmc_return = mmc_boot_all_send_cid( card );
|
| 1717 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1718 | {
|
| 1719 | dprintf(CRITICAL, "Error No. %d: Failure getting card's CID number!\n",
|
| 1720 | mmc_return );
|
| 1721 | return mmc_return;
|
| 1722 | }
|
| 1723 |
|
| 1724 | /* Ask card to send a relative card address (RCA) (CMD3) */
|
| 1725 | mmc_return = mmc_boot_send_relative_address( card );
|
| 1726 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1727 | {
|
| 1728 | dprintf(CRITICAL, "Error No. %d: Failure getting card's RCA!\n",
|
| 1729 | mmc_return );
|
| 1730 | return mmc_return;
|
| 1731 | }
|
| 1732 |
|
| 1733 | /* Set the card status as active */
|
| 1734 | card->status = MMC_BOOT_STATUS_ACTIVE;
|
| 1735 |
|
| 1736 | /* Get card's CSD register (CMD9) */
|
| 1737 | mmc_return = mmc_boot_send_csd( card );
|
| 1738 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1739 | {
|
| 1740 | dprintf(CRITICAL, "Error No.%d: Failure getting card's CSD information!\n",
|
| 1741 | mmc_return );
|
| 1742 | return mmc_return;
|
| 1743 | }
|
| 1744 |
|
| 1745 | /* Once CSD is received, set read and write timeout value now itself */
|
| 1746 | mmc_return = mmc_boot_set_read_timeout( host, card );
|
| 1747 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1748 | {
|
| 1749 | dprintf(CRITICAL, "Error No.%d: Failure setting Read Timeout value!\n",
|
| 1750 | mmc_return );
|
| 1751 | return mmc_return;
|
| 1752 | }
|
| 1753 |
|
| 1754 | mmc_return = mmc_boot_set_write_timeout( host, card );
|
| 1755 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1756 | {
|
| 1757 | dprintf(CRITICAL, "Error No.%d: Failure setting Write Timeout value!\n",
|
| 1758 | mmc_return );
|
| 1759 | return mmc_return;
|
| 1760 | }
|
| 1761 |
|
| 1762 | return MMC_BOOT_E_SUCCESS;
|
| 1763 | }
|
| 1764 |
|
| 1765 | /*
|
| 1766 | * Routine to initialize MMC card. It resets a card to idle state, verify operating
|
| 1767 | * voltage and set the card inready state.
|
| 1768 | */
|
| 1769 | static unsigned int mmc_boot_init_card( struct mmc_boot_host* host,
|
| 1770 | struct mmc_boot_card* card )
|
| 1771 | {
|
| 1772 | unsigned int mmc_retry = 0;
|
| 1773 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
|
| 1774 |
|
| 1775 | /* basic check */
|
| 1776 | if( ( host == NULL ) || ( card == NULL ) )
|
| 1777 | {
|
| 1778 | return MMC_BOOT_E_INVAL;
|
| 1779 | }
|
| 1780 |
|
| 1781 | /* 1. Card Reset - not necessary*/
|
| 1782 | mmc_return = mmc_boot_reset_cards();
|
| 1783 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1784 | {
|
| 1785 | dprintf(CRITICAL, "Error No.:%d: Failure resetting MMC cards!\n", mmc_return);
|
| 1786 | return mmc_return;
|
| 1787 | }
|
| 1788 |
|
| 1789 | /* 2. Card Initialization process */
|
| 1790 |
|
| 1791 | /* Send CMD1 to identify and reject cards that do not match host's VDD range
|
| 1792 | profile. Cards sends its OCR register in response.
|
| 1793 | */
|
| 1794 | mmc_retry = 0;
|
| 1795 | do
|
| 1796 | {
|
| 1797 | mmc_return = mmc_boot_send_op_cond( host, card );
|
| 1798 | /* Card returns busy status. We'll retry again! */
|
| 1799 | if( mmc_return == MMC_BOOT_E_CARD_BUSY )
|
| 1800 | {
|
| 1801 | mmc_retry++;
|
| 1802 | mdelay(200);
|
| 1803 | continue;
|
| 1804 | }
|
| 1805 | else if( mmc_return == MMC_BOOT_E_SUCCESS )
|
| 1806 | {
|
| 1807 | break;
|
| 1808 | }
|
| 1809 | else
|
| 1810 | {
|
| 1811 | dprintf(CRITICAL, "Error No. %d: Failure Initializing MMC Card!\n",
|
| 1812 | mmc_return );
|
| 1813 | return mmc_return;
|
| 1814 | }
|
| 1815 | }while( mmc_retry < host->cmd_retry );
|
| 1816 |
|
| 1817 | /* If card still returned busy status we are out of luck.
|
| 1818 | * Card cannot be initialized */
|
| 1819 | if( mmc_return == MMC_BOOT_E_CARD_BUSY )
|
| 1820 | {
|
| 1821 | dprintf(CRITICAL, "Error No. %d: Card has busy status set. \
|
| 1822 | Initialization not completed\n", mmc_return );
|
| 1823 | return MMC_BOOT_E_CARD_BUSY;
|
| 1824 | }
|
| 1825 |
|
| 1826 | /*Assuming high capacity mmc card*/
|
| 1827 | card->type = MMC_BOOT_TYPE_SDHC;
|
| 1828 |
|
| 1829 | return MMC_BOOT_E_SUCCESS;
|
| 1830 | }
|
| 1831 |
|
| 1832 |
|
| 1833 | /*
|
| 1834 | * Performs initialization and identification of all the MMC cards connected
|
| 1835 | * to the host.
|
| 1836 | */
|
| 1837 |
|
| 1838 | static unsigned int mmc_boot_init_and_identify_cards( struct mmc_boot_host* host, struct mmc_boot_card* card )
|
| 1839 | {
|
| 1840 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
|
| 1841 |
|
| 1842 | /* Basic check */
|
| 1843 | if( host == NULL )
|
| 1844 | {
|
| 1845 | return MMC_BOOT_E_INVAL;
|
| 1846 | }
|
| 1847 |
|
| 1848 | /* Initialize MMC card structure */
|
| 1849 | card->status = MMC_BOOT_STATUS_INACTIVE;
|
| 1850 | card->rd_block_len = MMC_BOOT_RD_BLOCK_LEN;
|
| 1851 | card->wr_block_len = MMC_BOOT_WR_BLOCK_LEN;
|
| 1852 |
|
| 1853 | /* Start initialization process (CMD0 & CMD1) */
|
| 1854 | mmc_return = mmc_boot_init_card( host, card );
|
| 1855 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1856 | {
|
| 1857 | return mmc_return;
|
| 1858 | }
|
| 1859 |
|
| 1860 | /* Start card identification process (CMD2, CMD3 & CMD9)*/
|
| 1861 | mmc_return = mmc_boot_identify_card( host, card );
|
| 1862 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1863 | {
|
| 1864 | return mmc_return;
|
| 1865 | }
|
| 1866 |
|
| 1867 | /* Select the card (CMD7) */
|
| 1868 | mmc_return = mmc_boot_select_card( card, card->rca );
|
| 1869 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1870 | {
|
| 1871 | dprintf(CRITICAL, "Error No.%d: Failure selecting the Card with RCA: %x\n",
|
| 1872 | mmc_return, card->rca );
|
| 1873 | return mmc_return;
|
| 1874 | }
|
| 1875 |
|
| 1876 | /* set interface speed */
|
| 1877 | mmc_return = mmc_boot_adjust_interface_speed( host, card );
|
| 1878 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1879 | {
|
| 1880 | dprintf(CRITICAL, "Error No.%d: Error adjusting interface speed!\n",
|
| 1881 | mmc_return );
|
| 1882 | return mmc_return;
|
| 1883 | }
|
| 1884 |
|
| 1885 | /* enable wide bus */
|
| 1886 | mmc_return = mmc_boot_set_bus_width( card, MMC_BOOT_BUS_WIDTH_4_BIT );
|
| 1887 | if( mmc_return != MMC_BOOT_E_SUCCESS )
|
| 1888 | {
|
| 1889 | dprintf(CRITICAL, "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n",
|
| 1890 | mmc_return, card->rca );
|
| 1891 | return mmc_return;
|
| 1892 | }
|
| 1893 |
|
| 1894 | return MMC_BOOT_E_SUCCESS;
|
| 1895 | }
|
| 1896 |
|
| 1897 | /*
|
| 1898 | * Read MBR from MMC card and fill partition table.
|
| 1899 | */
|
| 1900 | static unsigned int mmc_boot_read_MBR(void)
|
| 1901 | {
|
| 1902 | unsigned char buffer[MMC_BOOT_RD_BLOCK_LEN];
|
| 1903 | unsigned int dtype;
|
| 1904 | unsigned int dfirstsec;
|
| 1905 | unsigned int EBR_first_sec;
|
| 1906 | unsigned int EBR_current_sec;
|
| 1907 | int ret = 0;
|
| 1908 | int idx, i;
|
| 1909 |
|
| 1910 | /* Print out the MBR first */
|
| 1911 | ret = mmc_boot_read_from_card( &mmc_host, &mmc_card, 0, \
|
| 1912 | MMC_BOOT_RD_BLOCK_LEN, \
|
| 1913 | (unsigned int *)buffer);
|
| 1914 | if (ret)
|
| 1915 | {
|
| 1916 | return ret;
|
| 1917 | }
|
| 1918 |
|
| 1919 | /* Check to see if signature exists */
|
| 1920 | if ((buffer[TABLE_SIGNATURE] != 0x55) || \
|
| 1921 | (buffer[TABLE_SIGNATURE + 1] != 0xAA))
|
| 1922 | {
|
| 1923 | return -1;
|
| 1924 | }
|
| 1925 |
|
| 1926 | /* Print out the first 4 partition */
|
| 1927 | idx = TABLE_ENTRY_0;
|
| 1928 | for (i = 0; i < 4; i++)
|
| 1929 | {
|
| 1930 | mbr[mmc_partition_count].dstatus = \
|
| 1931 | buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_STATUS];
|
| 1932 | mbr[mmc_partition_count].dtype = \
|
| 1933 | buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
|
| 1934 | mbr[mmc_partition_count].dfirstsec = \
|
| 1935 | GET_LWORD_FROM_BYTE(&buffer[idx + \
|
| 1936 | i * TABLE_ENTRY_SIZE + \
|
| 1937 | OFFSET_FIRST_SEC]);
|
| 1938 | mbr[mmc_partition_count].dsize = \
|
| 1939 | GET_LWORD_FROM_BYTE(&buffer[idx + \
|
| 1940 | i * TABLE_ENTRY_SIZE + \
|
| 1941 | OFFSET_SIZE]);
|
| 1942 | dtype = mbr[mmc_partition_count].dtype;
|
| 1943 | dfirstsec = mbr[mmc_partition_count].dfirstsec;
|
| 1944 | mbr_fill_name(&mbr[mmc_partition_count], \
|
| 1945 | mbr[mmc_partition_count].dtype);
|
| 1946 | mmc_partition_count++;
|
| 1947 | if (mmc_partition_count == MAX_PARTITIONS)
|
| 1948 | return ret;
|
| 1949 | }
|
| 1950 |
|
| 1951 | /* See if the last partition is EBR, if not, parsing is done */
|
| 1952 | if (dtype != 0x05)
|
| 1953 | {
|
| 1954 | return ret;
|
| 1955 | }
|
| 1956 |
|
| 1957 | EBR_first_sec = dfirstsec;
|
| 1958 | EBR_current_sec = dfirstsec;
|
| 1959 |
|
| 1960 | ret = mmc_boot_read_from_card( &mmc_host, &mmc_card, \
|
| 1961 | (EBR_first_sec * 512), \
|
| 1962 | MMC_BOOT_RD_BLOCK_LEN, \
|
| 1963 | (unsigned int *)buffer);
|
| 1964 | if (ret)
|
| 1965 | {
|
| 1966 | return ret;
|
| 1967 | }
|
| 1968 | /* Loop to parse the EBR */
|
| 1969 | for (i = 0;; i++)
|
| 1970 | {
|
| 1971 | if ((buffer[TABLE_SIGNATURE] != 0x55) || (buffer[TABLE_SIGNATURE + 1] != 0xAA))
|
| 1972 | {
|
| 1973 | break;
|
| 1974 | }
|
| 1975 | mbr[mmc_partition_count].dstatus = \
|
| 1976 | buffer[TABLE_ENTRY_0 + OFFSET_STATUS];
|
| 1977 | mbr[mmc_partition_count].dtype = \
|
| 1978 | buffer[TABLE_ENTRY_0 + OFFSET_TYPE];
|
| 1979 | mbr[mmc_partition_count].dfirstsec = \
|
| 1980 | GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 + \
|
| 1981 | OFFSET_FIRST_SEC]) + \
|
| 1982 | EBR_current_sec;
|
| 1983 | mbr[mmc_partition_count].dsize = \
|
| 1984 | GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 + \
|
| 1985 | OFFSET_SIZE]);
|
| 1986 | mbr_fill_name(&(mbr[mmc_partition_count]), \
|
| 1987 | mbr[mmc_partition_count].dtype);
|
| 1988 | mmc_partition_count++;
|
| 1989 | if (mmc_partition_count == MAX_PARTITIONS)
|
| 1990 | return ret;
|
| 1991 |
|
| 1992 | dfirstsec = GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
|
| 1993 | if(dfirstsec == 0)
|
| 1994 | {
|
| 1995 | /* Getting to the end of the EBR tables */
|
| 1996 | break;
|
| 1997 | }
|
| 1998 | /* More EBR to follow - read in the next EBR sector */
|
| 1999 | ret = mmc_boot_read_from_card( &mmc_host, &mmc_card, \
|
| 2000 | ((EBR_first_sec + dfirstsec) * 512), \
|
| 2001 | MMC_BOOT_RD_BLOCK_LEN, \
|
| 2002 | (unsigned int *)buffer);
|
| 2003 | if (ret)
|
| 2004 | {
|
| 2005 | return ret;
|
| 2006 | }
|
| 2007 | EBR_current_sec = EBR_first_sec + dfirstsec;
|
| 2008 | }
|
| 2009 | return ret;
|
| 2010 | }
|
| 2011 |
|
| 2012 | /*
|
| 2013 | * Entry point to MMC boot process
|
| 2014 | */
|
Subbaraman Narayanamurthy | 4b43c35 | 2010-09-24 13:20:52 -0700 | [diff] [blame] | 2015 | unsigned int mmc_boot_main(unsigned char slot, unsigned int base)
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2016 | {
|
| 2017 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
|
| 2018 |
|
| 2019 | memset( (struct mmc_boot_host*)&mmc_host, 0, sizeof( struct mmc_boot_host ) );
|
| 2020 | memset( (struct mmc_boot_card*)&mmc_card, 0, sizeof(struct mmc_boot_card) );
|
| 2021 |
|
Subbaraman Narayanamurthy | 4b43c35 | 2010-09-24 13:20:52 -0700 | [diff] [blame] | 2022 | mmc_slot = slot;
|
| 2023 | mmc_boot_mci_base = base;
|
| 2024 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2025 | #ifndef PLATFORM_MSM8X60
|
| 2026 | /* Waiting for modem to come up */
|
| 2027 | while (readl(MSM_SHARED_BASE + 0x14) != 1);
|
| 2028 | #endif
|
| 2029 | /* Initialize necessary data structure and enable/set clock and power */
|
| 2030 | dprintf(INFO," Initializing MMC host data structure and clock!\n" );
|
| 2031 | mmc_ret = mmc_boot_init( &mmc_host );
|
| 2032 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 2033 | {
|
| 2034 | dprintf(CRITICAL, "MMC Boot: Error Initializing MMC Card!!!\n" );
|
| 2035 | return MMC_BOOT_E_FAILURE;
|
| 2036 | }
|
| 2037 |
|
| 2038 | /* Initialize and identify cards connected to host */
|
| 2039 | mmc_ret = mmc_boot_init_and_identify_cards( &mmc_host, &mmc_card );
|
| 2040 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 2041 | {
|
| 2042 | dprintf(CRITICAL, "MMC Boot: Failure detecting MMC card!!!\n" );
|
| 2043 | return MMC_BOOT_E_FAILURE;
|
| 2044 | }
|
| 2045 |
|
| 2046 | /* Read MBR of the card */
|
| 2047 | mmc_ret = mmc_boot_read_MBR();
|
| 2048 | if( mmc_ret != MMC_BOOT_E_SUCCESS )
|
| 2049 | {
|
| 2050 | dprintf(CRITICAL, "MMC Boot: MBR read failed!\n" );
|
| 2051 | return MMC_BOOT_E_FAILURE;
|
| 2052 | }
|
| 2053 |
|
| 2054 | return MMC_BOOT_E_SUCCESS;
|
| 2055 | }
|
| 2056 |
|
| 2057 | /*
|
| 2058 | * MMC write function
|
| 2059 | */
|
| 2060 | unsigned int mmc_write (unsigned long long data_addr, unsigned int data_len, unsigned int* in)
|
| 2061 | {
|
| 2062 | int val = 0;
|
| 2063 | unsigned int write_size = ((unsigned)(0xFFFFFF/512))*512;
|
| 2064 | unsigned offset = 0;
|
| 2065 | unsigned int *sptr = in;
|
Subbaraman Narayanamurthy | c95b5b1 | 2010-08-31 13:19:48 -0700 | [diff] [blame] | 2066 |
|
| 2067 | if(data_len % 512)
|
| 2068 | data_len = ROUND_TO_PAGE(data_len, 511);
|
| 2069 |
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2070 | while(data_len > write_size)
|
| 2071 | {
|
| 2072 | val = mmc_boot_write_to_card( &mmc_host, &mmc_card, \
|
| 2073 | data_addr + offset, \
|
| 2074 | write_size, sptr);
|
| 2075 | if(val)
|
| 2076 | {
|
| 2077 | return val;
|
| 2078 | }
|
| 2079 |
|
| 2080 | sptr += (write_size/sizeof(unsigned));
|
| 2081 | offset += write_size;
|
| 2082 | data_len -= write_size;
|
| 2083 | }
|
| 2084 | if (data_len)
|
| 2085 | {
|
| 2086 | val = mmc_boot_write_to_card( &mmc_host, &mmc_card, \
|
| 2087 | data_addr + offset, \
|
| 2088 | data_len, sptr);
|
| 2089 | }
|
| 2090 | return val;
|
| 2091 | }
|
| 2092 |
|
| 2093 | /*
|
| 2094 | * MMC read function
|
| 2095 | */
|
| 2096 | unsigned int mmc_read (unsigned long long data_addr, unsigned int* out, unsigned int data_len)
|
| 2097 | {
|
| 2098 | int val = 0;
|
| 2099 | val = mmc_boot_read_from_card( &mmc_host, &mmc_card, data_addr, data_len, out);
|
| 2100 | return val;
|
| 2101 | }
|
| 2102 |
|
| 2103 | /*
|
| 2104 | * Fill name for android partition found.
|
| 2105 | */
|
| 2106 | static void mbr_fill_name (struct mbr_entry *mbr_ent, unsigned int type)
|
| 2107 | {
|
| 2108 | switch(type)
|
| 2109 | {
|
| 2110 | memset(mbr_ent->name, 0, 64);
|
David Ng | 77849d3 | 2010-08-04 15:18:50 -0700 | [diff] [blame] | 2111 | case MMC_MODEM_TYPE:
|
Subbaraman Narayanamurthy | 88aa13d | 2010-08-25 19:06:16 -0700 | [diff] [blame] | 2112 | case MMC_MODEM_TYPE2:
|
David Ng | 77849d3 | 2010-08-04 15:18:50 -0700 | [diff] [blame] | 2113 | /* if there are more than one with type "modem", mmc_ptn_offset will return the first one */
|
| 2114 | memcpy(mbr_ent->name,"modem",5);
|
| 2115 | break;
|
Ajay Dudani | 0270463 | 2010-08-30 14:40:07 -0700 | [diff] [blame] | 2116 | case MMC_SBL1_TYPE:
|
| 2117 | memcpy(mbr_ent->name,"sbl1",4);
|
| 2118 | break;
|
| 2119 | case MMC_SBL2_TYPE:
|
| 2120 | memcpy(mbr_ent->name,"sbl2",4);
|
| 2121 | break;
|
| 2122 | case MMC_SBL3_TYPE:
|
| 2123 | memcpy(mbr_ent->name,"sbl3",4);
|
| 2124 | break;
|
| 2125 | case MMC_RPM_TYPE:
|
| 2126 | memcpy(mbr_ent->name,"rpm",3);
|
| 2127 | break;
|
| 2128 | case MMC_TZ_TYPE:
|
| 2129 | memcpy(mbr_ent->name,"tz",2);
|
| 2130 | break;
|
| 2131 | case MMC_ABOOT_TYPE:
|
| 2132 | memcpy(mbr_ent->name,"aboot",5);
|
| 2133 | break;
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2134 | case MMC_BOOT_TYPE:
|
David Ng | 77849d3 | 2010-08-04 15:18:50 -0700 | [diff] [blame] | 2135 | memcpy(mbr_ent->name,"boot",4);
|
| 2136 | break;
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2137 | case MMC_USERDATA_TYPE:
|
David Ng | 77849d3 | 2010-08-04 15:18:50 -0700 | [diff] [blame] | 2138 | strcpy((char *)mbr_ent->name,(const char *)ext3_partitions[ext3_count]);
|
| 2139 | ext3_count++;
|
| 2140 | break;
|
Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame] | 2141 | };
|
| 2142 | }
|
| 2143 |
|
| 2144 | /*
|
| 2145 | * Returns offset of given partition
|
| 2146 | */
|
| 2147 | unsigned long long mmc_ptn_offset (unsigned char * name)
|
| 2148 | {
|
| 2149 | unsigned n;
|
| 2150 | for(n = 0; n < mmc_partition_count; n++) {
|
| 2151 | if(!strcmp((const char *)mbr[n].name, (const char *)name)) {
|
| 2152 | return (mbr[n].dfirstsec * MMC_BOOT_RD_BLOCK_LEN);
|
| 2153 | }
|
| 2154 | }
|
| 2155 | return 0;
|
| 2156 | }
|
| 2157 |
|
Subbaraman Narayanamurthy | c95b5b1 | 2010-08-31 13:19:48 -0700 | [diff] [blame] | 2158 | unsigned long long mmc_ptn_size (unsigned char * name)
|
| 2159 | {
|
| 2160 | unsigned n;
|
| 2161 | for(n = 0; n < mmc_partition_count; n++) {
|
| 2162 | if(!strcmp((const char *)mbr[n].name, (const char *)name)) {
|
| 2163 | return (mbr[n].dsize * MMC_BOOT_RD_BLOCK_LEN);
|
| 2164 | }
|
| 2165 | }
|
| 2166 | return 0;
|
| 2167 | }
|