blob: 8f3da018073932f316b55f5768fbe7e07385164b [file] [log] [blame]
Channagoud Kadabi92db1122014-06-25 16:00:13 -04001/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <platform/irqs.h>
32#include <platform/gpio.h>
33#include <reg.h>
34#include <target.h>
35#include <platform.h>
36#include <dload_util.h>
37#include <uart_dm.h>
38#include <mmc.h>
39#include <spmi.h>
40#include <board.h>
41#include <smem.h>
42#include <baseband.h>
43#include <dev/keys.h>
44#include <crypto5_wrapper.h>
45#include <hsusb.h>
46#include <clock.h>
47#include <partition_parser.h>
48#include <scm.h>
49#include <platform/clock.h>
50#include <platform/gpio.h>
51#include <platform/timer.h>
52#include <stdlib.h>
53
54extern bool target_use_signed_kernel(void);
55static void set_sdc_power_ctrl();
56
57static unsigned int target_id;
58
59#if MMC_SDHCI_SUPPORT
60struct mmc_device *dev;
61#endif
62
63#define PMIC_ARB_CHANNEL_NUM 0
64#define PMIC_ARB_OWNER_ID 0
65
66#define WDOG_DEBUG_DISABLE_BIT 17
67
68#define CE_INSTANCE 2
69#define CE_EE 1
70#define CE_FIFO_SIZE 64
71#define CE_READ_PIPE 3
72#define CE_WRITE_PIPE 2
73#define CE_READ_PIPE_LOCK_GRP 0
74#define CE_WRITE_PIPE_LOCK_GRP 0
75#define CE_ARRAY_SIZE 20
76
77#define FASTBOOT_MODE 0x77665500
78
79#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
80
81#if MMC_SDHCI_SUPPORT
82static uint32_t mmc_sdhci_base[] =
83 { MSM_SDC1_SDHCI_BASE };
84static uint32_t mmc_sdc_pwrctl_irq[] =
85 { SDCC1_PWRCTL_IRQ };
86#endif
87
88static uint32_t mmc_sdc_base[] =
89 { MSM_SDC1_BASE };
90
91void target_early_init(void)
92{
93#if WITH_DEBUG_UART
94 uart_dm_init(2, 0, BLSP1_UART2_BASE);
95#endif
96}
97
98/* Return 1 if vol_up pressed */
99static int target_volume_up()
100{
101 return 0;
102}
103
104/* Return 1 if vol_down pressed */
105uint32_t target_volume_down()
106{
107 return 0;
108}
109
110static void target_keystatus()
111{
112 keys_init();
113
114 if (target_volume_down())
115 keys_post_event(KEY_VOLUMEDOWN, 1);
116
117 if (target_volume_up())
118 keys_post_event(KEY_VOLUMEUP, 1);
119}
120
121/* Set up params for h/w CE. */
122void target_crypto_init_params()
123{
124 struct crypto_init_params ce_params;
125
126 /* Set up base addresses and instance. */
127 ce_params.crypto_instance = CE_INSTANCE;
128 ce_params.crypto_base = MSM_CE2_BASE;
129 ce_params.bam_base = MSM_CE2_BAM_BASE;
130
131 /* Set up BAM config. */
132 ce_params.bam_ee = CE_EE;
133 ce_params.pipes.read_pipe = CE_READ_PIPE;
134 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
135 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
136 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
137
138 /* Assign buffer sizes. */
139 ce_params.num_ce = CE_ARRAY_SIZE;
140 ce_params.read_fifo_size = CE_FIFO_SIZE;
141 ce_params.write_fifo_size = CE_FIFO_SIZE;
142
143 /* BAM is initialized by TZ for this platform.
144 * Do not do it again as the initialization address space
145 * is locked.
146 */
147 ce_params.do_bam_init = 0;
148
149 crypto_init_params(&ce_params);
150}
151
152crypto_engine_type board_ce_type(void)
153{
154 return CRYPTO_ENGINE_TYPE_HW;
155}
156
157#if MMC_SDHCI_SUPPORT
158static void target_mmc_sdhci_init()
159{
160 struct mmc_config_data config = {0};
161
162 config.bus_width = DATA_BUS_WIDTH_8BIT;
163 config.max_clk_rate = MMC_CLK_96MHZ;
164
165 /* Trying Slot 1*/
166 config.slot = 1;
167 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
168 config.pwrctl_base = mmc_sdc_base[config.slot - 1];
169 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
170
171 if (!(dev = mmc_init(&config))) {
172 dprintf(CRITICAL, "mmc init failed!");
173 ASSERT(0);
174 }
175
176 /*
177 * MMC initialization is complete, read the partition table info
178 */
179 if (partition_read_table()) {
180 dprintf(CRITICAL, "Error reading the partition table info\n");
181 ASSERT(0);
182 }
183}
184
185void *target_mmc_device()
186{
187 return (void *) dev;
188}
189
190#else
191
192static void target_mmc_mci_init()
193{
194 uint32_t base_addr;
195 uint8_t slot;
196
197 /* Trying Slot 1 */
198 slot = 1;
199 base_addr = mmc_sdc_base[slot - 1];
200
201 if (mmc_boot_main(slot, base_addr))
202 {
203 dprintf(CRITICAL, "mmc init failed!");
204 ASSERT(0);
205 }
206}
207
208/*
209 * Function to set the capabilities for the host
210 */
211void target_mmc_caps(struct mmc_host *host)
212{
213 host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
214 host->caps.ddr_mode = 0;
215 host->caps.hs200_mode = 1;
216 host->caps.hs_clk_rate = MMC_CLK_96MHZ;
217}
218
219#endif
220
221void target_init(void)
222{
223 dprintf(INFO, "target_init()\n");
224
225 target_keystatus();
226
227 if (target_use_signed_kernel())
228 target_crypto_init_params();
229
230 /*
231 * Set drive strength & pull ctrl for
232 * emmc
233 */
234 set_sdc_power_ctrl();
235
236#if MMC_SDHCI_SUPPORT
237 target_mmc_sdhci_init();
238#else
239 target_mmc_mci_init();
240#endif
241}
242
243unsigned board_machtype(void)
244{
245 return target_id;
246}
247
248void target_fastboot_init(void)
249{
250}
251
252/* Detect the target type */
253void target_detect(struct board_data *board)
254{
255 /* This property is filled as part of board.c */
256}
257
258/* Detect the modem type */
259void target_baseband_detect(struct board_data *board)
260{
261 uint32_t platform;
262 uint32_t platform_subtype;
263
264 platform = board->platform;
265 platform_subtype = board->platform_subtype;
266
267 /*
268 * Look for platform subtype if present, else
269 * check for platform type to decide on the
270 * baseband type
271 */
272 switch (platform_subtype) {
273 case HW_PLATFORM_SUBTYPE_UNKNOWN:
274 break;
275 default:
276 dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
277 ASSERT(0);
278 };
279
280 switch (platform) {
281 case FSM9010:
282 board->baseband = BASEBAND_MSM;
283 break;
284 default:
285 dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
286 ASSERT(0);
287 };
288}
289
290unsigned target_baseband()
291{
292 return board_baseband();
293}
294
295void target_serialno(unsigned char *buf)
296{
297 unsigned int serialno;
298 if (target_is_emmc_boot()) {
299 serialno = mmc_get_psn();
300 snprintf((char *)buf, 13, "%x", serialno);
301 }
302}
303
304unsigned check_reboot_mode(void)
305{
306 uint32_t restart_reason = 0;
307 uint32_t restart_reason_addr;
308
309 restart_reason_addr = RESTART_REASON_ADDR;
310
311 /* Read reboot reason and scrub it */
312 restart_reason = readl(restart_reason_addr);
313 writel(0x00, restart_reason_addr);
314
315 return restart_reason;
316}
317
318void reboot_device(unsigned reboot_reason)
319{
320 /* Write the reboot reason */
321 writel(reboot_reason, RESTART_REASON_ADDR);
322
323 /* Disable Watchdog Debug.
324 * Required becuase of a H/W bug which causes the system to
325 * reset partially even for non watchdog resets.
326 */
327 writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
328
329 dsb();
330
331 /* Wait until the write takes effect. */
332 while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
333
334 /* Drop PS_HOLD for MSM */
335 writel(0x00, MPM2_MPM_PS_HOLD);
336
337 mdelay(5000);
338
339 dprintf(CRITICAL, "Rebooting failed\n");
340}
341
342int set_download_mode(enum dload_mode mode)
343{
344 dload_util_write_cookie(mode == NORMAL_DLOAD ?
345 DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
346
347 return 0;
348}
349
350/* Check if MSM needs VBUS mimic for USB */
351static int target_needs_vbus_mimic()
352{
353 return 1;
354}
355
356/* Do target specific usb initialization */
357void target_usb_init(void)
358{
359 uint32_t val;
360
361 extern void ulpi_write(unsigned val, unsigned reg);
362
363 if (target_needs_vbus_mimic()) {
364 /* Select and enable external configuration with USB PHY */
365 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
366
367 /* Enable sess_vld */
368 val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
369 writel(val, USB_GENCONFIG_2);
370
371 /* Enable external vbus configuration in the LINK */
372 val = readl(USB_USBCMD);
373 val |= SESS_VLD_CTRL;
374 writel(val, USB_USBCMD);
375 }
376}
377
378/* Returns 1 if target supports continuous splash screen. */
379int target_cont_splash_screen()
380{
381 return 0;
382}
383
384unsigned target_pause_for_battery_charge(void)
385{
386 return 0;
387}
388
389void target_uninit(void)
390{
391#if MMC_SDHCI_SUPPORT
392 mmc_put_card_to_sleep(dev);
393#else
394 mmc_put_card_to_sleep();
395#endif
396}
397
398void shutdown_device()
399{
400 dprintf(CRITICAL, "Going down for shutdown.\n");
401
402 /* Drop PS_HOLD for MSM */
403 writel(0x00, MPM2_MPM_PS_HOLD);
404
405 mdelay(5000);
406
407 dprintf(CRITICAL, "Shutdown failed\n");
408}
409
410static void set_sdc_power_ctrl()
411{
412 /* Drive strength configs for sdc pins */
413 struct tlmm_cfgs sdc1_hdrv_cfg[] =
414 {
415 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
416 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
417 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
418 };
419
420 /* Pull configs for sdc pins */
421 struct tlmm_cfgs sdc1_pull_cfg[] =
422 {
423 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
424 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
425 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
426 };
427
428 /* Set the drive strength & pull control values */
429 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
430 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
431}
432
433int emmc_recovery_init(void)
434{
435 extern int _emmc_recovery_init(void);
436
437 return _emmc_recovery_init();
438}
439
440void target_usb_stop(void)
441{
442}