Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <bits.h> |
| 31 | #include <reg.h> |
| 32 | #include <err.h> |
| 33 | #include <smem.h> |
| 34 | #include <clock.h> |
| 35 | #include <mipi_dsi.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <qtimer.h> |
| 38 | #include <arch/defines.h> |
| 39 | |
| 40 | #define VCO_REF_CLOCK_RATE 19200000 |
| 41 | |
| 42 | #define DSIPHY_T_TA_GO_TIM_COUNT 0x014 |
| 43 | #define DSIPHY_T_TA_SURE_TIM_COUNT 0x018 |
| 44 | #define DSIPHY_PLL_POWERUP_CTRL 0x034 |
| 45 | #define DSIPHY_PLL_PROP_CHRG_PUMP_CTRL 0x038 |
| 46 | #define DSIPHY_PLL_INTEG_CHRG_PUMP_CTRL 0x03c |
| 47 | #define DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL 0x044 |
| 48 | #define DSIPHY_PLL_VCO_CTRL 0x048 |
| 49 | #define DSIPHY_PLL_GMP_CTRL_DIG_TST 0x04c |
| 50 | #define DSIPHY_PLL_PHA_ERR_CTRL_0 0x050 |
| 51 | #define DSIPHY_PLL_LOCK_FILTER 0x054 |
| 52 | #define DSIPHY_PLL_UNLOCK_FILTER 0x058 |
| 53 | #define DSIPHY_PLL_INPUT_DIV_PLL_OVR 0x05c |
| 54 | #define DSIPHY_PLL_LOOP_DIV_RATIO_0 0x060 |
| 55 | #define DSIPHY_PLL_INPUT_LOOP_DIV_RAT_CTRL 0x064 |
| 56 | #define DSIPHY_PLL_PRO_DLY_RELOCK 0x06c |
| 57 | #define DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL 0x070 |
| 58 | #define DSIPHY_PLL_LOCK_DET_MODE_SEL 0x074 |
| 59 | #define DSIPHY_PLL_ANA_PROG_CTRL 0x07c |
| 60 | #define DSIPHY_HSTX_DRIV_INDATA_CTRL_CLKLANE 0x0c0 |
| 61 | #define DSIPHY_HSTX_DATAREV_CTRL_CLKLANE 0x0d4 |
| 62 | #define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE0 0x100 |
| 63 | #define DSIPHY_HS_FREQ_RAN_SEL 0x110 |
| 64 | #define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE0 0x114 |
| 65 | #define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE1 0x140 |
| 66 | #define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE1 0x154 |
| 67 | #define DSIPHY_HSTX_CLKLANE_REQSTATE_TIM_CTRL 0x180 |
| 68 | #define DSIPHY_HSTX_CLKLANE_HS0STATE_TIM_CTRL 0x188 |
| 69 | #define DSIPHY_HSTX_CLKLANE_TRALSTATE_TIM_CTRL 0x18c |
| 70 | #define DSIPHY_HSTX_CLKLANE_EXITSTATE_TIM_CTRL 0x190 |
| 71 | #define DSIPHY_HSTX_CLKLANE_CLKPOSTSTATE_TIM_CTRL 0x194 |
| 72 | #define DSIPHY_HSTX_DATALANE_REQSTATE_TIM_CTRL 0x1c0 |
| 73 | #define DSIPHY_HSTX_DATALANE_HS0STATE_TIM_CTRL 0x1c8 |
| 74 | #define DSIPHY_HSTX_DATALANE_TRAILSTATE_TIM_CTRL 0x1cc |
| 75 | #define DSIPHY_HSTX_DATALANE_EXITSTATE_TIM_CTRL 0x1d0 |
| 76 | #define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE2 0x200 |
| 77 | #define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE2 0x214 |
| 78 | #define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE3 0x254 |
| 79 | #define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE3 0x240 |
| 80 | #define DSIPHY_SLEWRATE_FSM_OVR_CTRL 0x280 |
| 81 | #define DSIPHY_SLEWRATE_DDL_LOOP_CTRL 0x28c |
| 82 | #define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0 0x290 |
| 83 | #define DSIPHY_PLL_PHA_ERR_CTRL_1 0x2e4 |
| 84 | #define DSIPHY_PLL_LOOP_DIV_RATIO_1 0x2e8 |
| 85 | #define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_1 0x328 |
| 86 | #define DSIPHY_SSC0 0x394 |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 87 | #define DSIPHY_SSC1 0x398 |
| 88 | #define DSIPHY_SSC2 0x39c |
| 89 | #define DSIPHY_SSC3 0x3a0 |
| 90 | #define DSIPHY_SSC4 0x3a4 |
| 91 | #define DSIPHY_SSC5 0x3a8 |
| 92 | #define DSIPHY_SSC6 0x3ac |
| 93 | #define DSIPHY_SSC10 0x360 |
| 94 | #define DSIPHY_SSC11 0x364 |
| 95 | #define DSIPHY_SSC12 0x368 |
| 96 | #define DSIPHY_SSC13 0x36c |
| 97 | #define DSIPHY_SSC14 0x370 |
| 98 | #define DSIPHY_SSC15 0x374 |
| 99 | #define DSIPHY_SSC7 0x3b0 |
| 100 | #define DSIPHY_SSC8 0x3b4 |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 101 | #define DSIPHY_SSC9 0x3b8 |
| 102 | #define DSIPHY_STAT0 0x3e0 |
| 103 | #define DSIPHY_CTRL0 0x3e8 |
| 104 | #define DSIPHY_SYS_CTRL 0x3f0 |
| 105 | #define DSIPHY_PLL_CTRL 0x3f8 |
| 106 | #define DSIPHY_REQ_DLY 0x3fc |
| 107 | |
| 108 | struct dsi_pll_param { |
| 109 | uint32_t vco_freq; |
| 110 | uint32_t hsfreqrange; |
| 111 | uint32_t vco_cntrl; |
| 112 | uint32_t osc_freq_target; |
| 113 | uint32_t m_div; |
| 114 | uint32_t prop_cntrl; |
| 115 | uint32_t int_cntrl; |
| 116 | uint32_t gmp_cntrl; |
| 117 | uint32_t cpbias_cntrl; |
| 118 | |
| 119 | /* mux and dividers */ |
| 120 | uint32_t gp_div_mux; |
| 121 | uint32_t post_div_mux; |
| 122 | uint32_t pixel_divhf; |
| 123 | uint32_t fsm_ovr_ctrl; |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 124 | |
| 125 | /* SSC parameters */ |
| 126 | uint32_t mpll_ssc_peak_i; |
| 127 | uint32_t mpll_stepsize_i; |
| 128 | uint32_t mpll_mint_i; |
| 129 | uint32_t mpll_frac_den; |
| 130 | uint32_t mpll_frac_quot_i; |
| 131 | uint32_t mpll_frac_rem; |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | static uint32_t __mdss_dsi_get_hsfreqrange(uint64_t target_freq) |
| 135 | { |
| 136 | uint64_t bitclk_rate_mhz = ((target_freq * 2) / 1000000); |
| 137 | |
| 138 | if (bitclk_rate_mhz >= 80 && bitclk_rate_mhz < 90) |
| 139 | return 0x00; |
| 140 | else if (bitclk_rate_mhz >= 90 && bitclk_rate_mhz < 100) |
| 141 | return 0x10; |
| 142 | else if (bitclk_rate_mhz >= 100 && bitclk_rate_mhz < 110) |
| 143 | return 0x20; |
| 144 | else if (bitclk_rate_mhz >= 110 && bitclk_rate_mhz < 120) |
| 145 | return 0x30; |
| 146 | else if (bitclk_rate_mhz >= 120 && bitclk_rate_mhz < 130) |
| 147 | return 0x01; |
| 148 | else if (bitclk_rate_mhz >= 130 && bitclk_rate_mhz < 140) |
| 149 | return 0x11; |
| 150 | else if (bitclk_rate_mhz >= 140 && bitclk_rate_mhz < 150) |
| 151 | return 0x21; |
| 152 | else if (bitclk_rate_mhz >= 150 && bitclk_rate_mhz < 160) |
| 153 | return 0x31; |
| 154 | else if (bitclk_rate_mhz >= 160 && bitclk_rate_mhz < 170) |
| 155 | return 0x02; |
| 156 | else if (bitclk_rate_mhz >= 170 && bitclk_rate_mhz < 180) |
| 157 | return 0x12; |
| 158 | else if (bitclk_rate_mhz >= 180 && bitclk_rate_mhz < 190) |
| 159 | return 0x22; |
| 160 | else if (bitclk_rate_mhz >= 190 && bitclk_rate_mhz < 205) |
| 161 | return 0x32; |
| 162 | else if (bitclk_rate_mhz >= 205 && bitclk_rate_mhz < 220) |
| 163 | return 0x03; |
| 164 | else if (bitclk_rate_mhz >= 220 && bitclk_rate_mhz < 235) |
| 165 | return 0x13; |
| 166 | else if (bitclk_rate_mhz >= 235 && bitclk_rate_mhz < 250) |
| 167 | return 0x23; |
| 168 | else if (bitclk_rate_mhz >= 250 && bitclk_rate_mhz < 275) |
| 169 | return 0x33; |
| 170 | else if (bitclk_rate_mhz >= 275 && bitclk_rate_mhz < 300) |
| 171 | return 0x04; |
| 172 | else if (bitclk_rate_mhz >= 300 && bitclk_rate_mhz < 325) |
| 173 | return 0x14; |
| 174 | else if (bitclk_rate_mhz >= 325 && bitclk_rate_mhz < 350) |
| 175 | return 0x25; |
| 176 | else if (bitclk_rate_mhz >= 350 && bitclk_rate_mhz < 400) |
| 177 | return 0x35; |
| 178 | else if (bitclk_rate_mhz >= 400 && bitclk_rate_mhz < 450) |
| 179 | return 0x05; |
| 180 | else if (bitclk_rate_mhz >= 450 && bitclk_rate_mhz < 500) |
| 181 | return 0x16; |
| 182 | else if (bitclk_rate_mhz >= 500 && bitclk_rate_mhz < 550) |
| 183 | return 0x26; |
| 184 | else if (bitclk_rate_mhz >= 550 && bitclk_rate_mhz < 600) |
| 185 | return 0x37; |
| 186 | else if (bitclk_rate_mhz >= 600 && bitclk_rate_mhz < 650) |
| 187 | return 0x07; |
| 188 | else if (bitclk_rate_mhz >= 650 && bitclk_rate_mhz < 700) |
| 189 | return 0x18; |
| 190 | else if (bitclk_rate_mhz >= 700 && bitclk_rate_mhz < 750) |
| 191 | return 0x28; |
| 192 | else if (bitclk_rate_mhz >= 750 && bitclk_rate_mhz < 800) |
| 193 | return 0x39; |
| 194 | else if (bitclk_rate_mhz >= 800 && bitclk_rate_mhz < 850) |
| 195 | return 0x09; |
| 196 | else if (bitclk_rate_mhz >= 850 && bitclk_rate_mhz < 900) |
| 197 | return 0x19; |
| 198 | else if (bitclk_rate_mhz >= 900 && bitclk_rate_mhz < 950) |
| 199 | return 0x29; |
| 200 | else if (bitclk_rate_mhz >= 950 && bitclk_rate_mhz < 1000) |
| 201 | return 0x3a; |
| 202 | else if (bitclk_rate_mhz >= 1000 && bitclk_rate_mhz < 1050) |
| 203 | return 0x0a; |
| 204 | else if (bitclk_rate_mhz >= 1050 && bitclk_rate_mhz < 1100) |
| 205 | return 0x1a; |
| 206 | else if (bitclk_rate_mhz >= 1100 && bitclk_rate_mhz < 1150) |
| 207 | return 0x2a; |
| 208 | else if (bitclk_rate_mhz >= 1150 && bitclk_rate_mhz < 1200) |
| 209 | return 0x3b; |
| 210 | else if (bitclk_rate_mhz >= 1200 && bitclk_rate_mhz < 1250) |
| 211 | return 0x0b; |
| 212 | else if (bitclk_rate_mhz >= 1250 && bitclk_rate_mhz < 1300) |
| 213 | return 0x1b; |
| 214 | else if (bitclk_rate_mhz >= 1300 && bitclk_rate_mhz < 1350) |
| 215 | return 0x2b; |
| 216 | else if (bitclk_rate_mhz >= 1350 && bitclk_rate_mhz < 1400) |
| 217 | return 0x3c; |
| 218 | else if (bitclk_rate_mhz >= 1400 && bitclk_rate_mhz < 1450) |
| 219 | return 0x0c; |
| 220 | else if (bitclk_rate_mhz >= 1450 && bitclk_rate_mhz < 1500) |
| 221 | return 0x1c; |
| 222 | else if (bitclk_rate_mhz >= 1500 && bitclk_rate_mhz < 1550) |
| 223 | return 0x2c; |
| 224 | else if (bitclk_rate_mhz >= 1550 && bitclk_rate_mhz < 1600) |
| 225 | return 0x3d; |
| 226 | else if (bitclk_rate_mhz >= 1600 && bitclk_rate_mhz < 1650) |
| 227 | return 0x0d; |
| 228 | else if (bitclk_rate_mhz >= 1650 && bitclk_rate_mhz < 1700) |
| 229 | return 0x1d; |
| 230 | else if (bitclk_rate_mhz >= 1700 && bitclk_rate_mhz < 1750) |
| 231 | return 0x2e; |
| 232 | else if (bitclk_rate_mhz >= 1750 && bitclk_rate_mhz < 1800) |
| 233 | return 0x3e; |
| 234 | else if (bitclk_rate_mhz >= 1800 && bitclk_rate_mhz < 1850) |
| 235 | return 0x0e; |
| 236 | else if (bitclk_rate_mhz >= 1850 && bitclk_rate_mhz < 1900) |
| 237 | return 0x1e; |
| 238 | else if (bitclk_rate_mhz >= 1900 && bitclk_rate_mhz < 1950) |
| 239 | return 0x2f; |
| 240 | else if (bitclk_rate_mhz >= 1950 && bitclk_rate_mhz < 2000) |
| 241 | return 0x3f; |
| 242 | else if (bitclk_rate_mhz >= 2000 && bitclk_rate_mhz < 2050) |
| 243 | return 0x0f; |
| 244 | else if (bitclk_rate_mhz >= 2050 && bitclk_rate_mhz < 2100) |
| 245 | return 0x40; |
| 246 | else if (bitclk_rate_mhz >= 2100 && bitclk_rate_mhz < 2150) |
| 247 | return 0x41; |
| 248 | else if (bitclk_rate_mhz >= 2150 && bitclk_rate_mhz < 2200) |
| 249 | return 0x42; |
| 250 | else if (bitclk_rate_mhz >= 2200 && bitclk_rate_mhz < 2250) |
| 251 | return 0x43; |
| 252 | else if (bitclk_rate_mhz >= 2250 && bitclk_rate_mhz < 2300) |
| 253 | return 0x44; |
| 254 | else if (bitclk_rate_mhz >= 2300 && bitclk_rate_mhz < 2350) |
| 255 | return 0x45; |
| 256 | else if (bitclk_rate_mhz >= 2350 && bitclk_rate_mhz < 2400) |
| 257 | return 0x46; |
| 258 | else if (bitclk_rate_mhz >= 2400 && bitclk_rate_mhz < 2450) |
| 259 | return 0x47; |
| 260 | else if (bitclk_rate_mhz >= 2450 && bitclk_rate_mhz < 2500) |
| 261 | return 0x48; |
| 262 | else |
| 263 | return 0x49; |
| 264 | } |
| 265 | |
| 266 | static void __mdss_dsi_get_pll_vco_cntrl(uint64_t target_freq, |
| 267 | uint32_t post_div_mux, uint32_t *vco_cntrl, uint32_t *cpbias_cntrl) |
| 268 | { |
| 269 | uint64_t target_freq_mhz = (target_freq / 1000000); |
| 270 | uint32_t p_div = BIT(post_div_mux); |
| 271 | |
| 272 | if (p_div == 1) { |
| 273 | *vco_cntrl = 0x00; |
| 274 | *cpbias_cntrl = 0; |
| 275 | } else if (p_div == 2) { |
| 276 | *vco_cntrl = 0x30; |
| 277 | *cpbias_cntrl = 1; |
| 278 | } else if (p_div == 4) { |
| 279 | *vco_cntrl = 0x10; |
| 280 | *cpbias_cntrl = 0; |
| 281 | } else if (p_div == 8) { |
| 282 | *vco_cntrl = 0x20; |
| 283 | *cpbias_cntrl = 0; |
| 284 | } else if (p_div == 16) { |
| 285 | *vco_cntrl = 0x30; |
| 286 | *cpbias_cntrl = 0; |
| 287 | } else { |
| 288 | *vco_cntrl = 0x00; |
| 289 | *cpbias_cntrl = 1; |
| 290 | } |
| 291 | |
| 292 | if (target_freq_mhz <= 1250 && target_freq_mhz >= 1092) |
| 293 | *vco_cntrl = *vco_cntrl | 2; |
| 294 | else if (target_freq_mhz < 1092 && target_freq_mhz >= 950) |
| 295 | *vco_cntrl = *vco_cntrl | 3; |
| 296 | else if (target_freq_mhz < 950 && target_freq_mhz >= 712) |
| 297 | *vco_cntrl = *vco_cntrl | 1; |
| 298 | else if (target_freq_mhz < 712 && target_freq_mhz >= 546) |
| 299 | *vco_cntrl = *vco_cntrl | 2; |
| 300 | else if (target_freq_mhz < 546 && target_freq_mhz >= 475) |
| 301 | *vco_cntrl = *vco_cntrl | 3; |
| 302 | else if (target_freq_mhz < 475 && target_freq_mhz >= 356) |
| 303 | *vco_cntrl = *vco_cntrl | 1; |
| 304 | else if (target_freq_mhz < 356 && target_freq_mhz >= 273) |
| 305 | *vco_cntrl = *vco_cntrl | 2; |
| 306 | else if (target_freq_mhz < 273 && target_freq_mhz >= 237) |
| 307 | *vco_cntrl = *vco_cntrl | 3; |
| 308 | else if (target_freq_mhz < 237 && target_freq_mhz >= 178) |
| 309 | *vco_cntrl = *vco_cntrl | 1; |
| 310 | else if (target_freq_mhz < 178 && target_freq_mhz >= 136) |
| 311 | *vco_cntrl = *vco_cntrl | 2; |
| 312 | else if (target_freq_mhz < 136 && target_freq_mhz >= 118) |
| 313 | *vco_cntrl = *vco_cntrl | 3; |
| 314 | else if (target_freq_mhz < 118 && target_freq_mhz >= 89) |
| 315 | *vco_cntrl = *vco_cntrl | 1; |
| 316 | else if (target_freq_mhz < 89 && target_freq_mhz >= 68) |
| 317 | *vco_cntrl = *vco_cntrl | 2; |
| 318 | else if (target_freq_mhz < 68 && target_freq_mhz >= 57) |
| 319 | *vco_cntrl = *vco_cntrl | 3; |
| 320 | else if (target_freq_mhz < 57 && target_freq_mhz >= 44) |
| 321 | *vco_cntrl = *vco_cntrl | 1; |
| 322 | else |
| 323 | *vco_cntrl = *vco_cntrl | 2; |
| 324 | } |
| 325 | |
| 326 | static uint32_t __mdss_dsi_get_osc_freq_target(uint64_t target_freq) |
| 327 | { |
| 328 | uint64_t target_freq_mhz = (target_freq / 1000000); |
| 329 | |
| 330 | if (target_freq_mhz <= 1000) |
| 331 | return 1315; |
| 332 | else if (target_freq_mhz > 1000 && target_freq_mhz <= 1500) |
| 333 | return 1839; |
| 334 | else |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | static uint64_t __mdss_dsi_pll_get_m_div(uint64_t vco_rate) |
| 339 | { |
| 340 | return ((vco_rate * 4) / VCO_REF_CLOCK_RATE); |
| 341 | } |
| 342 | |
| 343 | static uint32_t __mdss_dsi_get_fsm_ovr_ctrl(uint64_t target_freq) |
| 344 | { |
| 345 | uint64_t bitclk_rate_mhz = ((target_freq * 2) / 1000000); |
| 346 | |
| 347 | if (bitclk_rate_mhz > 1500 && bitclk_rate_mhz <= 2500) |
| 348 | return 0; |
| 349 | else |
| 350 | return BIT(6); |
| 351 | } |
| 352 | |
| 353 | static void mdss_dsi_pll_12nm_calc_reg(struct dsi_pll_param *param) |
| 354 | { |
| 355 | uint64_t target_freq = 0; |
| 356 | |
| 357 | target_freq = (param->vco_freq / BIT(param->post_div_mux)); |
| 358 | |
| 359 | param->hsfreqrange = __mdss_dsi_get_hsfreqrange(target_freq); |
| 360 | __mdss_dsi_get_pll_vco_cntrl(target_freq, param->post_div_mux, |
| 361 | ¶m->vco_cntrl, ¶m->cpbias_cntrl); |
| 362 | param->osc_freq_target = __mdss_dsi_get_osc_freq_target(target_freq); |
| 363 | param->m_div = (uint32_t) __mdss_dsi_pll_get_m_div(param->vco_freq); |
| 364 | param->fsm_ovr_ctrl = __mdss_dsi_get_fsm_ovr_ctrl(target_freq); |
| 365 | param->prop_cntrl = 0x05; |
| 366 | param->int_cntrl = 0x00; |
| 367 | param->gmp_cntrl = 0x1; |
| 368 | } |
| 369 | |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 370 | static uint32_t __mdss_dsi_get_multi_intX100(uint64_t vco_rate, uint32_t *rem) |
| 371 | { |
| 372 | uint32_t reminder = 0; |
| 373 | uint64_t temp = 0; |
| 374 | const uint32_t quarterX100 = 25; |
| 375 | |
| 376 | temp = vco_rate / VCO_REF_CLOCK_RATE; |
| 377 | temp *= 100; |
| 378 | reminder = vco_rate % VCO_REF_CLOCK_RATE; |
| 379 | |
| 380 | /* |
| 381 | * Multiplication integer needs to be floored in steps of 0.25 |
| 382 | * Hence multi_intX100 needs to be rounded off in steps of 25 |
| 383 | */ |
| 384 | if (reminder < (VCO_REF_CLOCK_RATE / 4)) { |
| 385 | *rem = reminder; |
| 386 | return temp; |
| 387 | } else if (reminder >= (VCO_REF_CLOCK_RATE / 4) && |
| 388 | reminder < (VCO_REF_CLOCK_RATE / 2)) { |
| 389 | *rem = (reminder - (VCO_REF_CLOCK_RATE / 4)); |
| 390 | return (temp + quarterX100); |
| 391 | } else if (reminder >= (VCO_REF_CLOCK_RATE / 2) && |
| 392 | reminder < ((3 * VCO_REF_CLOCK_RATE) / 4)) { |
| 393 | *rem = (reminder - (VCO_REF_CLOCK_RATE / 2)); |
| 394 | return (temp + (quarterX100 * 2)); |
| 395 | } |
| 396 | |
| 397 | *rem = (reminder - ((3 * VCO_REF_CLOCK_RATE) / 4)); |
| 398 | return (temp + (quarterX100 * 3)); |
| 399 | } |
| 400 | |
| 401 | static uint32_t __calc_gcd(uint32_t num1, uint32_t num2) |
| 402 | { |
| 403 | if (num2 != 0) |
| 404 | return __calc_gcd(num2, (num1 % num2)); |
| 405 | else |
| 406 | return num1; |
| 407 | } |
| 408 | |
| 409 | static void mdss_dsi_pll_12nm_calc_ssc(struct mdss_dsi_pll_config *pd, |
| 410 | struct dsi_pll_param *param) |
| 411 | { |
| 412 | uint64_t multi_intX100 = 0, temp = 0; |
| 413 | uint32_t temp_rem1 = 0, temp_rem2 = 0; |
| 414 | const uint64_t power_2_17 = 131072, power_2_10 = 1024; |
| 415 | |
| 416 | multi_intX100 = __mdss_dsi_get_multi_intX100(param->vco_freq, |
| 417 | &temp_rem1); |
| 418 | |
| 419 | /* Calculation for mpll_ssc_peak_i */ |
| 420 | temp = (multi_intX100 * pd->ssc_ppm * power_2_17); |
| 421 | temp = (temp / 100); /* 100 div for multi_intX100 */ |
| 422 | param->mpll_ssc_peak_i = |
| 423 | (uint32_t) (temp / 1000000); /*10^6 for SSC PPM */ |
| 424 | |
| 425 | /* Calculation for mpll_stepsize_i */ |
| 426 | param->mpll_stepsize_i = (uint32_t) ((param->mpll_ssc_peak_i * |
| 427 | pd->ssc_freq * power_2_10) / VCO_REF_CLOCK_RATE); |
| 428 | |
| 429 | /* Calculation for mpll_mint_i */ |
| 430 | param->mpll_mint_i = (uint32_t) (((multi_intX100 * 4) / 100) - 32); |
| 431 | |
| 432 | /* Calculation for mpll_frac_den */ |
| 433 | param->mpll_frac_den = (uint32_t) (VCO_REF_CLOCK_RATE / |
| 434 | __calc_gcd(param->vco_freq, VCO_REF_CLOCK_RATE)); |
| 435 | |
| 436 | /* Calculation for mpll_frac_quot_i */ |
| 437 | temp = (temp_rem1 * power_2_17); |
| 438 | param->mpll_frac_quot_i = (uint32_t) (temp / VCO_REF_CLOCK_RATE); |
| 439 | temp_rem2 = temp % VCO_REF_CLOCK_RATE; |
| 440 | |
| 441 | /* Calculation for mpll_frac_rem */ |
| 442 | param->mpll_frac_rem = (uint32_t) (((uint64_t) temp_rem2 * |
| 443 | param->mpll_frac_den) / VCO_REF_CLOCK_RATE); |
| 444 | |
| 445 | dprintf(SPEW, "mpll_ssc_peak_i=%d mpll_stepsize_i=%d mpll_mint_i=%d\n", |
| 446 | param->mpll_ssc_peak_i, param->mpll_stepsize_i, |
| 447 | param->mpll_mint_i); |
| 448 | dprintf(SPEW, "mpll_frac_den=%d mpll_frac_quot_i=%d mpll_frac_rem=%d\n", |
| 449 | param->mpll_frac_den, param->mpll_frac_quot_i, |
| 450 | param->mpll_frac_rem); |
| 451 | } |
| 452 | |
| 453 | static void pll_db_commit_12nm_ssc(struct dsi_pll_param *param, |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 454 | uint32_t phy_base) |
| 455 | { |
| 456 | uint32_t data = 0; |
| 457 | |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 458 | writel_relaxed(0x27, phy_base + DSIPHY_SSC0); |
| 459 | |
| 460 | data = (param->mpll_mint_i & 0xff); |
| 461 | writel_relaxed(data, phy_base + DSIPHY_SSC7); |
| 462 | |
| 463 | data = ((param->mpll_mint_i & 0xff00) >> 8); |
| 464 | writel_relaxed(data, phy_base + DSIPHY_SSC8); |
| 465 | |
| 466 | data = (param->mpll_ssc_peak_i & 0xff); |
| 467 | writel_relaxed(data, phy_base + DSIPHY_SSC1); |
| 468 | |
| 469 | data = ((param->mpll_ssc_peak_i & 0xff00) >> 8); |
| 470 | writel_relaxed(data, phy_base + DSIPHY_SSC2); |
| 471 | |
| 472 | data = ((param->mpll_ssc_peak_i & 0xf0000) >> 16); |
| 473 | writel_relaxed(data, phy_base + DSIPHY_SSC3); |
| 474 | |
| 475 | data = (param->mpll_stepsize_i & 0xff); |
| 476 | writel_relaxed(data, phy_base + DSIPHY_SSC4); |
| 477 | |
| 478 | data = ((param->mpll_stepsize_i & 0xff00) >> 8); |
| 479 | writel_relaxed(data, phy_base + DSIPHY_SSC5); |
| 480 | |
| 481 | data = ((param->mpll_stepsize_i & 0x1f0000) >> 16); |
| 482 | writel_relaxed(data, phy_base + DSIPHY_SSC6); |
| 483 | |
| 484 | data = (param->mpll_frac_quot_i & 0xff); |
| 485 | writel_relaxed(data, phy_base + DSIPHY_SSC10); |
| 486 | |
| 487 | data = ((param->mpll_frac_quot_i & 0xff00) >> 8); |
| 488 | writel_relaxed(data, phy_base + DSIPHY_SSC11); |
| 489 | |
| 490 | data = (param->mpll_frac_rem & 0xff); |
| 491 | writel_relaxed(data, phy_base + DSIPHY_SSC12); |
| 492 | |
| 493 | data = ((param->mpll_frac_rem & 0xff00) >> 8); |
| 494 | writel_relaxed(data, phy_base + DSIPHY_SSC13); |
| 495 | |
| 496 | data = (param->mpll_frac_den & 0xff); |
| 497 | writel_relaxed(data, phy_base + DSIPHY_SSC14); |
| 498 | |
| 499 | data = ((param->mpll_frac_den & 0xff00) >> 8); |
| 500 | writel_relaxed(data, phy_base + DSIPHY_SSC15); |
| 501 | } |
| 502 | |
| 503 | static void pll_db_commit_12nm(struct dsi_pll_param *param, |
| 504 | uint32_t phy_base, bool ssc_en) |
| 505 | { |
| 506 | uint32_t data = 0; |
| 507 | |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 508 | writel_relaxed(0x01, phy_base + DSIPHY_CTRL0); |
| 509 | writel_relaxed(0x05, phy_base + DSIPHY_PLL_CTRL); |
| 510 | writel_relaxed(0x01, phy_base + DSIPHY_SLEWRATE_DDL_LOOP_CTRL); |
| 511 | |
| 512 | data = ((param->hsfreqrange & 0x7f) | BIT(7)); |
| 513 | writel_relaxed(data, phy_base + DSIPHY_HS_FREQ_RAN_SEL); |
| 514 | |
| 515 | data = ((param->vco_cntrl & 0x3f) | BIT(6)); |
| 516 | writel_relaxed(data, phy_base + DSIPHY_PLL_VCO_CTRL); |
| 517 | |
| 518 | data = (param->osc_freq_target & 0x7f); |
| 519 | writel_relaxed(data, phy_base + DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0); |
| 520 | |
| 521 | data = ((param->osc_freq_target & 0xf80) >> 7); |
| 522 | writel_relaxed(data, phy_base + DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_1); |
| 523 | writel_relaxed(0x30, phy_base + DSIPHY_PLL_INPUT_LOOP_DIV_RAT_CTRL); |
| 524 | |
| 525 | data = (param->m_div & 0x3f); |
| 526 | writel_relaxed(data, phy_base + DSIPHY_PLL_LOOP_DIV_RATIO_0); |
| 527 | |
| 528 | data = ((param->m_div & 0xfc0) >> 6); |
| 529 | writel_relaxed(data, phy_base + DSIPHY_PLL_LOOP_DIV_RATIO_1); |
| 530 | writel_relaxed(0x60, phy_base + DSIPHY_PLL_INPUT_DIV_PLL_OVR); |
| 531 | |
| 532 | data = (param->prop_cntrl & 0x3f); |
| 533 | writel_relaxed(data, phy_base + DSIPHY_PLL_PROP_CHRG_PUMP_CTRL); |
| 534 | |
| 535 | data = (param->int_cntrl & 0x3f); |
| 536 | writel_relaxed(data, phy_base + DSIPHY_PLL_INTEG_CHRG_PUMP_CTRL); |
| 537 | |
| 538 | data = ((param->gmp_cntrl & 0x3) << 4); |
| 539 | writel_relaxed(data, phy_base + DSIPHY_PLL_GMP_CTRL_DIG_TST); |
| 540 | |
| 541 | data = ((param->cpbias_cntrl & 0x1) << 6) | BIT(4); |
| 542 | writel_relaxed(data, phy_base + DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL); |
| 543 | |
| 544 | data = ((param->gp_div_mux & 0x7) << 5) | 0x5; |
| 545 | writel_relaxed(data, phy_base + DSIPHY_PLL_CTRL); |
| 546 | |
| 547 | data = (param->pixel_divhf & 0x7f); |
| 548 | writel_relaxed(data, phy_base + DSIPHY_SSC9); |
| 549 | |
| 550 | writel_relaxed(0x03, phy_base + DSIPHY_PLL_ANA_PROG_CTRL); |
| 551 | writel_relaxed(0x50, phy_base + DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL); |
| 552 | writel_relaxed(param->fsm_ovr_ctrl, |
| 553 | phy_base + DSIPHY_SLEWRATE_FSM_OVR_CTRL); |
| 554 | writel_relaxed(0x01, phy_base + DSIPHY_PLL_PHA_ERR_CTRL_0); |
| 555 | writel_relaxed(0x00, phy_base + DSIPHY_PLL_PHA_ERR_CTRL_1); |
| 556 | writel_relaxed(0xff, phy_base + DSIPHY_PLL_LOCK_FILTER); |
| 557 | writel_relaxed(0x03, phy_base + DSIPHY_PLL_UNLOCK_FILTER); |
| 558 | writel_relaxed(0x0c, phy_base + DSIPHY_PLL_PRO_DLY_RELOCK); |
| 559 | writel_relaxed(0x02, phy_base + DSIPHY_PLL_LOCK_DET_MODE_SEL); |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 560 | |
| 561 | if (ssc_en) |
| 562 | pll_db_commit_12nm_ssc(param, phy_base); |
| 563 | |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 564 | dmb(); /* make sure register committed */ |
| 565 | } |
| 566 | |
| 567 | static void mdss_dsi_phy_12nm_init(struct msm_panel_info *pinfo, |
| 568 | uint32_t phy_base) |
| 569 | { |
| 570 | uint32_t *timing = pinfo->mipi.mdss_dsi_phy_db->timing; |
| 571 | |
| 572 | /* Shutdown PHY initially */ |
| 573 | writel_relaxed(0x09, phy_base + DSIPHY_SYS_CTRL); |
| 574 | /* CTRL0: CFG_CLK_EN */ |
| 575 | writel_relaxed(0x1, phy_base + DSIPHY_CTRL0); |
| 576 | |
| 577 | /* DSI PHY clock lane timings */ |
| 578 | writel_relaxed((timing[0] | BIT(7)), |
| 579 | phy_base + DSIPHY_HSTX_CLKLANE_HS0STATE_TIM_CTRL); |
| 580 | writel_relaxed((timing[1] | BIT(6)), |
| 581 | phy_base + DSIPHY_HSTX_CLKLANE_TRALSTATE_TIM_CTRL); |
| 582 | writel_relaxed((timing[2] | BIT(6)), |
| 583 | phy_base + DSIPHY_HSTX_CLKLANE_CLKPOSTSTATE_TIM_CTRL); |
| 584 | writel_relaxed(timing[3], |
| 585 | phy_base + DSIPHY_HSTX_CLKLANE_REQSTATE_TIM_CTRL); |
| 586 | writel_relaxed((timing[7] | BIT(6) | BIT(7)), |
| 587 | phy_base + DSIPHY_HSTX_CLKLANE_EXITSTATE_TIM_CTRL); |
| 588 | |
| 589 | /* DSI PHY data lane timings */ |
| 590 | writel_relaxed((timing[4] | BIT(7)), |
| 591 | phy_base + DSIPHY_HSTX_DATALANE_HS0STATE_TIM_CTRL); |
| 592 | writel_relaxed((timing[5] | BIT(6)), |
| 593 | phy_base + DSIPHY_HSTX_DATALANE_TRAILSTATE_TIM_CTRL); |
| 594 | writel_relaxed(timing[6], |
| 595 | phy_base + DSIPHY_HSTX_DATALANE_REQSTATE_TIM_CTRL); |
| 596 | writel_relaxed((timing[7] | BIT(6) | BIT(7)), |
| 597 | phy_base + DSIPHY_HSTX_DATALANE_EXITSTATE_TIM_CTRL); |
| 598 | |
| 599 | writel_relaxed(0x03, phy_base + DSIPHY_T_TA_GO_TIM_COUNT); |
| 600 | writel_relaxed(0x01, phy_base + DSIPHY_T_TA_SURE_TIM_COUNT); |
| 601 | writel_relaxed(0x85, phy_base + DSIPHY_REQ_DLY); |
| 602 | |
| 603 | /* DSI lane control registers */ |
| 604 | writel_relaxed(0x00, phy_base + |
| 605 | DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE0); |
| 606 | writel_relaxed(0x00, phy_base + |
| 607 | DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE1); |
| 608 | writel_relaxed(0x00, phy_base + |
| 609 | DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE2); |
| 610 | writel_relaxed(0x00, phy_base + |
| 611 | DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE3); |
| 612 | writel_relaxed(0x00, phy_base + |
| 613 | DSIPHY_HSTX_DATAREV_CTRL_CLKLANE); |
| 614 | dmb(); /* make sure DSI PHY registers are programmed */ |
| 615 | } |
| 616 | |
| 617 | void mdss_dsi_auto_pll_12nm_config(struct msm_panel_info *pinfo) |
| 618 | { |
| 619 | struct mdss_dsi_pll_config *pd = pinfo->mipi.dsi_pll_config; |
| 620 | uint32_t phy_base = pinfo->mipi.phy_base; |
| 621 | uint32_t sphy_base = pinfo->mipi.sphy_base; |
| 622 | struct dsi_pll_param param = {0}; |
| 623 | |
| 624 | param.vco_freq = pd->vco_clock; |
| 625 | param.post_div_mux = pd->p_div_mux; |
| 626 | param.gp_div_mux = pd->gp_div_mux; |
| 627 | param.pixel_divhf = pd->divhf; |
| 628 | |
| 629 | mdss_dsi_phy_12nm_init(pinfo, phy_base); |
| 630 | if (pinfo->mipi.dual_dsi) |
| 631 | mdss_dsi_phy_12nm_init(pinfo, sphy_base); |
| 632 | |
| 633 | mdss_dsi_pll_12nm_calc_reg(¶m); |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 634 | if (pd->ssc_en) |
| 635 | mdss_dsi_pll_12nm_calc_ssc(pd, ¶m); |
| 636 | pll_db_commit_12nm(¶m, phy_base, pd->ssc_en); |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static uint32_t is_pll_locked_12nm(uint32_t phy_base) |
| 640 | { |
| 641 | uint32_t cnt, status; |
| 642 | |
| 643 | /* check pll lock */ |
| 644 | for (cnt = 0; cnt < 50; cnt++) { |
| 645 | status = readl_relaxed(phy_base + DSIPHY_STAT0); |
| 646 | dprintf(SPEW, "%s: phy_base=%x cnt=%d status=%x\n", |
| 647 | __func__, phy_base, cnt, status); |
| 648 | status &= BIT(1); |
| 649 | if (status) |
| 650 | break; |
| 651 | udelay(500); |
| 652 | } |
| 653 | |
| 654 | return status; |
| 655 | } |
| 656 | |
| 657 | static void mdss_dsi_12nm_phy_hstx_drv_enable(uint32_t phy_base) |
| 658 | { |
| 659 | uint32_t data = BIT(2) | BIT(3); |
| 660 | |
| 661 | writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_CLKLANE); |
| 662 | writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE0); |
| 663 | writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE1); |
| 664 | writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE2); |
| 665 | writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE3); |
| 666 | dmb(); /* make sure DSI PHY registers are programmed */ |
| 667 | } |
| 668 | |
| 669 | bool mdss_dsi_auto_pll_12nm_enable(struct msm_panel_info *pinfo) |
| 670 | { |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 671 | struct mdss_dsi_pll_config *pd = pinfo->mipi.dsi_pll_config; |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 672 | uint32_t phy_base = pinfo->mipi.phy_base; |
| 673 | uint32_t sphy_base = pinfo->mipi.sphy_base; |
| 674 | |
| 675 | writel_relaxed(0x49, phy_base + DSIPHY_SYS_CTRL); |
| 676 | dmb(); /* make sure register committed */ |
| 677 | udelay(5); /* h/w recommended delay */ |
| 678 | writel_relaxed(0xc9, phy_base + DSIPHY_SYS_CTRL); |
| 679 | dmb(); /* make sure register committed */ |
| 680 | udelay(50); /* h/w recommended delay */ |
| 681 | |
| 682 | if (!is_pll_locked_12nm(phy_base)) { |
| 683 | dprintf(SPEW, "DSI PLL lock failed!\n"); |
| 684 | return false; |
| 685 | } |
| 686 | |
| 687 | dprintf(SPEW, "DSI PLL Locked!\n"); |
| 688 | |
| 689 | /* Enable DSI PLL output to DSI controller */ |
Padmanabhan Komanduru | e54f761 | 2018-05-03 09:29:50 +0530 | [diff] [blame] | 690 | if (pd->ssc_en) |
| 691 | writel_relaxed(0x67, phy_base + DSIPHY_SSC0); |
| 692 | else |
| 693 | writel_relaxed(0x40, phy_base + DSIPHY_SSC0); |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 694 | |
| 695 | mdss_dsi_12nm_phy_hstx_drv_enable(phy_base); |
| 696 | if (pinfo->mipi.dual_dsi) |
| 697 | mdss_dsi_12nm_phy_hstx_drv_enable(sphy_base); |
| 698 | return true; |
| 699 | } |