Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 32 | #include <err.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 33 | #include <msm_panel.h> |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 34 | #include <mipi_dsi.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
| 39 | #include <platform/gpio.h> |
| 40 | #include <platform/iomap.h> |
| 41 | #include <target/display.h> |
| 42 | |
Casey Piper | cbdfbd2 | 2013-08-14 17:22:16 -0700 | [diff] [blame] | 43 | #include "include/panel.h" |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 44 | #include "include/display_resource.h" |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 45 | |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 46 | #define HFPLL_LDO_ID 8 |
| 47 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 48 | static struct pm8x41_wled_data wled_ctrl = { |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 49 | .mod_scheme = 0x00, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 50 | .led1_brightness = (0x0F << 8) | 0xEF, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 51 | .max_duty_cycle = 0x01, |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 52 | .ovp = 0x0, |
Zhenhua Huang | d5355cb | 2013-09-04 16:03:01 +0800 | [diff] [blame] | 53 | .full_current_scale = 0x19, |
| 54 | .fdbck = 0x1 |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 55 | }; |
| 56 | |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame^] | 57 | static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base) |
| 58 | { |
| 59 | uint32_t i = 0; |
| 60 | uint32_t pll_locked = 0; |
| 61 | |
| 62 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 63 | |
| 64 | /* |
| 65 | * Add hardware recommended delays between register writes for |
| 66 | * the updates to take effect. These delays are necessary for the |
| 67 | * PLL to successfully lock |
| 68 | */ |
| 69 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 70 | udelay(200); |
| 71 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 72 | udelay(200); |
| 73 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 74 | udelay(1000); |
| 75 | |
| 76 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 77 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 78 | for (i = 0; (i < 4) && !pll_locked; i++) { |
| 79 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 80 | if (i != 0) |
| 81 | writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/ |
| 82 | udelay(1); |
| 83 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 84 | udelay(1000); |
| 85 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 86 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 87 | } |
| 88 | |
| 89 | return pll_locked; |
| 90 | } |
| 91 | |
| 92 | static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base) |
| 93 | { |
| 94 | uint32_t pll_locked = 0; |
| 95 | |
| 96 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 97 | |
| 98 | /* |
| 99 | * Add hardware recommended delays between register writes for |
| 100 | * the updates to take effect. These delays are necessary for the |
| 101 | * PLL to successfully lock |
| 102 | */ |
| 103 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 104 | udelay(200); |
| 105 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 106 | udelay(200); |
| 107 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 108 | udelay(200); |
| 109 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 110 | udelay(200); |
| 111 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 112 | udelay(200); |
| 113 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 114 | udelay(1000); |
| 115 | |
| 116 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 117 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 118 | |
| 119 | return pll_locked; |
| 120 | } |
| 121 | |
| 122 | static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base) |
| 123 | { |
| 124 | uint32_t pll_locked = 0; |
| 125 | |
| 126 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 127 | |
| 128 | /* |
| 129 | * Add hardware recommended delays between register writes for |
| 130 | * the updates to take effect. These delays are necessary for the |
| 131 | * PLL to successfully lock |
| 132 | */ |
| 133 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 134 | udelay(200); |
| 135 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 136 | udelay(200); |
| 137 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 138 | udelay(200); |
| 139 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 140 | udelay(200); |
| 141 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 142 | udelay(1000); |
| 143 | |
| 144 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 145 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 146 | |
| 147 | return pll_locked; |
| 148 | } |
| 149 | |
| 150 | static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base) |
| 151 | { |
| 152 | uint32_t pll_locked = 0; |
| 153 | |
| 154 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 155 | |
| 156 | /* |
| 157 | * Add hardware recommended delays between register writes for |
| 158 | * the updates to take effect. These delays are necessary for the |
| 159 | * PLL to successfully lock |
| 160 | */ |
| 161 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 162 | udelay(200); |
| 163 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 164 | udelay(200); |
| 165 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 166 | udelay(1000); |
| 167 | |
| 168 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 169 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 170 | |
| 171 | return pll_locked; |
| 172 | } |
| 173 | |
| 174 | static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base) |
| 175 | { |
| 176 | uint32_t pll_locked = 0; |
| 177 | |
| 178 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 179 | |
| 180 | /* |
| 181 | * Add hardware recommended delays between register writes for |
| 182 | * the updates to take effect. These delays are necessary for the |
| 183 | * PLL to successfully lock |
| 184 | */ |
| 185 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 186 | udelay(200); |
| 187 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 188 | udelay(200); |
| 189 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 190 | udelay(1); |
| 191 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 192 | udelay(1000); |
| 193 | |
| 194 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 195 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 196 | |
| 197 | return pll_locked; |
| 198 | } |
| 199 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 200 | int target_backlight_ctrl(uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 201 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 202 | dprintf(SPEW, "target_backlight_ctrl\n"); |
| 203 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 204 | pm8x41_wled_config(&wled_ctrl); |
| 205 | pm8x41_wled_sink_control(1); |
| 206 | pm8x41_wled_iled_sync_control(1); |
| 207 | pm8x41_wled_enable(1); |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame^] | 212 | static void dsi_pll_enable_seq(uint32_t ctl_base) |
| 213 | { |
| 214 | if (dsi_pll_enable_seq_m(ctl_base)) { |
| 215 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 216 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 217 | } else if (dsi_pll_enable_seq_f1(ctl_base)) { |
| 218 | } else if (dsi_pll_enable_seq_c(ctl_base)) { |
| 219 | } else if (dsi_pll_enable_seq_e(ctl_base)) { |
| 220 | } else { |
| 221 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 222 | } |
| 223 | } |
| 224 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 225 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 226 | { |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 227 | struct mdss_dsi_pll_config *pll_data; |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 228 | dprintf(SPEW, "target_panel_clock\n"); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 229 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 230 | pll_data = pinfo->mipi.dsi_pll_config; |
| 231 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 232 | if (enable) { |
| 233 | mdp_gdsc_ctrl(enable); |
| 234 | mdp_clock_init(); |
Casey Piper | 992edde | 2013-08-26 11:14:02 -0700 | [diff] [blame^] | 235 | mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data); |
| 236 | dsi_pll_enable_seq(MIPI_DSI0_BASE); |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 237 | mmss_clock_auto_pll_init(pll_data->pclk_m, |
| 238 | pll_data->pclk_n, |
| 239 | pll_data->pclk_d); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 240 | } else if(!target_cont_splash_screen()) { |
| 241 | /* Add here for non-continuous splash */ |
| 242 | /* FIXME:Need to disable the clocks. |
| 243 | * For now leave the clocks enabled until the kernel |
| 244 | * hang issue gets resolved |
| 245 | */ |
| 246 | } |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 251 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 252 | struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 253 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 254 | int ret = NO_ERROR; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 255 | if (enable) { |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 256 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 257 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 258 | reset_gpio.pin_strength, reset_gpio.pin_state); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 259 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 260 | gpio_set_dir(reset_gpio.pin_id, 2); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 261 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 262 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 263 | mdelay(resetseq->sleep[0]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 264 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 265 | mdelay(resetseq->sleep[1]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 266 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 267 | mdelay(resetseq->sleep[2]); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 268 | } else if(!target_cont_splash_screen()) { |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 269 | gpio_set_value(reset_gpio.pin_id, 0); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 270 | } |
| 271 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 272 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 273 | } |
| 274 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 275 | int target_ldo_ctrl(uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 276 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 277 | uint32_t ret = NO_ERROR; |
| 278 | uint32_t ldocounter = 0; |
| 279 | uint32_t pm8x41_ldo_base = 0x13F00; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 280 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 281 | while (ldocounter < TOTAL_LDO_DEFINED) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 282 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 283 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 284 | ldo_entry_array[ldocounter].ldo_type); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 285 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 286 | dprintf(SPEW, "Setting %s\n", |
| 287 | ldo_entry_array[ldocounter].ldo_id); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 288 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 289 | /* Set voltage during power on */ |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 290 | if (enable) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 291 | pm8x41_ldo_set_voltage(&ldo_entry, |
| 292 | ldo_entry_array[ldocounter].ldo_voltage); |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 293 | |
| 294 | pm8x41_ldo_control(&ldo_entry, enable); |
| 295 | |
| 296 | } else if(!target_cont_splash_screen() && |
| 297 | ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) { |
| 298 | pm8x41_ldo_control(&ldo_entry, enable); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 299 | } |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 300 | ldocounter++; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 301 | } |
| 302 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 303 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | void display_init(void) |
| 307 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 308 | gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | void display_shutdown(void) |
| 312 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 313 | gcdb_display_shutdown(); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 314 | } |