Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 5 |
| 43 | #define cxo_mm_source_val 0 |
| 44 | #define mmpll0_mm_source_val 1 |
| 45 | #define mmpll1_mm_source_val 2 |
| 46 | #define mmpll3_mm_source_val 3 |
| 47 | #define gpll0_mm_source_val 5 |
| 48 | |
| 49 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 50 | |
| 51 | |
| 52 | /* Clock Operations */ |
| 53 | static struct clk_ops clk_ops_rst = |
| 54 | { |
| 55 | .reset = clock_lib2_reset_clk_reset, |
| 56 | }; |
| 57 | |
| 58 | static struct clk_ops clk_ops_branch = |
| 59 | { |
| 60 | .enable = clock_lib2_branch_clk_enable, |
| 61 | .disable = clock_lib2_branch_clk_disable, |
| 62 | .set_rate = clock_lib2_branch_set_rate, |
| 63 | .reset = clock_lib2_branch_clk_reset, |
| 64 | }; |
| 65 | |
| 66 | static struct clk_ops clk_ops_rcg_mnd = |
| 67 | { |
| 68 | .enable = clock_lib2_rcg_enable, |
| 69 | .set_rate = clock_lib2_rcg_set_rate, |
| 70 | }; |
| 71 | |
| 72 | static struct clk_ops clk_ops_rcg = |
| 73 | { |
| 74 | .enable = clock_lib2_rcg_enable, |
| 75 | .set_rate = clock_lib2_rcg_set_rate, |
| 76 | }; |
| 77 | |
| 78 | static struct clk_ops clk_ops_cxo = |
| 79 | { |
| 80 | .enable = cxo_clk_enable, |
| 81 | .disable = cxo_clk_disable, |
| 82 | }; |
| 83 | |
| 84 | static struct clk_ops clk_ops_pll_vote = |
| 85 | { |
| 86 | .enable = pll_vote_clk_enable, |
| 87 | .disable = pll_vote_clk_disable, |
| 88 | .auto_off = pll_vote_clk_disable, |
| 89 | .is_enabled = pll_vote_clk_is_enabled, |
| 90 | }; |
| 91 | |
| 92 | static struct clk_ops clk_ops_vote = |
| 93 | { |
| 94 | .enable = clock_lib2_vote_clk_enable, |
| 95 | .disable = clock_lib2_vote_clk_disable, |
| 96 | }; |
| 97 | |
| 98 | /* Clock Sources */ |
| 99 | static struct fixed_clk cxo_clk_src = |
| 100 | { |
| 101 | .c = { |
| 102 | .rate = 19200000, |
| 103 | .dbg_name = "cxo_clk_src", |
| 104 | .ops = &clk_ops_cxo, |
| 105 | }, |
| 106 | }; |
| 107 | |
| 108 | static struct pll_vote_clk gpll0_clk_src = |
| 109 | { |
| 110 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 111 | .en_mask = BIT(0), |
| 112 | .status_reg = (void *) GPLL0_MODE, |
| 113 | .status_mask = BIT(30), |
| 114 | .parent = &cxo_clk_src.c, |
| 115 | |
| 116 | .c = { |
| 117 | .rate = 600000000, |
| 118 | .dbg_name = "gpll0_clk_src", |
| 119 | .ops = &clk_ops_pll_vote, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static struct pll_vote_clk gpll4_clk_src = |
| 124 | { |
| 125 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 126 | .en_mask = BIT(4), |
| 127 | .status_reg = (void *) GPLL4_MODE, |
| 128 | .status_mask = BIT(30), |
| 129 | .parent = &cxo_clk_src.c, |
| 130 | |
| 131 | .c = { |
| 132 | .rate = 1600000000, |
| 133 | .dbg_name = "gpll4_clk_src", |
| 134 | .ops = &clk_ops_pll_vote, |
| 135 | }, |
| 136 | }; |
| 137 | |
| 138 | /* UART Clocks */ |
| 139 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 140 | { |
| 141 | F( 3686400, gpll0, 1, 96, 15625), |
| 142 | F( 7372800, gpll0, 1, 192, 15625), |
| 143 | F(14745600, gpll0, 1, 384, 15625), |
| 144 | F(16000000, gpll0, 5, 2, 15), |
| 145 | F(19200000, cxo, 1, 0, 0), |
| 146 | F(24000000, gpll0, 5, 1, 5), |
| 147 | F(32000000, gpll0, 1, 4, 75), |
| 148 | F(40000000, gpll0, 15, 0, 0), |
| 149 | F(46400000, gpll0, 1, 29, 375), |
| 150 | F(48000000, gpll0, 12.5, 0, 0), |
| 151 | F(51200000, gpll0, 1, 32, 375), |
| 152 | F(56000000, gpll0, 1, 7, 75), |
| 153 | F(58982400, gpll0, 1, 1536, 15625), |
| 154 | F(60000000, gpll0, 10, 0, 0), |
| 155 | F(63160000, gpll0, 9.5, 0, 0), |
| 156 | F_END |
| 157 | }; |
| 158 | |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 159 | static struct rcg_clk blsp2_uart2_apps_clk_src = |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 160 | { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 161 | .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR, |
| 162 | .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR, |
| 163 | .m_reg = (uint32_t *) BLSP2_UART2_APPS_M, |
| 164 | .n_reg = (uint32_t *) BLSP2_UART2_APPS_N, |
| 165 | .d_reg = (uint32_t *) BLSP2_UART2_APPS_D, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 166 | |
| 167 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 168 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 169 | .current_freq = &rcg_dummy_freq, |
| 170 | |
| 171 | .c = { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 172 | .dbg_name = "blsp2_uart2_apps_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 173 | .ops = &clk_ops_rcg_mnd, |
| 174 | }, |
| 175 | }; |
| 176 | |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 177 | static struct branch_clk gcc_blsp2_uart2_apps_clk = |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 178 | { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 179 | .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR, |
| 180 | .parent = &blsp2_uart2_apps_clk_src.c, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 181 | |
| 182 | .c = { |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 183 | .dbg_name = "gcc_blsp2_uart2_apps_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 184 | .ops = &clk_ops_branch, |
| 185 | }, |
| 186 | }; |
| 187 | |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 188 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 189 | .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR, |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 190 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 191 | .en_mask = BIT(15), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 192 | |
| 193 | .c = { |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 194 | .dbg_name = "gcc_blsp2_ahb_clk", |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 195 | .ops = &clk_ops_vote, |
| 196 | }, |
| 197 | }; |
| 198 | |
| 199 | /* SDCC Clocks */ |
| 200 | static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = |
| 201 | { |
| 202 | F( 144000, cxo, 16, 3, 25), |
| 203 | F( 400000, cxo, 12, 1, 4), |
| 204 | F( 20000000, gpll0, 15, 1, 2), |
| 205 | F( 25000000, gpll0, 12, 1, 2), |
| 206 | F( 50000000, gpll0, 12, 0, 0), |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 207 | F( 96000000, gpll4, 4, 0, 0), |
| 208 | F(192000000, gpll4, 2, 0, 0), |
| 209 | F(384000000, gpll4, 1, 0, 0), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 210 | F_END |
| 211 | }; |
| 212 | |
| 213 | static struct rcg_clk sdcc1_apps_clk_src = |
| 214 | { |
| 215 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 216 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 217 | .m_reg = (uint32_t *) SDCC1_M, |
| 218 | .n_reg = (uint32_t *) SDCC1_N, |
| 219 | .d_reg = (uint32_t *) SDCC1_D, |
| 220 | |
| 221 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 222 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
| 223 | .current_freq = &rcg_dummy_freq, |
| 224 | |
| 225 | .c = { |
| 226 | .dbg_name = "sdc1_clk", |
| 227 | .ops = &clk_ops_rcg_mnd, |
| 228 | }, |
| 229 | }; |
| 230 | |
| 231 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 232 | { |
| 233 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 234 | .parent = &sdcc1_apps_clk_src.c, |
| 235 | |
| 236 | .c = { |
| 237 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 238 | .ops = &clk_ops_branch, |
| 239 | }, |
| 240 | }; |
| 241 | |
| 242 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 243 | { |
| 244 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 245 | .has_sibling = 1, |
| 246 | |
| 247 | .c = { |
| 248 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 249 | .ops = &clk_ops_branch, |
| 250 | }, |
| 251 | }; |
| 252 | |
| 253 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = { |
| 254 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 255 | .has_sibling = 1, |
| 256 | |
| 257 | .c = { |
| 258 | .dbg_name = "sys_noc_usb30_axi_clk", |
| 259 | .ops = &clk_ops_branch, |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 264 | F( 19200000, gpll0, 1, 0, 0), |
| 265 | F( 125000000, gpll0, 5, 0, 0), |
| 266 | F( 150000000, gpll0, 4, 0, 0), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 267 | F_END |
| 268 | }; |
| 269 | |
| 270 | static struct rcg_clk usb30_master_clk_src = { |
| 271 | .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR, |
| 272 | .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR, |
| 273 | .m_reg = (uint32_t *) USB30_MASTER_M, |
| 274 | .n_reg = (uint32_t *) USB30_MASTER_N, |
| 275 | .d_reg = (uint32_t *) USB30_MASTER_D, |
| 276 | |
| 277 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 278 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 279 | .current_freq = &rcg_dummy_freq, |
| 280 | |
| 281 | .c = { |
| 282 | .dbg_name = "usb30_master_clk_src", |
| 283 | .ops = &clk_ops_rcg, |
| 284 | }, |
| 285 | }; |
| 286 | |
| 287 | static struct branch_clk gcc_usb30_master_clk = { |
| 288 | .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR, |
| 289 | .bcr_reg = (uint32_t *) USB_30_BCR, |
| 290 | .parent = &usb30_master_clk_src.c, |
| 291 | |
| 292 | .c = { |
| 293 | .dbg_name = "usb30_master_clk", |
| 294 | .ops = &clk_ops_branch, |
| 295 | }, |
| 296 | }; |
| 297 | |
| 298 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 299 | F( 60000000, gpll0, 10, 0, 0), |
| 300 | F_END |
| 301 | }; |
| 302 | |
| 303 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 304 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 305 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 306 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 307 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 308 | .current_freq = &rcg_dummy_freq, |
| 309 | |
| 310 | .c = { |
| 311 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 312 | .ops = &clk_ops_rcg, |
| 313 | }, |
| 314 | }; |
| 315 | |
| 316 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 317 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 318 | .has_sibling = 0, |
| 319 | .parent = &usb30_mock_utmi_clk_src.c, |
| 320 | |
| 321 | .c = { |
| 322 | .dbg_name = "usb30_mock_utmi_clk", |
| 323 | .ops = &clk_ops_branch, |
| 324 | }, |
| 325 | }; |
| 326 | |
| 327 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 328 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 329 | .has_sibling = 1, |
| 330 | |
| 331 | .c = { |
| 332 | .dbg_name = "usb30_sleep_clk", |
| 333 | .ops = &clk_ops_branch, |
| 334 | }, |
| 335 | }; |
| 336 | |
| 337 | static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = { |
| 338 | F( 1200000, cxo, 16, 0, 0), |
| 339 | F_END |
| 340 | }; |
| 341 | |
| 342 | static struct rcg_clk usb30_phy_aux_clk_src = { |
| 343 | .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR, |
| 344 | .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR, |
| 345 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 346 | .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src, |
| 347 | .current_freq = &rcg_dummy_freq, |
| 348 | |
| 349 | .c = { |
| 350 | .dbg_name = "usb30_phy_aux_clk_src", |
| 351 | .ops = &clk_ops_rcg, |
| 352 | }, |
| 353 | }; |
| 354 | |
| 355 | static struct branch_clk gcc_usb30_phy_aux_clk = { |
| 356 | .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR, |
| 357 | .has_sibling = 0, |
| 358 | .parent = &usb30_phy_aux_clk_src.c, |
| 359 | |
| 360 | .c = { |
| 361 | .dbg_name = "usb30_phy_aux_clk", |
| 362 | .ops = &clk_ops_branch, |
| 363 | }, |
| 364 | }; |
| 365 | |
| 366 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 367 | .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR, |
| 368 | .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR, |
| 369 | .has_sibling = 1, |
| 370 | |
| 371 | .c = { |
| 372 | .dbg_name = "usb30_pipe_clk", |
| 373 | .ops = &clk_ops_branch, |
| 374 | }, |
| 375 | }; |
| 376 | |
| 377 | static struct reset_clk gcc_usb30_phy_reset = { |
| 378 | .bcr_reg = (uint32_t )USB30_PHY_BCR, |
| 379 | |
| 380 | .c = { |
| 381 | .dbg_name = "usb30_phy_reset", |
| 382 | .ops = &clk_ops_rst, |
| 383 | }, |
| 384 | }; |
| 385 | |
| 386 | static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { |
| 387 | .cbcr_reg = (uint32_t *)USB_PHY_CFG_AHB2PHY_CBCR, |
| 388 | .has_sibling = 1, |
| 389 | |
| 390 | .c = { |
| 391 | .dbg_name = "usb_phy_cfg_ahb2phy_clk", |
| 392 | .ops = &clk_ops_branch, |
| 393 | }, |
| 394 | }; |
| 395 | |
| 396 | |
| 397 | /* Clock lookup table */ |
| 398 | static struct clk_lookup msm_thulium_clocks[] = |
| 399 | { |
| 400 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 401 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 402 | |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame^] | 403 | CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c), |
Channagoud Kadabi | 35503c4 | 2014-11-14 16:22:43 -0800 | [diff] [blame] | 404 | CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c), |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 405 | |
| 406 | /* USB30 clocks */ |
| 407 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 408 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 409 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 410 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
| 411 | CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c), |
| 412 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 413 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 414 | |
| 415 | CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c), |
| 416 | }; |
| 417 | |
| 418 | void platform_clock_init(void) |
| 419 | { |
| 420 | clk_init(msm_thulium_clocks, ARRAY_SIZE(msm_thulium_clocks)); |
| 421 | } |