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gerrit-public.fairphone.software / kernel / lk / a4c9d3a60ac02b027e9948e8c90e4be745f9cb1a / . / platform / msm8226 / include / platform / iomap.h
blob: 851e79875711f3408504d03151ef14c7af288c1b [file] [log] [blame]
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
Deepa Dinamania63c5182013-01-30 12:39:34 -0800[diff] [blame]29#ifndef _PLATFORM_MSM8226_IOMAP_H_
30#define _PLATFORM_MSM8226_IOMAP_H_
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]31
32#define MSM_IOMAP_BASE 0xF9000000
33#define MSM_IOMAP_END 0xFEFFFFFF
34
35#define SDRAM_START_ADDR 0x00000000
36
37#define MSM_SHARED_BASE 0x0FA00000
38
39#define APPS_SS_BASE 0xF9000000
40
Deepa Dinamani595d6f92013-02-26 13:58:03 -0800[diff] [blame]41#define SYSTEM_IMEM_BASE 0xFE800000
Pavel Nedev16f49232013-04-29 16:15:36 +0300[diff] [blame]42#define MSM_SHARED_IMEM_BASE 0xFE805000
43
44#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Pavel Nedeva4c9d3a2013-05-15 14:42:34 +0300[diff] [blame^]45#define DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0x0)
46#define EMERGENCY_DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0xFE0)
Deepa Dinamani595d6f92013-02-26 13:58:03 -0800[diff] [blame]47
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]48#define MSM_GIC_DIST_BASE APPS_SS_BASE
49#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
50#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
51#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
52#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
53
54#define PERIPH_SS_BASE 0xF9800000
55
56#define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000)
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
Channagoud Kadabi2a4e6f92013-05-02 17:07:13 -0700[diff] [blame]58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]59#define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800)
60#define MSM_SDC3_BAM_BASE (PERIPH_SS_BASE + 0x00044000)
61#define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000)
Channagoud Kadabi2a4e6f92013-05-02 17:07:13 -0700[diff] [blame]62#define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]63#define MSM_SDC3_DML_BASE (PERIPH_SS_BASE + 0x00064800)
64#define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000)
65#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
66#define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800)
Channagoud Kadabi2a4e6f92013-05-02 17:07:13 -0700[diff] [blame]67#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]68
69#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
70#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
71#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
72#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
73#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
74#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
75#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
76
77#define CLK_CTL_BASE 0xFC400000
78
79#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
80
81#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]82
83#define SPMI_BASE 0xFC4C0000
84#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
85#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
86
87#define MSM_CE1_BAM_BASE 0xFD404000
88#define MSM_CE1_BASE 0xFD41A000
89
90#define TLMM_BASE_ADDR 0xFD510000
91#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
92#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
93
94#define MPM2_MPM_CTRL_BASE 0xFC4A1000
95#define MPM2_MPM_PS_HOLD 0xFC4AB000
96
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]97/* GPLL */
Deepa Dinamani0a6c48c2013-02-04 15:45:01 -0800[diff] [blame]98#define GPLL0_MODE CLK_CTL_BASE
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]99#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
100#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
101#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
102
Deepa Dinamanic51ad202013-04-02 14:58:56 -0700[diff] [blame]103/* CE 1 */
104#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
105#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
106#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
107#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
108#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
109#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
110
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]111/* SDCC */
112#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
113#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
114#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
115#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
116#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
117#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
118#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
119#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
120#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
121
122/* UART */
123#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
Deepa Dinamani0a6c48c2013-02-04 15:45:01 -0800[diff] [blame]124#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784)
125#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C)
126#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790)
127#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794)
128#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798)
129#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]130
131/* USB */
132#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
133#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
134#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
135#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
136
Channagoud Kadabi2a4e6f92013-05-02 17:07:13 -0700[diff] [blame]137/* SDHCI */
138#define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078)
139#define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0)
140#define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8)
141
142/* DRV strength for sdcc */
143#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
Deepa Dinamani645e9b12012-12-21 14:23:40 -0800[diff] [blame]144#endif