Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #include <debug.h> |
Travis Geiselbrecht | 2c691e8 | 2008-09-04 02:41:01 -0700 | [diff] [blame] | 24 | #include <reg.h> |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 25 | #include <dev/uart.h> |
| 26 | #include <platform/omap3.h> |
| 27 | #include <target/debugconfig.h> |
| 28 | |
| 29 | struct uart_stat { |
| 30 | addr_t base; |
| 31 | uint shift; |
| 32 | }; |
| 33 | |
| 34 | static struct uart_stat uart[3] = { |
| 35 | { OMAP_UART1_BASE, 2 }, |
| 36 | { OMAP_UART2_BASE, 2 }, |
| 37 | { OMAP_UART3_BASE, 2 }, |
| 38 | }; |
| 39 | |
| 40 | static inline void write_uart_reg(int port, uint reg, unsigned char data) |
| 41 | { |
| 42 | *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift)) = data; |
| 43 | } |
| 44 | |
| 45 | static inline unsigned char read_uart_reg(int port, uint reg) |
| 46 | { |
| 47 | return *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift)); |
| 48 | } |
| 49 | |
| 50 | #define LCR_8N1 0x03 |
| 51 | |
| 52 | #define FCR_FIFO_EN 0x01 /* Fifo enable */ |
| 53 | #define FCR_RXSR 0x02 /* Receiver soft reset */ |
| 54 | #define FCR_TXSR 0x04 /* Transmitter soft reset */ |
| 55 | |
| 56 | #define MCR_DTR 0x01 |
| 57 | #define MCR_RTS 0x02 |
| 58 | #define MCR_DMA_EN 0x04 |
| 59 | #define MCR_TX_DFR 0x08 |
| 60 | |
| 61 | #define LCR_WLS_MSK 0x03 /* character length select mask */ |
| 62 | #define LCR_WLS_5 0x00 /* 5 bit character length */ |
| 63 | #define LCR_WLS_6 0x01 /* 6 bit character length */ |
| 64 | #define LCR_WLS_7 0x02 /* 7 bit character length */ |
| 65 | #define LCR_WLS_8 0x03 /* 8 bit character length */ |
| 66 | #define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ |
| 67 | #define LCR_PEN 0x08 /* Parity eneble */ |
| 68 | #define LCR_EPS 0x10 /* Even Parity Select */ |
| 69 | #define LCR_STKP 0x20 /* Stick Parity */ |
| 70 | #define LCR_SBRK 0x40 /* Set Break */ |
| 71 | #define LCR_BKSE 0x80 /* Bank select enable */ |
| 72 | |
| 73 | #define LSR_DR 0x01 /* Data ready */ |
| 74 | #define LSR_OE 0x02 /* Overrun */ |
| 75 | #define LSR_PE 0x04 /* Parity error */ |
| 76 | #define LSR_FE 0x08 /* Framing error */ |
| 77 | #define LSR_BI 0x10 /* Break */ |
| 78 | #define LSR_THRE 0x20 /* Xmit holding register empty */ |
| 79 | #define LSR_TEMT 0x40 /* Xmitter empty */ |
| 80 | #define LSR_ERR 0x80 /* Error */ |
| 81 | |
| 82 | #define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ |
| 83 | #define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ |
| 84 | #define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ |
| 85 | |
| 86 | #define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ |
| 87 | |
| 88 | void uart_init_port(int port, uint baud) |
| 89 | { |
| 90 | /* clear the tx & rx fifo and disable */ |
| 91 | uint16_t baud_divisor = (V_NS16550_CLK / 16 / baud); |
| 92 | |
| 93 | write_uart_reg(port, UART_IER, 0); |
| 94 | write_uart_reg(port, UART_LCR, LCR_BKSE | LCRVAL); // config mode A |
| 95 | write_uart_reg(port, UART_DLL, baud_divisor & 0xff); |
| 96 | write_uart_reg(port, UART_DLH, (baud_divisor >> 8) & 0xff); |
| 97 | write_uart_reg(port, UART_LCR, LCRVAL); // operational mode |
| 98 | write_uart_reg(port, UART_MCR, MCRVAL); |
| 99 | write_uart_reg(port, UART_FCR, FCRVAL); |
| 100 | write_uart_reg(port, UART_MDR1, 0); // UART 16x mode |
| 101 | |
| 102 | // write_uart_reg(port, UART_LCR, 0xBF); // config mode B |
| 103 | // write_uart_reg(port, UART_EFR, (1<<7)|(1<<6)); // hw flow control |
| 104 | // write_uart_reg(port, UART_LCR, LCRVAL); // operational mode |
| 105 | } |
| 106 | |
| 107 | void uart_init_early(void) |
| 108 | { |
Travis Geiselbrecht | 2c691e8 | 2008-09-04 02:41:01 -0700 | [diff] [blame] | 109 | /* UART1 */ |
| 110 | RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1), |
| 111 | RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1), |
| 112 | |
| 113 | /* UART2 */ |
| 114 | RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1), |
| 115 | RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1), |
| 116 | |
| 117 | /* UART3 */ |
| 118 | RMWREG32(CM_FCLKEN_PER, 11, 1, 1), |
| 119 | RMWREG32(CM_ICLKEN_PER, 11, 1, 1), |
| 120 | |
Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 121 | uart_init_port(DEBUG_UART, 115200); |
| 122 | } |
| 123 | |
| 124 | void uart_init(void) |
| 125 | { |
| 126 | } |
| 127 | |
| 128 | int uart_putc(int port, char c ) |
| 129 | { |
| 130 | while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out |
| 131 | ; |
| 132 | write_uart_reg(port, UART_THR, c); |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | int uart_getc(int port, bool wait) /* returns -1 if no data available */ |
| 137 | { |
| 138 | if (wait) { |
| 139 | while (!(read_uart_reg(port, UART_LSR) & (1<<0))) // wait for data to show up in the rx fifo |
| 140 | ; |
| 141 | } else { |
| 142 | if (!(read_uart_reg(port, UART_LSR) & (1<<0))) |
| 143 | return -1; |
| 144 | } |
| 145 | return read_uart_reg(port, UART_RHR); |
| 146 | } |
| 147 | |
| 148 | void uart_flush_tx(int port) |
| 149 | { |
| 150 | while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out |
| 151 | ; |
| 152 | } |
| 153 | |
| 154 | void uart_flush_rx(int port) |
| 155 | { |
| 156 | // empty the rx fifo |
| 157 | while (read_uart_reg(port, UART_LSR) & (1<<0)) { |
| 158 | volatile char c = read_uart_reg(port, UART_RHR); |
| 159 | (void)c; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | |