Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Code Aurora nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 29 | #include <err.h> |
| 30 | #include <assert.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 31 | #include <debug.h> |
| 32 | #include <reg.h> |
| 33 | #include <platform/iomap.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 34 | #include <mmc.h> |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 35 | #include <clock.h> |
| 36 | #include <platform/clock.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 37 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 38 | void hsusb_clock_init(void) |
| 39 | { |
| 40 | int ret; |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 41 | struct clk *iclk, *cclk; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 42 | |
| 43 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 44 | if(ret) |
| 45 | { |
| 46 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 47 | ASSERT(0); |
| 48 | } |
| 49 | |
| 50 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 51 | if(ret) |
| 52 | { |
| 53 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 54 | ASSERT(0); |
| 55 | } |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 56 | |
| 57 | mdelay(20); |
| 58 | |
| 59 | iclk = clk_get("usb_iface_clk"); |
| 60 | cclk = clk_get("usb_core_clk"); |
| 61 | |
| 62 | /* Disable USB all clock init */ |
| 63 | writel(0, USB_BOOT_CLOCK_CTL); |
| 64 | |
| 65 | clk_disable(iclk); |
| 66 | clk_disable(cclk); |
| 67 | |
| 68 | mdelay(20); |
| 69 | |
| 70 | /* Start the block reset for usb */ |
| 71 | writel(1, USB_HS_BCR); |
| 72 | |
| 73 | mdelay(20); |
| 74 | |
| 75 | /* Take usb block out of reset */ |
| 76 | writel(0, USB_HS_BCR); |
| 77 | |
| 78 | mdelay(20); |
| 79 | |
| 80 | ret = clk_enable(iclk); |
| 81 | |
| 82 | if(ret) |
| 83 | { |
| 84 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 85 | ASSERT(0); |
| 86 | } |
| 87 | |
| 88 | ret = clk_enable(cclk); |
| 89 | |
| 90 | if(ret) |
| 91 | { |
| 92 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 93 | ASSERT(0); |
| 94 | } |
| 95 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 96 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 97 | |
| 98 | void clock_init_mmc(uint32_t interface) |
| 99 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 100 | char clk_name[64]; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 101 | int ret; |
| 102 | |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 103 | snprintf(clk_name, 64, "sdc%u_iface_clk", interface); |
| 104 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 105 | /* enable interface clock */ |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 106 | ret = clk_get_set_enable(clk_name, 0, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 107 | if(ret) |
| 108 | { |
| 109 | dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret); |
| 110 | ASSERT(0); |
| 111 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | /* Configure MMC clock */ |
| 115 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 116 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 117 | int ret; |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 118 | uint32_t reg; |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 119 | char clk_name[64]; |
| 120 | |
| 121 | snprintf(clk_name, 64, "sdc%u_core_clk", interface); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 122 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 123 | if(freq == MMC_CLK_400KHZ) |
| 124 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 125 | ret = clk_get_set_enable(clk_name, 400000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 126 | } |
| 127 | else if(freq == MMC_CLK_50MHZ) |
| 128 | { |
Neeti Desai | ddc771b | 2012-08-28 18:17:04 -0700 | [diff] [blame] | 129 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 130 | } |
| 131 | else |
| 132 | { |
| 133 | dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq); |
| 134 | ASSERT(0); |
| 135 | } |
| 136 | |
| 137 | |
| 138 | if(ret) |
| 139 | { |
| 140 | dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret); |
| 141 | ASSERT(0); |
| 142 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 143 | |
| 144 | reg = 0; |
| 145 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 146 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 147 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
| 148 | writel(reg, MMC_BOOT_MCI_CLK); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 149 | } |
| 150 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 151 | /* Configure UART clock based on the UART block id*/ |
| 152 | void clock_config_uart_dm(uint8_t id) |
| 153 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 154 | int ret; |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 155 | |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame^] | 156 | |
| 157 | ret = clk_get_set_enable("uart2_iface_clk", 0, 1); |
| 158 | if(ret) |
| 159 | { |
| 160 | dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret); |
| 161 | ASSERT(0); |
| 162 | } |
| 163 | |
| 164 | ret = clk_get_set_enable("uart2_core_clk", 7372800, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 165 | if(ret) |
| 166 | { |
| 167 | dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret); |
| 168 | ASSERT(0); |
| 169 | } |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 170 | } |