blob: 93837f921f245d150de8c2de57366a619a0fdcbc [file] [log] [blame]
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +05301/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <smem.h>
32#include <err.h>
33#include <msm_panel.h>
34#include <mipi_dsi.h>
35#include <pm8x41.h>
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +053036#include <pm8x41_wled.h>
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +053037#include <board.h>
38#include <mdp3.h>
39#include <scm.h>
40#include <platform/gpio.h>
41#include <platform/iomap.h>
42#include <target/display.h>
43
44#include "include/panel.h"
45#include "include/display_resource.h"
46
47#define VCO_DELAY_USEC 1000
48#define GPIO_STATE_LOW 0
49#define GPIO_STATE_HIGH 2
50#define RESET_GPIO_SEQ_LEN 3
51#define PWM_DUTY_US 13
52#define PWM_PERIOD_US 27
53
54static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
55{
56 writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
57 mdelay(1);
58 writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
59 mdelay(1);
60}
61
62static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base)
63{
64 uint32_t pll_locked = 0;
65
66 writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
67 udelay(1);
68 writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
69
70 /*
71 * Add hardware recommended delays between register writes for
72 * the updates to take effect. These delays are necessary for the
73 * PLL to successfully lock
74 */
75 writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
76 udelay(1);
77 writel(0x01, pll_base + 0x0020); /* GLB CFG */
78 udelay(1);
79 writel(0x05, pll_base + 0x0020); /* GLB CFG */
80 udelay(1);
81 writel(0x0f, pll_base + 0x0020); /* GLB CFG */
82 udelay(1);
83
84 writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
85 udelay(1);
86 writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
87 udelay(512);
88 pll_locked = readl(pll_base + 0x00c0) & 0x01;
89
90 return pll_locked;
91}
92
93int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
94{
95 struct pm8x41_mpp mpp;
96 int rc;
97
98 if (bl->bl_interface_type == BL_DCS)
99 return 0;
100
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530101 mpp.base = PM8x41_MMP2_BASE;
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530102 mpp.vin = MPP_VIN0;
103 if (enable) {
104 pm_pwm_enable(false);
105 rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
106 if (rc < 0)
107 mpp.mode = MPP_HIGH;
108 else {
109 mpp.mode = MPP_DTEST1;
110 pm_pwm_enable(true);
111 }
112 pm8x41_config_output_mpp(&mpp);
113 pm8x41_enable_mpp(&mpp, MPP_ENABLE);
114 } else {
115 pm_pwm_enable(false);
116 pm8x41_enable_mpp(&mpp, MPP_DISABLE);
117 }
118 mdelay(20);
119 return 0;
120}
121
122int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
123{
124 int32_t ret = 0;
125 struct mdss_dsi_pll_config *pll_data;
126 dprintf(SPEW, "target_panel_clock\n");
127
128 pll_data = pinfo->mipi.dsi_pll_config;
129 pll_data->vco_delay = VCO_DELAY_USEC;
130
131 if (enable) {
132 mdp_gdsc_ctrl(enable);
133 mdss_bus_clocks_enable();
134 mdp_clock_enable();
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530135
136 /*
137 * Enable auto functional gating
138 * on DSI CMD AXI fetch from DDR
139 */
140 writel(0x3ffff, MDP_CGC_EN);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530141 ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
142 if (ret) {
143 dprintf(CRITICAL,
144 "%s: Failed to restore MDP security configs",
145 __func__);
146 mdp_clock_disable();
147 mdss_bus_clocks_disable();
148 mdp_gdsc_ctrl(0);
149 return ret;
150 }
151 mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
152 mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
153 MIPI_DSI0_BASE, pll_data);
154 if (!dsi_pll_enable_seq_8909(DSI0_PLL_BASE))
155 dprintf(CRITICAL, "Not able to enable the pll\n");
156 gcc_dsi_clocks_enable(pll_data->pclk_m,
157 pll_data->pclk_n,
158 pll_data->pclk_d);
159 } else if(!target_cont_splash_screen()) {
160 gcc_dsi_clocks_disable();
161 mdp_clock_disable();
162 mdss_bus_clocks_disable();
163 mdp_gdsc_ctrl(enable);
164 }
165
166 return 0;
167}
168
169int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
170 struct msm_panel_info *pinfo)
171{
172 int ret = NO_ERROR;
173 uint32_t hw_id = board_hardware_id();
174 uint32_t hw_subtype = board_hardware_subtype();
175
176 if (enable) {
177 if (pinfo->mipi.use_enable_gpio) {
178 gpio_tlmm_config(enable_gpio.pin_id, 0,
179 enable_gpio.pin_direction, enable_gpio.pin_pull,
180 enable_gpio.pin_strength,
181 enable_gpio.pin_state);
182
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530183 gpio_set(enable_gpio.pin_id, 2);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530184 }
185
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530186 if (hw_id == HW_PLATFORM_SURF || (hw_id == HW_PLATFORM_MTP)) {
187 /* configure backlight gpio for CDP and MTP */
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530188 gpio_tlmm_config(bkl_gpio.pin_id, 0,
189 bkl_gpio.pin_direction, bkl_gpio.pin_pull,
190 bkl_gpio.pin_strength, bkl_gpio.pin_state);
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530191 gpio_set(bkl_gpio.pin_id, 2);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530192 }
193
194 gpio_tlmm_config(reset_gpio.pin_id, 0,
195 reset_gpio.pin_direction, reset_gpio.pin_pull,
196 reset_gpio.pin_strength, reset_gpio.pin_state);
197
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530198 gpio_set(reset_gpio.pin_id, 2);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530199
200 /* reset */
201 for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
202 if (resetseq->pin_state[i] == GPIO_STATE_LOW)
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530203 gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530204 else
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530205 gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530206 mdelay(resetseq->sleep[i]);
207 }
208 } else if(!target_cont_splash_screen()) {
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530209 gpio_set(reset_gpio.pin_id, 0);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530210 if (pinfo->mipi.use_enable_gpio)
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530211 gpio_set(enable_gpio.pin_id, 0);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530212 }
213
214 return ret;
215}
216
217int target_ldo_ctrl(uint8_t enable)
218{
219 /*
220 * The PMIC regulators needed for display are enabled in SBL.
221 * There is no access to the regulators is LK.
222 */
223 return NO_ERROR;
224}
225
226bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
227{
Shivaraj Shettyaf4c6072014-11-04 16:25:31 +0530228 return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +0530229}
230
231void target_display_init(const char *panel_name)
232{
233 uint32_t panel_loop = 0;
234 uint32_t ret = 0;
235
236 if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
237 dprintf(INFO, "Skip panel configuration\n");
238 return;
239 }
240
241 do {
242 target_force_cont_splash_disable(false);
243 ret = gcdb_display_init(panel_name, MDP_REV_305, MIPI_FB_ADDR);
244 if (!ret || ret == ERR_NOT_SUPPORTED) {
245 break;
246 } else {
247 target_force_cont_splash_disable(true);
248 msm_display_off();
249 }
250 } while (++panel_loop <= oem_panel_max_auto_detect_panels());
251}
252
253void target_display_shutdown(void)
254{
255 gcdb_display_shutdown();
256}