Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <mdp3.h> |
| 32 | #include <mipi_dsi.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <platform/clock.h> |
| 35 | #include <target/display.h> |
| 36 | |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 37 | void config_renesas_dsi_video_mode(void) |
| 38 | { |
| 39 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 40 | unsigned char dst_format = 3; /* RGB888 */ |
| 41 | unsigned char traffic_mode = 2; /* non burst mode with sync start events */ |
| 42 | unsigned char lane_en = 3; /* 3 Lanes -- Enables Data Lane0, 1, 2 */ |
| 43 | unsigned long low_pwr_stop_mode = 1; |
| 44 | unsigned char eof_bllp_pwr = 0x9; /* Needed or else will have blank line at top of display */ |
| 45 | unsigned char interleav = 0; |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 46 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 47 | unsigned short display_wd = REN_MIPI_FB_WIDTH; |
| 48 | unsigned short display_ht = REN_MIPI_FB_HEIGHT; |
| 49 | unsigned short image_wd = REN_MIPI_FB_WIDTH; |
| 50 | unsigned short image_ht = REN_MIPI_FB_HEIGHT; |
| 51 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 52 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 53 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 54 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 55 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 56 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
Aparna Mallavarapu | 45869c3 | 2011-08-05 13:22:35 +0530 | [diff] [blame] | 57 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 58 | dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n"); |
| 59 | dprintf(SPEW, "Traffic mode: burst mode\n"); |
| 60 | if (machine_is_7x25a()) { |
| 61 | dprintf(CRITICAL, |
| 62 | "Entered 7x25A in config_renesas_dsi_video_mode\n"); |
| 63 | dprintf(SPEW, "Data Lane: 1 lane\n"); |
| 64 | display_wd = REN_MIPI_FB_WIDTH_HVGA; |
| 65 | display_ht = REN_MIPI_FB_HEIGHT_HVGA; |
| 66 | image_wd = REN_MIPI_FB_WIDTH_HVGA; |
| 67 | image_ht = REN_MIPI_FB_HEIGHT_HVGA; |
| 68 | hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA; |
| 69 | hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA; |
| 70 | vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA; |
| 71 | vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES_HVGA; |
| 72 | hsync_width = MIPI_HSYNC_PULSE_WIDTH_HVGA; |
| 73 | vsync_width = MIPI_VSYNC_PULSE_WIDTH_HVGA; |
| 74 | lane_en = 1; |
| 75 | } else { |
| 76 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
| 77 | } |
Aparna Mallavarapu | 45869c3 | 2011-08-05 13:22:35 +0530 | [diff] [blame] | 78 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 79 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 80 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 81 | writel(0x00000000, DSI_CLK_CTRL); |
| 82 | writel(0x00000000, DSI_CLK_CTRL); |
| 83 | writel(0x00000000, DSI_CLK_CTRL); |
| 84 | writel(0x00000000, DSI_CLK_CTRL); |
| 85 | writel(0x00000002, DSI_CLK_CTRL); |
| 86 | writel(0x00000006, DSI_CLK_CTRL); |
| 87 | writel(0x0000000e, DSI_CLK_CTRL); |
| 88 | writel(0x0000001e, DSI_CLK_CTRL); |
| 89 | writel(0x0000003e, DSI_CLK_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 90 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 91 | writel(0, DSI_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 92 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 93 | writel(0, DSI_ERR_INT_MASK0); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 94 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 95 | writel(0x02020202, DSI_INT_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 96 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 97 | writel(((hsync_porch_bp + display_wd) << 16) | hsync_porch_bp, |
| 98 | DSI_VIDEO_MODE_ACTIVE_H); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 99 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 100 | writel(((vsync_porch_bp + display_ht) << 16) | vsync_porch_bp, |
| 101 | DSI_VIDEO_MODE_ACTIVE_V); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 102 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 103 | writel(((display_ht + vsync_porch_fp + vsync_porch_bp) << 16) | |
| 104 | (display_wd + hsync_porch_fp + hsync_porch_bp), |
| 105 | DSI_VIDEO_MODE_TOTAL); |
| 106 | writel((hsync_width) << 16 | 0, DSI_VIDEO_MODE_HSYNC); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 107 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 108 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 109 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 110 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 111 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 112 | writel(1, DSI_EOT_PACKET_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 113 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 114 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 115 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 116 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 117 | eof_bllp_pwr << 12 | traffic_mode << 8 | dst_format << 4 | 0x0, |
| 118 | DSI_VIDEO_MODE_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 119 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 120 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 121 | writel(0x80006711, DSI_CAL_CTRL); |
| 122 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 123 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 124 | writel(0x00010100, DSI_INT_CTRL); |
| 125 | writel(0x02010202, DSI_INT_CTRL); |
| 126 | writel(0x02030303, DSI_INT_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 127 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 128 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
| 129 | | 0x103, DSI_CTRL); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 130 | } |