Unnati Gandhi | b3820bc | 2014-07-04 16:56:27 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define gpll0_mm_source_val 1 |
| 44 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 45 | |
| 46 | |
| 47 | /* Clock Operations */ |
| 48 | static struct clk_ops clk_ops_branch = |
| 49 | { |
| 50 | .enable = clock_lib2_branch_clk_enable, |
| 51 | .disable = clock_lib2_branch_clk_disable, |
| 52 | .set_rate = clock_lib2_branch_set_rate, |
| 53 | }; |
| 54 | |
| 55 | static struct clk_ops clk_ops_rcg_mnd = |
| 56 | { |
| 57 | .enable = clock_lib2_rcg_enable, |
| 58 | .set_rate = clock_lib2_rcg_set_rate, |
| 59 | }; |
| 60 | |
| 61 | static struct clk_ops clk_ops_rcg = |
| 62 | { |
| 63 | .enable = clock_lib2_rcg_enable, |
| 64 | .set_rate = clock_lib2_rcg_set_rate, |
| 65 | }; |
| 66 | |
| 67 | static struct clk_ops clk_ops_cxo = |
| 68 | { |
| 69 | .enable = cxo_clk_enable, |
| 70 | .disable = cxo_clk_disable, |
| 71 | }; |
| 72 | |
| 73 | static struct clk_ops clk_ops_pll_vote = |
| 74 | { |
| 75 | .enable = pll_vote_clk_enable, |
| 76 | .disable = pll_vote_clk_disable, |
| 77 | .auto_off = pll_vote_clk_disable, |
| 78 | .is_enabled = pll_vote_clk_is_enabled, |
| 79 | }; |
| 80 | |
| 81 | static struct clk_ops clk_ops_vote = |
| 82 | { |
| 83 | .enable = clock_lib2_vote_clk_enable, |
| 84 | .disable = clock_lib2_vote_clk_disable, |
| 85 | }; |
| 86 | |
| 87 | /* Clock Sources */ |
| 88 | static struct fixed_clk cxo_clk_src = |
| 89 | { |
| 90 | .c = { |
| 91 | .rate = 19200000, |
| 92 | .dbg_name = "cxo_clk_src", |
| 93 | .ops = &clk_ops_cxo, |
| 94 | }, |
| 95 | }; |
| 96 | |
| 97 | static struct pll_vote_clk gpll0_clk_src = |
| 98 | { |
| 99 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 100 | .en_mask = BIT(0), |
| 101 | .status_reg = (void *) GPLL0_STATUS, |
| 102 | .status_mask = BIT(17), |
| 103 | .parent = &cxo_clk_src.c, |
| 104 | |
| 105 | .c = { |
| 106 | .rate = 800000000, |
| 107 | .dbg_name = "gpll0_clk_src", |
| 108 | .ops = &clk_ops_pll_vote, |
| 109 | }, |
| 110 | }; |
| 111 | |
| 112 | /* SDCC Clocks */ |
| 113 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 114 | { |
| 115 | F( 144000, cxo, 16, 3, 25), |
| 116 | F( 400000, cxo, 12, 1, 4), |
| 117 | F( 20000000, gpll0, 10, 1, 4), |
| 118 | F( 25000000, gpll0, 16, 1, 2), |
| 119 | F( 50000000, gpll0, 16, 0, 0), |
| 120 | F(100000000, gpll0, 8, 0, 0), |
| 121 | F(177770000, gpll0, 4.5, 0, 0), |
| 122 | F(200000000, gpll0, 4, 0, 0), |
| 123 | F_END |
| 124 | }; |
| 125 | |
| 126 | static struct rcg_clk sdcc1_apps_clk_src = |
| 127 | { |
| 128 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 129 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 130 | .m_reg = (uint32_t *) SDCC1_M, |
| 131 | .n_reg = (uint32_t *) SDCC1_N, |
| 132 | .d_reg = (uint32_t *) SDCC1_D, |
| 133 | |
| 134 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 135 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 136 | .current_freq = &rcg_dummy_freq, |
| 137 | |
| 138 | .c = { |
| 139 | .dbg_name = "sdc1_clk", |
| 140 | .ops = &clk_ops_rcg_mnd, |
| 141 | }, |
| 142 | }; |
| 143 | |
| 144 | /* BLSP1_QUP2 Clocks */ |
| 145 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup2_i2c_apps_clk_src[] = |
| 146 | { |
| 147 | F( 96000, cxo, 10, 1, 2), |
| 148 | F( 4800000, cxo, 4, 0, 0), |
| 149 | F( 9600000, cxo, 2, 0, 0), |
| 150 | F( 16000000, gpll0, 10, 1, 5), |
| 151 | F( 19200000, gpll0, 1, 0, 0), |
| 152 | F( 25000000, gpll0, 16, 1, 2), |
| 153 | F( 50000000, gpll0, 16, 0, 0), |
| 154 | F_END |
| 155 | }; |
| 156 | |
| 157 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 158 | { |
| 159 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 160 | .parent = &sdcc1_apps_clk_src.c, |
| 161 | |
| 162 | .c = { |
| 163 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 164 | .ops = &clk_ops_branch, |
| 165 | }, |
| 166 | }; |
| 167 | |
| 168 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 169 | { |
| 170 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 171 | .has_sibling = 1, |
| 172 | |
| 173 | .c = { |
| 174 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 175 | .ops = &clk_ops_branch, |
| 176 | }, |
| 177 | }; |
| 178 | |
| 179 | static struct rcg_clk sdcc2_apps_clk_src = |
| 180 | { |
| 181 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 182 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 183 | .m_reg = (uint32_t *) SDCC2_M, |
| 184 | .n_reg = (uint32_t *) SDCC2_N, |
| 185 | .d_reg = (uint32_t *) SDCC2_D, |
| 186 | |
| 187 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 188 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 189 | .current_freq = &rcg_dummy_freq, |
| 190 | |
| 191 | .c = { |
| 192 | .dbg_name = "sdc2_clk", |
| 193 | .ops = &clk_ops_rcg_mnd, |
| 194 | }, |
| 195 | }; |
| 196 | |
| 197 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 198 | { |
| 199 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 200 | .parent = &sdcc2_apps_clk_src.c, |
| 201 | |
| 202 | .c = { |
| 203 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 204 | .ops = &clk_ops_branch, |
| 205 | }, |
| 206 | }; |
| 207 | |
| 208 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 209 | { |
| 210 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 211 | .has_sibling = 1, |
| 212 | |
| 213 | .c = { |
| 214 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 215 | .ops = &clk_ops_branch, |
| 216 | }, |
| 217 | }; |
| 218 | |
| 219 | /* UART Clocks */ |
| 220 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 221 | { |
| 222 | F( 3686400, gpll0, 1, 72, 15625), |
| 223 | F( 7372800, gpll0, 1, 144, 15625), |
| 224 | F(14745600, gpll0, 1, 288, 15625), |
| 225 | F(16000000, gpll0, 10, 1, 5), |
| 226 | F(19200000, cxo, 1, 0, 0), |
| 227 | F(24000000, gpll0, 1, 3, 100), |
| 228 | F(25000000, gpll0, 16, 1, 2), |
| 229 | F(32000000, gpll0, 1, 1, 25), |
| 230 | F(40000000, gpll0, 1, 1, 20), |
| 231 | F(46400000, gpll0, 1, 29, 500), |
| 232 | F(48000000, gpll0, 1, 3, 50), |
| 233 | F(51200000, gpll0, 1, 8, 125), |
| 234 | F(56000000, gpll0, 1, 7, 100), |
| 235 | F(58982400, gpll0, 1,1152, 15625), |
| 236 | F(60000000, gpll0, 1, 3, 40), |
| 237 | F_END |
| 238 | }; |
| 239 | |
| 240 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 241 | { |
| 242 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 243 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 244 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 245 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 246 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 247 | |
| 248 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 249 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 250 | .current_freq = &rcg_dummy_freq, |
| 251 | |
| 252 | .c = { |
| 253 | .dbg_name = "blsp1_uart2_apps_clk", |
| 254 | .ops = &clk_ops_rcg_mnd, |
| 255 | }, |
| 256 | }; |
| 257 | |
| 258 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 259 | { |
| 260 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 261 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 262 | |
| 263 | .c = { |
| 264 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 265 | .ops = &clk_ops_branch, |
| 266 | }, |
| 267 | }; |
| 268 | |
| 269 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 270 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 271 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 272 | .en_mask = BIT(10), |
| 273 | |
| 274 | .c = { |
| 275 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 276 | .ops = &clk_ops_vote, |
| 277 | }, |
| 278 | }; |
| 279 | |
| 280 | /* USB Clocks */ |
| 281 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 282 | { |
| 283 | F(80000000, gpll0, 10, 0, 0), |
| 284 | F_END |
| 285 | }; |
| 286 | |
| 287 | static struct rcg_clk usb_hs_system_clk_src = |
| 288 | { |
| 289 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 290 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 291 | |
| 292 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 293 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 294 | .current_freq = &rcg_dummy_freq, |
| 295 | |
| 296 | .c = { |
| 297 | .dbg_name = "usb_hs_system_clk", |
| 298 | .ops = &clk_ops_rcg, |
| 299 | }, |
| 300 | }; |
| 301 | |
| 302 | static struct branch_clk gcc_usb_hs_system_clk = |
| 303 | { |
| 304 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 305 | .parent = &usb_hs_system_clk_src.c, |
| 306 | |
| 307 | .c = { |
| 308 | .dbg_name = "gcc_usb_hs_system_clk", |
| 309 | .ops = &clk_ops_branch, |
| 310 | }, |
| 311 | }; |
| 312 | |
| 313 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 314 | { |
| 315 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 316 | .has_sibling = 1, |
| 317 | |
| 318 | .c = { |
| 319 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 320 | .ops = &clk_ops_branch, |
| 321 | }, |
| 322 | }; |
| 323 | |
| 324 | /* Display clocks */ |
| 325 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 326 | F_MM(19200000, cxo, 1, 0, 0), |
| 327 | F_END |
| 328 | }; |
| 329 | |
| 330 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
| 331 | F_MM( 80000000, gpll0, 10, 0, 0), |
| 332 | F_MM( 100000000, gpll0, 8, 0, 0), |
| 333 | F_MM( 200000000, gpll0, 4, 0, 0), |
| 334 | F_MM( 320000000, gpll0, 2.5, 0, 0), |
| 335 | F_END |
| 336 | }; |
| 337 | |
| 338 | static struct rcg_clk dsi_esc0_clk_src = { |
| 339 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 340 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 341 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 342 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 343 | |
| 344 | .c = { |
| 345 | .dbg_name = "dsi_esc0_clk_src", |
| 346 | .ops = &clk_ops_rcg, |
| 347 | }, |
| 348 | }; |
| 349 | |
| 350 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 351 | F_MM(19200000, cxo, 1, 0, 0), |
| 352 | F_END |
| 353 | }; |
| 354 | |
| 355 | static struct rcg_clk vsync_clk_src = { |
| 356 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 357 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 358 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 359 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 360 | |
| 361 | .c = { |
| 362 | .dbg_name = "vsync_clk_src", |
| 363 | .ops = &clk_ops_rcg, |
| 364 | }, |
| 365 | }; |
| 366 | |
| 367 | static struct branch_clk mdss_esc0_clk = { |
| 368 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 369 | .parent = &dsi_esc0_clk_src.c, |
| 370 | .has_sibling = 0, |
| 371 | |
| 372 | .c = { |
| 373 | .dbg_name = "mdss_esc0_clk", |
| 374 | .ops = &clk_ops_branch, |
| 375 | }, |
| 376 | }; |
| 377 | |
| 378 | static struct branch_clk mdss_axi_clk = { |
| 379 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 380 | .has_sibling = 1, |
| 381 | |
| 382 | .c = { |
| 383 | .dbg_name = "mdss_axi_clk", |
| 384 | .ops = &clk_ops_branch, |
| 385 | }, |
| 386 | }; |
| 387 | |
| 388 | static struct branch_clk mdp_ahb_clk = { |
| 389 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 390 | .has_sibling = 1, |
| 391 | |
| 392 | .c = { |
| 393 | .dbg_name = "mdp_ahb_clk", |
| 394 | .ops = &clk_ops_branch, |
| 395 | }, |
| 396 | }; |
| 397 | |
| 398 | static struct rcg_clk mdss_mdp_clk_src = { |
| 399 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 400 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 401 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 402 | .freq_tbl = ftbl_mdp_clk, |
| 403 | .current_freq = &rcg_dummy_freq, |
| 404 | |
| 405 | .c = { |
| 406 | .dbg_name = "mdss_mdp_clk_src", |
| 407 | .ops = &clk_ops_rcg, |
| 408 | }, |
| 409 | }; |
| 410 | |
| 411 | static struct branch_clk mdss_mdp_clk = { |
| 412 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 413 | .parent = &mdss_mdp_clk_src.c, |
| 414 | .has_sibling = 0, |
| 415 | |
| 416 | .c = { |
| 417 | .dbg_name = "mdss_mdp_clk", |
| 418 | .ops = &clk_ops_branch, |
| 419 | }, |
| 420 | }; |
| 421 | |
| 422 | static struct branch_clk mdss_vsync_clk = { |
| 423 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 424 | .parent = &vsync_clk_src.c, |
| 425 | .has_sibling = 0, |
| 426 | |
| 427 | .c = { |
| 428 | .dbg_name = "mdss_vsync_clk", |
| 429 | .ops = &clk_ops_branch, |
| 430 | }, |
| 431 | }; |
| 432 | |
| 433 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 434 | F(160000000, gpll0, 5, 0, 0), |
| 435 | F_END |
| 436 | }; |
| 437 | |
| 438 | static struct rcg_clk ce1_clk_src = { |
| 439 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 440 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 441 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 442 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 443 | .current_freq = &rcg_dummy_freq, |
| 444 | |
| 445 | .c = { |
| 446 | .dbg_name = "ce1_clk_src", |
| 447 | .ops = &clk_ops_rcg, |
| 448 | }, |
| 449 | }; |
| 450 | |
| 451 | static struct vote_clk gcc_ce1_clk = { |
| 452 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 453 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 454 | .en_mask = BIT(2), |
| 455 | |
| 456 | .c = { |
| 457 | .dbg_name = "gcc_ce1_clk", |
| 458 | .ops = &clk_ops_vote, |
| 459 | }, |
| 460 | }; |
| 461 | |
| 462 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 463 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 464 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 465 | .en_mask = BIT(0), |
| 466 | |
| 467 | .c = { |
| 468 | .dbg_name = "gcc_ce1_ahb_clk", |
| 469 | .ops = &clk_ops_vote, |
| 470 | }, |
| 471 | }; |
| 472 | |
| 473 | static struct vote_clk gcc_ce1_axi_clk = { |
| 474 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 475 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 476 | .en_mask = BIT(1), |
| 477 | |
| 478 | .c = { |
| 479 | .dbg_name = "gcc_ce1_axi_clk", |
| 480 | .ops = &clk_ops_vote, |
| 481 | }, |
| 482 | }; |
| 483 | |
| 484 | |
| 485 | static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src = |
| 486 | { |
| 487 | .cmd_reg = (uint32_t *) GCC_BLSP1_QUP2_CMD_RCGR, |
| 488 | .cfg_reg = (uint32_t *) GCC_BLSP1_QUP2_CFG_RCGR, |
| 489 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 490 | .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src, |
| 491 | .current_freq = &rcg_dummy_freq, |
| 492 | |
| 493 | .c = { |
| 494 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 495 | .ops = &clk_ops_rcg, |
| 496 | }, |
| 497 | }; |
| 498 | |
| 499 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 500 | .cbcr_reg = GCC_BLSP1_QUP2_APPS_CBCR, |
| 501 | .parent = &gcc_blsp1_qup2_i2c_apps_clk_src.c, |
| 502 | |
| 503 | .c = { |
| 504 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 505 | .ops = &clk_ops_branch, |
| 506 | }, |
| 507 | }; |
| 508 | /* Clock lookup table */ |
| 509 | static struct clk_lookup msm_clocks_ferrum[] = |
| 510 | { |
| 511 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 512 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 513 | |
| 514 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 515 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 516 | |
| 517 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 518 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 519 | |
| 520 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 521 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 522 | |
| 523 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 524 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
| 525 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 526 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 527 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 528 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
| 529 | |
| 530 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 531 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 532 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 533 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 534 | |
| 535 | CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c), |
| 536 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c), |
| 537 | CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c), |
| 538 | }; |
| 539 | |
| 540 | void platform_clock_init(void) |
| 541 | { |
| 542 | clk_init(msm_clocks_ferrum, ARRAY_SIZE(msm_clocks_ferrum)); |
| 543 | } |