Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 30 | #include "mipi_renesas.h" |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 31 | |
| 32 | int mipi_renesas_video_fwvga_config(void *pdata) |
| 33 | { |
| 34 | int ret = NO_ERROR; |
| 35 | /* 3 Lanes -- Enables Data Lane0, 1, 2 */ |
| 36 | unsigned char lane_en = 3; |
| 37 | unsigned long low_pwr_stop_mode = 1; |
| 38 | |
| 39 | /* Needed or else will have blank line at top of display */ |
| 40 | unsigned char eof_bllp_pwr = 0x9; |
| 41 | |
| 42 | unsigned char interleav = 0; |
| 43 | struct lcdc_panel_info *lcdc = NULL; |
| 44 | struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata; |
| 45 | |
| 46 | if (pinfo == NULL) |
| 47 | return ERR_INVALID_ARGS; |
| 48 | |
| 49 | lcdc = &(pinfo->lcdc); |
| 50 | if (lcdc == NULL) |
| 51 | return ERR_INVALID_ARGS; |
| 52 | |
| 53 | ret = mipi_dsi_video_mode_config((pinfo->xres), |
| 54 | (pinfo->yres), |
| 55 | (pinfo->xres), |
| 56 | (pinfo->yres), |
| 57 | (lcdc->h_front_porch), |
| 58 | (lcdc->h_back_porch), |
| 59 | (lcdc->v_front_porch), |
| 60 | (lcdc->v_back_porch), |
| 61 | (lcdc->h_pulse_width), |
| 62 | (lcdc->v_pulse_width), |
| 63 | pinfo->mipi.dst_format, |
| 64 | pinfo->mipi.traffic_mode, |
| 65 | lane_en, |
| 66 | low_pwr_stop_mode, |
| 67 | eof_bllp_pwr, |
| 68 | interleav); |
| 69 | return ret; |
| 70 | } |
| 71 | |
| 72 | int mipi_renesas_video_fwvga_on() |
| 73 | { |
| 74 | int ret = NO_ERROR; |
| 75 | return ret; |
| 76 | } |
| 77 | |
| 78 | int mipi_renesas_video_fwvga_off() |
| 79 | { |
| 80 | int ret = NO_ERROR; |
| 81 | return ret; |
| 82 | } |
| 83 | |
| 84 | static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = { |
| 85 | /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */ |
| 86 | {0x03, 0x01, 0x01, 0x00}, /* regulator */ |
| 87 | /* timing */ |
| 88 | {0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22, |
| 89 | 0x90, 0x18, 0x03, 0x04}, |
| 90 | {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */ |
| 91 | {0xbb, 0x02, 0x06, 0x00}, /* strength */ |
| 92 | /* pll control */ |
| 93 | {0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62, |
| 94 | 0x01, 0x0f, 0x07, /* --> Two lane configuration */ |
| 95 | 0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0}, |
| 96 | }; |
| 97 | |
| 98 | void mipi_renesas_video_fwvga_init(struct msm_panel_info *pinfo) |
| 99 | { |
| 100 | if (!pinfo) |
| 101 | return; |
| 102 | |
| 103 | pinfo->xres = REN_MIPI_FB_WIDTH; |
| 104 | pinfo->yres = REN_MIPI_FB_HEIGHT; |
| 105 | pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 106 | pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 107 | pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH; |
| 108 | pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES; |
| 109 | pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 110 | pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH; |
| 111 | pinfo->mipi.num_of_lanes = 2; |
| 112 | |
| 113 | pinfo->type = MIPI_VIDEO_PANEL; |
| 114 | pinfo->wait_cycle = 0; |
| 115 | pinfo->bpp = 24; |
Channagoud Kadabi | ebbca34 | 2012-06-29 18:14:31 +0530 | [diff] [blame] | 116 | pinfo->clk_rate = 499000000; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 117 | |
| 118 | pinfo->mipi.mode = DSI_VIDEO_MODE; |
| 119 | pinfo->mipi.traffic_mode = 2; |
| 120 | pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; |
| 121 | pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db; |
| 122 | pinfo->mipi.tx_eot_append = TRUE; |
| 123 | |
| 124 | pinfo->mipi.lane_swap = 1; |
| 125 | pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds; |
| 126 | pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds); |
| 127 | |
| 128 | pinfo->on = mipi_renesas_video_fwvga_on; |
| 129 | pinfo->off = mipi_renesas_video_fwvga_off; |
| 130 | pinfo->config = mipi_renesas_video_fwvga_config; |
| 131 | |
| 132 | return; |
| 133 | } |
| 134 | |
| 135 | void mipi_renesas_video_hvga_init(struct msm_panel_info *pinfo) |
| 136 | { |
| 137 | if (!pinfo) |
| 138 | return; |
| 139 | |
| 140 | pinfo->xres = REN_MIPI_FB_WIDTH_HVGA; |
| 141 | pinfo->yres = REN_MIPI_FB_HEIGHT_HVGA; |
| 142 | pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA; |
| 143 | pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA; |
| 144 | pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA; |
| 145 | pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES_HVGA; |
| 146 | pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH_HVGA; |
| 147 | pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH_HVGA; |
| 148 | pinfo->mipi.num_of_lanes = 1; |
| 149 | |
| 150 | pinfo->type = MIPI_VIDEO_PANEL; |
| 151 | pinfo->wait_cycle = 0; |
| 152 | pinfo->bpp = 24; |
| 153 | |
| 154 | pinfo->mipi.mode = DSI_VIDEO_MODE; |
| 155 | pinfo->mipi.traffic_mode = 2; |
| 156 | pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; |
| 157 | pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db; |
| 158 | pinfo->mipi.tx_eot_append = TRUE; |
| 159 | |
| 160 | pinfo->mipi.lane_swap = 1; |
| 161 | pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds; |
| 162 | pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds); |
| 163 | |
| 164 | pinfo->on = mipi_renesas_video_fwvga_on; |
| 165 | pinfo->off = mipi_renesas_video_fwvga_off; |
| 166 | pinfo->config = mipi_renesas_video_fwvga_config; |
| 167 | |
| 168 | return; |
| 169 | } |