Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 29 | #ifndef __MSM8994_CLOCK_H |
| 30 | #define __MSM8994_CLOCK_H |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 31 | |
| 32 | #include <clock.h> |
| 33 | #include <clock_lib2.h> |
| 34 | |
| 35 | #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC |
| 36 | |
Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame^] | 37 | #define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off)) |
| 38 | |
| 39 | #define MDP_GDSCR REG_MM(0x2304) |
| 40 | #define GDSC_POWER_ON_BIT BIT(31) |
| 41 | #define GDSC_POWER_ON_STATUS_BIT BIT(29) |
| 42 | #define GDSC_EN_FEW_WAIT_MASK (0x0F << 16) |
| 43 | #define GDSC_EN_FEW_WAIT_256_MASK BIT(19) |
| 44 | |
| 45 | #define VSYNC_CMD_RCGR REG_MM(0x2080) |
| 46 | #define VSYNC_CFG_RCGR REG_MM(0x2084) |
| 47 | #define MDSS_VSYNC_CBCR REG_MM(0x2328) |
| 48 | #define MDP_CMD_RCGR REG_MM(0x2040) |
| 49 | #define MDP_CFG_RCGR REG_MM(0x2044) |
| 50 | #define MDP_CBCR REG_MM(0x231C) |
| 51 | #define MDP_LUT_CBCR REG_MM(0x2320) |
| 52 | #define MDP_AHB_CBCR REG_MM(0x2308) |
| 53 | |
| 54 | #define MDP_AXI_CMD_RCGR REG_MM(0x5040) |
| 55 | #define MDP_AXI_CFG_RCGR REG_MM(0x5044) |
| 56 | |
| 57 | #define MDP_AXI_CBCR REG_MM(0x2310) |
| 58 | #define MMSS_S0_AXI_CBCR REG_MM(0x5064) |
| 59 | #define MMSS_MMSSNOC_AXI_CBCR REG_MM(0x506C) |
| 60 | |
| 61 | #define DSI_BYTE0_CMD_RCGR REG_MM(0x2120) |
| 62 | #define DSI_BYTE0_CFG_RCGR REG_MM(0x2124) |
| 63 | #define DSI_BYTE0_CBCR REG_MM(0x233C) |
| 64 | #define DSI_ESC0_CMD_RCGR REG_MM(0x2160) |
| 65 | #define DSI_ESC0_CFG_RCGR REG_MM(0x2164) |
| 66 | #define DSI_ESC0_CBCR REG_MM(0x2344) |
| 67 | #define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000) |
| 68 | #define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004) |
| 69 | #define DSI_PIXEL0_CBCR REG_MM(0x2314) |
| 70 | #define DSI_PIXEL0_M REG_MM(0x2008) |
| 71 | #define DSI_PIXEL0_N REG_MM(0x200C) |
| 72 | #define DSI_PIXEL0_D REG_MM(0x2010) |
| 73 | |
| 74 | #define DSI0_PHY_PLL_OUT BIT(8) |
| 75 | #define PIXEL_SRC_DIV_1_5 BIT(1) |
| 76 | |
| 77 | #define DSI_BYTE1_CMD_RCGR REG_MM(0x2140) |
| 78 | #define DSI_BYTE1_CFG_RCGR REG_MM(0x2144) |
| 79 | #define DSI_BYTE1_CBCR REG_MM(0x2340) |
| 80 | #define DSI_ESC1_CMD_RCGR REG_MM(0x2180) |
| 81 | #define DSI_ESC1_CFG_RCGR REG_MM(0x2184) |
| 82 | #define DSI_ESC1_CBCR REG_MM(0x2348) |
| 83 | #define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020) |
| 84 | #define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024) |
| 85 | #define DSI_PIXEL1_CBCR REG_MM(0x2318) |
| 86 | #define DSI_PIXEL1_M REG_MM(0x2028) |
| 87 | #define DSI_PIXEL1_N REG_MM(0x202C) |
| 88 | #define DSI_PIXEL1_D REG_MM(0x2030) |
| 89 | |
| 90 | #define MDSS_EDPPIXEL_CBCR REG_MM(0x232C) |
| 91 | #define MDSS_EDPLINK_CBCR REG_MM(0x2330) |
| 92 | #define MDSS_EDPAUX_CBCR REG_MM(0x2334) |
| 93 | #define EDPPIXEL_M REG_MM(0x20A8) |
| 94 | #define EDPPIXEL_N REG_MM(0x20AC) |
| 95 | #define EDPPIXEL_D REG_MM(0x20B0) |
| 96 | #define EDPPIXEL_CFG_RCGR REG_MM(0x20A4) |
| 97 | #define EDPPIXEL_CMD_RCGR REG_MM(0x20A0) |
| 98 | #define EDPLINK_CFG_RCGR REG_MM(0x20C4) |
| 99 | #define EDPLINK_CMD_RCGR REG_MM(0x20C0) |
| 100 | #define EDPAUX_CFG_RCGR REG_MM(0x20E4) |
| 101 | #define EDPAUX_CMD_RCGR REG_MM(0x20E0) |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 102 | |
| 103 | void platform_clock_init(void); |
| 104 | |
| 105 | void clock_init_mmc(uint32_t interface); |
| 106 | void clock_config_mmc(uint32_t interface, uint32_t freq); |
| 107 | void clock_config_uart_dm(uint8_t id); |
| 108 | void hsusb_clock_init(void); |
| 109 | void clock_config_ce(uint8_t instance); |
| 110 | void mdp_clock_init(void); |
| 111 | void clock_ce_enable(uint8_t instance); |
| 112 | void clock_ce_disable(uint8_t instance); |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 113 | void clock_usb30_init(void); |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 114 | |
| 115 | #endif |