Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* Copyright 2007, Google Inc. */ |
| 2 | |
| 3 | #include <debug.h> |
| 4 | #include <dev/gpio.h> |
| 5 | #include <kernel/thread.h> |
| 6 | #include <mddi.h> |
| 7 | |
| 8 | #define MDDI_CLIENT_CORE_BASE 0x108000 |
| 9 | #define LCD_CONTROL_BLOCK_BASE 0x110000 |
| 10 | #define SPI_BLOCK_BASE 0x120000 |
| 11 | #define I2C_BLOCK_BASE 0x130000 |
| 12 | #define PWM_BLOCK_BASE 0x140000 |
| 13 | #define GPIO_BLOCK_BASE 0x150000 |
| 14 | #define SYSTEM_BLOCK1_BASE 0x160000 |
| 15 | #define SYSTEM_BLOCK2_BASE 0x170000 |
| 16 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 17 | #define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) |
| 18 | #define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) |
| 19 | #define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) |
| 20 | #define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) |
| 21 | #define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) |
| 22 | #define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) |
| 23 | #define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) |
| 24 | #define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) |
| 25 | #define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) |
| 26 | #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) |
| 27 | #define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) |
| 28 | #define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) |
| 29 | #define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) |
| 30 | #define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) |
| 31 | #define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) |
| 32 | #define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) |
| 33 | #define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) |
| 34 | #define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) |
| 35 | #define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) |
| 36 | #define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) |
| 37 | #define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) |
| 38 | #define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) |
| 39 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 40 | #define SRST (LCD_CONTROL_BLOCK_BASE|0x00) |
| 41 | #define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) |
| 42 | #define START (LCD_CONTROL_BLOCK_BASE|0x08) |
| 43 | #define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) |
| 44 | #define CMN (LCD_CONTROL_BLOCK_BASE|0x10) |
| 45 | #define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) |
| 46 | #define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) |
| 47 | #define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) |
| 48 | #define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) |
| 49 | #define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) |
| 50 | #define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) |
| 51 | |
| 52 | #define PXL (LCD_CONTROL_BLOCK_BASE|0x30) |
| 53 | #define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) |
| 54 | #define HSW (LCD_CONTROL_BLOCK_BASE|0x38) |
| 55 | #define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) |
| 56 | #define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) |
| 57 | #define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) |
| 58 | #define VSW (LCD_CONTROL_BLOCK_BASE|0x48) |
| 59 | #define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) |
| 60 | #define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) |
| 61 | #define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) |
| 62 | #define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) |
| 63 | #define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) |
| 64 | #define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) |
| 65 | #define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) |
| 66 | #define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) |
| 67 | #define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) |
| 68 | #define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) |
| 69 | #define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) |
| 70 | #define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) |
| 71 | #define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) |
| 72 | #define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) |
| 73 | #define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) |
| 74 | #define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) |
| 75 | #define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) |
| 76 | |
| 77 | #define MONI (LCD_CONTROL_BLOCK_BASE|0xB0) |
| 78 | |
| 79 | #define Current (LCD_CONTROL_BLOCK_BASE|0xC0) |
| 80 | #define LCD (LCD_CONTROL_BLOCK_BASE|0xC4) |
| 81 | #define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8) |
| 82 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 83 | #define SSICTL (SPI_BLOCK_BASE|0x00) |
| 84 | #define SSITIME (SPI_BLOCK_BASE|0x04) |
| 85 | #define SSITX (SPI_BLOCK_BASE|0x08) |
| 86 | #define SSIRX (SPI_BLOCK_BASE|0x0C) |
| 87 | #define SSIINTC (SPI_BLOCK_BASE|0x10) |
| 88 | #define SSIINTS (SPI_BLOCK_BASE|0x14) |
| 89 | #define SSIDBG1 (SPI_BLOCK_BASE|0x18) |
| 90 | #define SSIDBG2 (SPI_BLOCK_BASE|0x1C) |
| 91 | #define SSIID (SPI_BLOCK_BASE|0x20) |
| 92 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 93 | #define I2CSETUP (I2C_BLOCK_BASE|0x00) |
| 94 | #define I2CCTRL (I2C_BLOCK_BASE|0x04) |
| 95 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 96 | #define TIMER0LOAD (PWM_BLOCK_BASE|0x00) |
| 97 | #define TIMER0VALUE (PWM_BLOCK_BASE|0x04) |
| 98 | #define TIMER0CONTROL (PWM_BLOCK_BASE|0x08) |
| 99 | #define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C) |
| 100 | #define TIMER0RIS (PWM_BLOCK_BASE|0x10) |
| 101 | #define TIMER0MIS (PWM_BLOCK_BASE|0x14) |
| 102 | #define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18) |
| 103 | #define PWM0OFF (PWM_BLOCK_BASE|0x1C) |
| 104 | #define TIMER1LOAD (PWM_BLOCK_BASE|0x20) |
| 105 | #define TIMER1VALUE (PWM_BLOCK_BASE|0x24) |
| 106 | #define TIMER1CONTROL (PWM_BLOCK_BASE|0x28) |
| 107 | #define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C) |
| 108 | #define TIMER1RIS (PWM_BLOCK_BASE|0x30) |
| 109 | #define TIMER1MIS (PWM_BLOCK_BASE|0x34) |
| 110 | #define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38) |
| 111 | #define PWM1OFF (PWM_BLOCK_BASE|0x3C) |
| 112 | #define TIMERITCR (PWM_BLOCK_BASE|0x60) |
| 113 | #define TIMERITOP (PWM_BLOCK_BASE|0x64) |
| 114 | #define PWMCR (PWM_BLOCK_BASE|0x68) |
| 115 | #define PWMID (PWM_BLOCK_BASE|0x6C) |
| 116 | #define PWMMON (PWM_BLOCK_BASE|0x70) |
| 117 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 118 | #define GPIODATA (GPIO_BLOCK_BASE|0x00) |
| 119 | #define GPIODIR (GPIO_BLOCK_BASE|0x04) |
| 120 | #define GPIOIS (GPIO_BLOCK_BASE|0x08) |
| 121 | #define GPIOIBE (GPIO_BLOCK_BASE|0x0C) |
| 122 | #define GPIOIEV (GPIO_BLOCK_BASE|0x10) |
| 123 | #define GPIOIE (GPIO_BLOCK_BASE|0x14) |
| 124 | #define GPIORIS (GPIO_BLOCK_BASE|0x18) |
| 125 | #define GPIOMIS (GPIO_BLOCK_BASE|0x1C) |
| 126 | #define GPIOIC (GPIO_BLOCK_BASE|0x20) |
| 127 | #define GPIOOMS (GPIO_BLOCK_BASE|0x24) |
| 128 | #define GPIOPC (GPIO_BLOCK_BASE|0x28) |
| 129 | |
| 130 | #define GPIOID (GPIO_BLOCK_BASE|0x30) |
| 131 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 132 | #define WKREQ (SYSTEM_BLOCK1_BASE|0x00) |
| 133 | #define CLKENB (SYSTEM_BLOCK1_BASE|0x04) |
| 134 | #define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) |
| 135 | #define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) |
| 136 | #define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) |
| 137 | |
| 138 | struct init_table { |
| 139 | unsigned int reg; |
| 140 | unsigned int val; |
| 141 | }; |
| 142 | |
| 143 | static struct init_table toshiba_480x640_init_table[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 144 | {DPSET0, 0x4BEC0066}, // # MDC.DPSET0 # Setup DPLL parameters |
| 145 | {DPSET1, 0x00000113}, // # MDC.DPSET1 |
| 146 | {DPSUS, 0x00000000}, // # MDC.DPSUS # Set DPLL oscillation enable |
| 147 | {DPRUN, 0x00000001}, // # MDC.DPRUN # Release reset signal for DPLL |
| 148 | {0, 14}, // wait_ms(14); |
| 149 | {SYSCKENA, 0x00000001}, // # MDC.SYSCKENA # Enable system clock output |
| 150 | {CLKENB, 0x000000EF}, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) |
| 151 | {GPIO_BLOCK_BASE, 0x03FF0000}, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 |
| 152 | {GPIODIR, 0x0000024D}, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) |
| 153 | {SYSTEM_BLOCK2_BASE, 0x00000173}, // # SYS.GPIOSEL # GPIO port multiplexing control |
| 154 | {GPIOPC, 0x03C300C0}, // # GPI .GPIOPC # GPIO2,3 PD cut |
| 155 | {SYSTEM_BLOCK1_BASE, 0x00000000}, // # SYS.WKREQ # Wake-up request event is VSYNC alignment |
| 156 | {GPIOIS, 0x00000000}, // # GPI .GPIOIS # Set interrupt sense of GPIO |
| 157 | {GPIOIEV, 0x00000001}, // # GPI .GPIOIEV # Set interrupt event of GPIO |
| 158 | {GPIOIC, 0x000003FF}, // # GPI .GPIOIC # GPIO interrupt clear |
| 159 | {GPIO_BLOCK_BASE, 0x00060006}, // # GPI .GPIODATA # Release LCDD reset |
| 160 | {GPIO_BLOCK_BASE, 0x00080008}, // # GPI .GPIODATA # eDRAM VD supply |
| 161 | {GPIO_BLOCK_BASE, 0x02000200}, // # GPI .GPIODATA # TEST LED ON |
| 162 | {DRAMPWR, 0x00000001}, // # SYS.DRAMPWR # eDRAM power up |
| 163 | {TIMER0CONTROL, 0x00000060}, // # PWM.Timer0Control # PWM0 output stop |
| 164 | {PWM_BLOCK_BASE, 0x00001388}, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF) |
| 165 | //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 166 | #if 0 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 167 | {PWM0OFF, 0x00001387}, // SURF 100% backlight |
| 168 | {PWM0OFF, 0x00000000}, // FFA 100% backlight |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 169 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 170 | {PWM0OFF, 0x000009C3}, // 50% BL |
| 171 | {TIMER1CONTROL, 0x00000060}, // # PWM.Timer1Control # PWM1 output stop |
| 172 | {TIMER1LOAD, 0x00001388}, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF) |
| 173 | //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF |
| 174 | {PWM1OFF, 0x00001387}, |
| 175 | {TIMER0CONTROL, 0x000000E0}, // # PWM.Timer0Control # PWM0 output start |
| 176 | {TIMER1CONTROL, 0x000000E0}, // # PWM.Timer1Control # PWM1 output start |
| 177 | {PWMCR, 0x00000003}, // # PWM.PWMCR # PWM output enable |
| 178 | {0, 1}, // wait_ms(1); |
| 179 | {SPI_BLOCK_BASE, 0x00000799}, // # SPI .SSICTL # SPI operation mode setting |
| 180 | {SSITIME, 0x00000100}, // # SPI .SSITIME # SPI serial interface timing setting |
| 181 | {SPI_BLOCK_BASE, 0x0000079b}, // # SPI .SSICTL # Set SPI active mode |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 182 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 183 | {SSITX, 0x00000000}, // # SPI.SSITX # Release from Deep Stanby mode |
| 184 | {0, 1}, // wait_ms(1); |
| 185 | {SSITX, 0x00000000}, // # SPI.SSITX |
| 186 | {0, 1}, // wait_ms(1); |
| 187 | {SSITX, 0x00000000}, // # SPI.SSITX |
| 188 | {0, 1}, // wait_ms(1); |
| 189 | {SSITX, 0x000800BA}, // # SPI.SSITX *NOTE 1 # Command setting of SPI block |
| 190 | {SSITX, 0x00000111}, // # Display mode setup(1) : Normaly Black |
| 191 | {SSITX, 0x00080036}, // # Command setting of SPI block |
| 192 | {SSITX, 0x00000100}, // # Memory access control |
| 193 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 194 | {SSITX, 0x000800BB}, // # Command setting of SPI block |
| 195 | {SSITX, 0x00000100}, // # Display mode setup(2) |
| 196 | {SSITX, 0x0008003A}, // # Command setting of SPI block |
| 197 | {SSITX, 0x00000160}, // # RGB Interface data format |
| 198 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 199 | {SSITX, 0x000800BF}, // # Command setting of SPI block |
| 200 | {SSITX, 0x00000100}, // # Drivnig method |
| 201 | {SSITX, 0x000800B1}, // # Command setting of SPI block |
| 202 | {SSITX, 0x0000015D}, // # Booster operation setup |
| 203 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 204 | {SSITX, 0x000800B2}, // # Command setting of SPI block |
| 205 | {SSITX, 0x00000133}, // # Booster mode setup |
| 206 | {SSITX, 0x000800B3}, // # Command setting of SPI block |
| 207 | {SSITX, 0x00000122}, // # Booster frequencies setup |
| 208 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 209 | {SSITX, 0x000800B4}, // # Command setting of SPI block |
| 210 | {SSITX, 0x00000102}, // # OP-amp capability/System clock freq. division setup |
| 211 | {SSITX, 0x000800B5}, // # Command setting of SPI block |
| 212 | {SSITX, 0x0000011F}, // # VCS Voltage adjustment (1C->1F for Rev 2) |
| 213 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 214 | {SSITX, 0x000800B6}, // # Command setting of SPI block |
| 215 | {SSITX, 0x00000128}, // # VCOM Voltage adjustment |
| 216 | {SSITX, 0x000800B7}, // # Command setting of SPI block |
| 217 | {SSITX, 0x00000103}, // # Configure an external display signal |
| 218 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 219 | {SSITX, 0x000800B9}, // # Command setting of SPI block |
| 220 | {SSITX, 0x00000120}, // # DCCK/DCEV timing setup |
| 221 | {SSITX, 0x000800BD}, // # Command setting of SPI block |
| 222 | {SSITX, 0x00000102}, // # ASW signal control |
| 223 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 224 | {SSITX, 0x000800BE}, // # Command setting of SPI block |
| 225 | {SSITX, 0x00000100}, // # Dummy display (white/black) count setup for QUAD Data operation |
| 226 | {SSITX, 0x000800C0}, // # Command setting of SPI block |
| 227 | {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (A) |
| 228 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 229 | {SSITX, 0x000800C1}, // # Command setting of SPI block |
| 230 | {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (B) |
| 231 | {SSITX, 0x000800C2}, // # Command setting of SPI block |
| 232 | {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (C) |
| 233 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 234 | {SSITX, 0x000800C3}, // # Command setting of SPI block |
| 235 | {SSITX, 0x0008010A}, // # wait_ms(-in line clock count setup (D) |
| 236 | {SSITX, 0x0000010A}, // |
| 237 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 238 | {SSITX, 0x000800C4}, // # Command setting of SPI block |
| 239 | {SSITX, 0x00080160}, // # Seep-in line clock count setup (E) |
| 240 | {SSITX, 0x00000160}, // |
| 241 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 242 | {SSITX, 0x000800C5}, // # Command setting of SPI block |
| 243 | {SSITX, 0x00080160}, // # wait_ms(-in line clock count setup (F) |
| 244 | {SSITX, 0x00000160}, // |
| 245 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 246 | {SSITX, 0x000800C6}, // # Command setting of SPI block |
| 247 | {SSITX, 0x00080160}, // # wait_ms(-in line clock setup (G) |
| 248 | {SSITX, 0x00000160}, // |
| 249 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 250 | {SSITX, 0x000800C7}, // # Command setting of SPI block |
| 251 | {SSITX, 0x00080133}, // # Gamma 1 fine tuning (1) |
| 252 | {SSITX, 0x00000143}, // |
| 253 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 254 | {SSITX, 0x000800C8}, // # Command setting of SPI block |
| 255 | {SSITX, 0x00000144}, // # Gamma 1 fine tuning (2) |
| 256 | {SSITX, 0x000800C9}, // # Command setting of SPI block |
| 257 | {SSITX, 0x00000133}, // # Gamma 1 inclination adjustment |
| 258 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 259 | {SSITX, 0x000800CA}, // # Command setting of SPI block |
| 260 | {SSITX, 0x00000100}, // # Gamma 1 blue offset adjustment |
| 261 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 262 | {SSITX, 0x000800EC}, // # Command setting of SPI block |
| 263 | {SSITX, 0x00080102}, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting] |
| 264 | {SSITX, 0x00000118}, // |
| 265 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 266 | {SSITX, 0x000800CF}, // # Command setting of SPI block |
| 267 | {SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table1 for VGA] |
| 268 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 269 | {SSITX, 0x000800D0}, // # Command setting of SPI block |
| 270 | {SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table1 for VGA] |
| 271 | {SSITX, 0x00000104}, // |
| 272 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 273 | {SSITX, 0x000800D1}, // # Command setting of SPI block |
| 274 | {SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table1 for VGA] |
| 275 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 276 | {SSITX, 0x000800D2}, // # Command setting of SPI block |
| 277 | {SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA] |
| 278 | {SSITX, 0x0000013A}, // |
| 279 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 280 | {SSITX, 0x000800D3}, // # Command setting of SPI block |
| 281 | {SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table1 for VGA] |
| 282 | {SSITX, 0x0000013A}, // |
| 283 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 284 | {SSITX, 0x000800D4}, // # Command setting of SPI block |
| 285 | {SSITX, 0x00080124}, // # ASW timing control (1) [PCLK Sync. Table1 for VGA] |
| 286 | {SSITX, 0x0000016E}, // |
| 287 | {0, 1}, // wait_ms(1); // # Wait SPI fifo empty |
| 288 | {SSITX, 0x000800D5}, // # Command setting of SPI block |
| 289 | {SSITX, 0x00000124}, // # ASW timing control (2) [PCLK Sync. Table1 for VGA] |
| 290 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 291 | {SSITX, 0x000800ED}, // # Command setting of SPI block |
| 292 | {SSITX, 0x00080101}, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ] |
| 293 | {SSITX, 0x0000010A}, // |
| 294 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 295 | {SSITX, 0x000800D6}, // # Command setting of SPI block |
| 296 | {SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA] |
| 297 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 298 | {SSITX, 0x000800D7}, // # Command setting of SPI block |
| 299 | {SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA] |
| 300 | {SSITX, 0x0000010A}, // |
| 301 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 302 | {SSITX, 0x000800D8}, // # Command setting of SPI block |
| 303 | {SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA] |
| 304 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 305 | {SSITX, 0x000800D9}, // # Command setting of SPI block |
| 306 | {SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA] |
| 307 | {SSITX, 0x00000114}, // |
| 308 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 309 | {SSITX, 0x000800DE}, // # Command setting of SPI block |
| 310 | {SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table2 for QVGA] |
| 311 | {SSITX, 0x00000114}, // |
| 312 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 313 | {SSITX, 0x000800DF}, // # Command setting of SPI block |
| 314 | {SSITX, 0x00080112}, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA] |
| 315 | {SSITX, 0x0000013F}, // |
| 316 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 317 | {SSITX, 0x000800E0}, // # Command setting of SPI block |
| 318 | {SSITX, 0x0000010B}, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA] |
| 319 | {SSITX, 0x000800E2}, // # Command setting of SPI block |
| 320 | {SSITX, 0x00000101}, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq) |
| 321 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 322 | {SSITX, 0x000800E3}, // # Command setting of SPI block |
| 323 | {SSITX, 0x00000136}, // # Built-in oscillator clock count setup |
| 324 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 325 | {SSITX, 0x000800E4}, // # Command setting of SPI block |
| 326 | {SSITX, 0x00080100}, // # CKV timing control for using build-in osc |
| 327 | {SSITX, 0x00000103}, // |
| 328 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 329 | {SSITX, 0x000800E5}, // # Command setting of SPI block |
| 330 | {SSITX, 0x00080102}, // # OEV timing control for using build-in osc |
| 331 | {SSITX, 0x00000104}, // |
| 332 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 333 | {SSITX, 0x000800E6}, // # Command setting of SPI block |
| 334 | {SSITX, 0x00000103}, // # DCEV timing control for using build-in osc |
| 335 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 336 | {SSITX, 0x000800E7}, // # Command setting of SPI block |
| 337 | {SSITX, 0x00080104}, // # ASW timing setup for using build-in osc(1) |
| 338 | {SSITX, 0x0000010A}, // |
| 339 | {0, 2}, // wait_ms(2); // # Wait SPI fifo empty |
| 340 | {SSITX, 0x000800E8}, // # Command setting of SPI block |
| 341 | {SSITX, 0x00000104}, // # ASW timing setup for using build-in osc(2) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 342 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 343 | {CLKENB, 0x000001EF}, // # SYS.CLKENB # DCLK enable |
| 344 | {START, 0x00000000}, // # LCD.START # LCDC wait_ms( mode |
| 345 | {WRSTB, 0x0000003F}, // # LCD.WRSTB # write_client_reg( strobe |
| 346 | {RDSTB, 0x00000432}, // # LCD.RDSTB # Read strobe |
| 347 | {PORT_ENB, 0x00000002}, // # LCD.PORT_ENB # Asynchronous port enable |
| 348 | {VSYNIF, 0x00000000}, // # LCD.VSYNCIF # VSYNC I/F mode set |
| 349 | {ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # Index setting of SUB LCDD |
| 350 | {ASY_DATB, 0x00000001}, // # Oscillator start |
| 351 | {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable |
| 352 | {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable |
| 353 | {0, 10}, // wait_ms(10); |
| 354 | {ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2 |
| 355 | {ASY_DATB, 0x80000000}, // |
| 356 | {ASY_DATC, 0x80000000}, // |
| 357 | {ASY_DATD, 0x80000000}, // |
| 358 | {ASY_CMDSET, 0x00000009}, // # LCD.ASY_CMDSET |
| 359 | {ASY_CMDSET, 0x00000008}, // # LCD.ASY_CMDSET |
| 360 | {ASY_DATA, 0x80000007}, // # LCD.ASY_DATx # Index setting of SUB LCDD |
| 361 | {ASY_DATB, 0x00004005}, // # LCD driver control |
| 362 | {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable |
| 363 | {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable |
| 364 | {0, 20}, // wait_ms(20); |
| 365 | {ASY_DATA, 0x80000059}, // # LCD.ASY_DATx # Index setting of SUB LCDD |
| 366 | {ASY_DATB, 0x00000000}, // # LTPS I/F control |
| 367 | {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable |
| 368 | {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 369 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 370 | {VSYNIF, 0x00000001}, // # LCD.VSYNCIF # VSYNC I/F mode OFF |
| 371 | {PORT_ENB, 0x00000001}, // # LCD.PORT_ENB # SYNC I/F output select |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 372 | |
| 373 | /******************************/ |
| 374 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 375 | {VSYNIF, 0x00000001}, // VSYNC I/F mode OFF |
| 376 | {PORT_ENB, 0x00000001}, // SYNC I/F mode ON |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 377 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 378 | {BITMAP1, 0x01E000F0}, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1 |
| 379 | {BITMAP2, 0x01E000F0}, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2 |
| 380 | {BITMAP3, 0x01E000F0}, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3 |
| 381 | {BITMAP4, 0x00DC00B0}, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4 |
| 382 | {CLKENB, 0x000001EF}, // SYS.CLKENB ); // DCLK supply |
| 383 | {PORT_ENB, 0x00000001}, // LCD.PORT_ENB ); // Synchronous port enable |
| 384 | {PORT, 0x00000004}, // LCD.PORT ); // Polarity of DE is set to high active |
| 385 | {PXL, 0x00000002}, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output) |
| 386 | {MPLFBUF, 0x00000000}, // LCD.MPLFBUF ); // Select the reading buffer |
| 387 | {HCYCLE, 0x0000010b}, // LCD.HCYCLE ); // Setup to VGA size |
| 388 | {HSW, 0x00000003}, // LCD.HSW |
| 389 | {HDE_START, 0x00000007}, // LCD.HDE_START |
| 390 | {HDE_SIZE, 0x000000EF}, // LCD.HDE_SIZE |
| 391 | {VCYCLE, 0x00000285}, // LCD.VCYCLE |
| 392 | {VSW, 0x00000001}, // LCD.VSW |
| 393 | {VDE_START, 0x00000003}, // LCD.VDE_START |
| 394 | {VDE_SIZE, 0x0000027F}, // LCD.VDE_SIZE |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 395 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 396 | {START, 0x00000001}, // LCD.START ); // LCDC - Pixel data transfer start |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 397 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 398 | {0, 10}, // wait_ms( 10 ); |
| 399 | {SSITX, 0x000800BC}, // SPI.SSITX ); // Command setting of SPI block |
| 400 | {SSITX, 0x00000180}, // Display data setup |
| 401 | {SSITX, 0x0008003B}, // Command setting of SPI block |
| 402 | {SSITX, 0x00000100}, // Quad Data configuration - VGA |
| 403 | {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty |
| 404 | {SSITX, 0x000800B0}, // Command setting of SPI block |
| 405 | {SSITX, 0x00000116}, // Power supply ON/OFF control |
| 406 | {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty |
| 407 | {SSITX, 0x000800B8}, // Command setting of SPI block |
| 408 | {SSITX, 0x000801FF}, // Output control |
| 409 | {SSITX, 0x000001F5}, |
| 410 | {0, 1}, // wait_ms( 1); // Wait SPI fifo empty |
| 411 | {SSITX, 0x00000011}, // wait_ms(-out (Command only) |
| 412 | {SSITX, 0x00000029}, // Display on (Command only) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 413 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 414 | {SYSTEM_BLOCK1_BASE, 0x00000002}, // # wakeREQ -> GPIO |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 415 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 416 | {0, 0} |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 417 | }; |
| 418 | |
| 419 | static void _panel_init(struct init_table *init_table) |
| 420 | { |
| 421 | unsigned n; |
| 422 | |
| 423 | dprintf(INFO, "panel_init()\n"); |
| 424 | |
| 425 | n = 0; |
| 426 | while (init_table[n].reg != 0 || init_table[n].val != 0) { |
| 427 | if (init_table[n].reg != 0) |
| 428 | mddi_remote_write(init_table[n].val, init_table[n].reg); |
| 429 | else |
| 430 | mdelay(init_table[n].val); |
| 431 | n++; |
| 432 | } |
| 433 | |
| 434 | dprintf(INFO, "panel_init() done\n"); |
| 435 | } |
| 436 | |
| 437 | void panel_init(struct mddi_client_caps *client_caps) |
| 438 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 439 | switch (client_caps->manufacturer_name) { |
| 440 | case 0xd263: // Toshiba |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 441 | dprintf(INFO, "Found Toshiba panel\n"); |
| 442 | _panel_init(toshiba_480x640_init_table); |
| 443 | break; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 444 | case 0x4474: //?? |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 445 | if (client_caps->product_code == 0xc065) |
| 446 | dprintf(INFO, "Found WVGA panel\n"); |
| 447 | break; |
| 448 | } |
| 449 | } |
| 450 | |
| 451 | void panel_poweron(void) |
| 452 | { |
| 453 | gpio_set(88, 0); |
| 454 | gpio_config(88, GPIO_OUTPUT); |
| 455 | udelay(10); |
| 456 | gpio_set(88, 1); |
| 457 | mdelay(10); |
| 458 | |
| 459 | //mdelay(1000); // uncomment for second stage boot |
| 460 | } |
| 461 | |
| 462 | void panel_backlight(int on) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 463 | { |
| 464 | } |