Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * QUP driver for Qualcomm MSM platforms |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include <debug.h> |
| 35 | #include <arch/arm.h> |
| 36 | #include <reg.h> |
| 37 | #include <kernel/thread.h> |
| 38 | |
| 39 | #include <i2c_qup.h> |
| 40 | #include <platform/irqs.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <platform/gpio_hw.h> |
| 43 | |
| 44 | static struct qup_i2c_dev *dev_addr = NULL; |
| 45 | |
| 46 | /* QUP Registers */ |
| 47 | enum { |
| 48 | QUP_CONFIG = 0x0, |
| 49 | QUP_STATE = 0x4, |
| 50 | QUP_IO_MODE = 0x8, |
| 51 | QUP_SW_RESET = 0xC, |
| 52 | QUP_OPERATIONAL = 0x18, |
| 53 | QUP_ERROR_FLAGS = 0x1C, |
| 54 | QUP_ERROR_FLAGS_EN = 0x20, |
| 55 | QUP_MX_READ_CNT = 0x208, |
| 56 | QUP_MX_INPUT_CNT = 0x200, |
| 57 | QUP_MX_WR_CNT = 0x100, |
| 58 | QUP_OUT_DEBUG = 0x108, |
| 59 | QUP_OUT_FIFO_CNT = 0x10C, |
| 60 | QUP_OUT_FIFO_BASE = 0x110, |
| 61 | QUP_IN_READ_CUR = 0x20C, |
| 62 | QUP_IN_DEBUG = 0x210, |
| 63 | QUP_IN_FIFO_CNT = 0x214, |
| 64 | QUP_IN_FIFO_BASE = 0x218, |
| 65 | QUP_I2C_CLK_CTL = 0x400, |
| 66 | QUP_I2C_STATUS = 0x404, |
| 67 | }; |
| 68 | |
| 69 | /* QUP States and reset values */ |
| 70 | enum { |
| 71 | QUP_RESET_STATE = 0, |
| 72 | QUP_RUN_STATE = 1U, |
| 73 | QUP_STATE_MASK = 3U, |
| 74 | QUP_PAUSE_STATE = 3U, |
| 75 | QUP_STATE_VALID = 1U << 2, |
| 76 | QUP_I2C_MAST_GEN = 1U << 4, |
| 77 | QUP_OPERATIONAL_RESET = 0xFF0, |
| 78 | QUP_I2C_STATUS_RESET = 0xFFFFFC, |
| 79 | }; |
| 80 | |
| 81 | /* QUP OPERATIONAL FLAGS */ |
| 82 | enum { |
| 83 | QUP_OUT_SVC_FLAG = 1U << 8, |
| 84 | QUP_IN_SVC_FLAG = 1U << 9, |
| 85 | QUP_MX_INPUT_DONE = 1U << 11, |
| 86 | }; |
| 87 | |
| 88 | /* I2C mini core related values */ |
| 89 | enum { |
| 90 | I2C_MINI_CORE = 2U << 8, |
| 91 | I2C_N_VAL = 0xF, |
| 92 | |
| 93 | }; |
| 94 | |
| 95 | /* Packing Unpacking words in FIFOs , and IO modes*/ |
| 96 | enum { |
| 97 | QUP_WR_BLK_MODE = 1U << 10, |
| 98 | QUP_RD_BLK_MODE = 1U << 12, |
| 99 | QUP_UNPACK_EN = 1U << 14, |
| 100 | QUP_PACK_EN = 1U << 15, |
| 101 | }; |
| 102 | |
| 103 | /* QUP tags */ |
| 104 | enum { |
| 105 | QUP_OUT_NOP = 0, |
| 106 | QUP_OUT_START = 1U << 8, |
| 107 | QUP_OUT_DATA = 2U << 8, |
| 108 | QUP_OUT_STOP = 3U << 8, |
| 109 | QUP_OUT_REC = 4U << 8, |
| 110 | QUP_IN_DATA = 5U << 8, |
| 111 | QUP_IN_STOP = 6U << 8, |
| 112 | QUP_IN_NACK = 7U << 8, |
| 113 | }; |
| 114 | |
| 115 | /* Status, Error flags */ |
| 116 | enum { |
| 117 | I2C_STATUS_WR_BUFFER_FULL = 1U << 0, |
| 118 | I2C_STATUS_BUS_ACTIVE = 1U << 8, |
| 119 | I2C_STATUS_ERROR_MASK = 0x38000FC, |
| 120 | QUP_I2C_NACK_FLAG = 1U << 3, |
| 121 | QUP_IN_NOT_EMPTY = 1U << 5, |
| 122 | QUP_STATUS_ERROR_FLAGS = 0x7C, |
| 123 | }; |
| 124 | |
| 125 | void set_i2c_clk(struct qup_i2c_dev *dev) |
| 126 | { |
| 127 | uint32_t md = 0; |
| 128 | uint32_t ns = 0; |
| 129 | |
| 130 | switch (dev->src_clk_freq) { |
| 131 | case 24000000: |
| 132 | ns = I2C_APPS_CLK_NS_24MHz; |
| 133 | md = I2C_APPS_CLK_MD_24MHz; |
| 134 | break; |
| 135 | default: |
| 136 | return; |
| 137 | } |
| 138 | /* Enable the GSBI8 HCLK */ |
| 139 | writel((GSBI8_HCLK_CTL_CLK_ENA << GSBI8_HCLK_CTL_S), |
| 140 | GSBIn_HCLK_CTL(dev->gsbi_number)); |
| 141 | clock_config(ns, |
| 142 | md, |
| 143 | GSBIn_QUP_APPS_NS(dev->gsbi_number), |
| 144 | GSBIn_QUP_APPS_MD(dev->gsbi_number)); |
| 145 | } |
| 146 | |
| 147 | void i2c_gpio_cfg(uint32_t base) |
| 148 | { |
| 149 | switch (base) { |
| 150 | case GSBI8_BASE: |
| 151 | gpio_tlmm_config(64, 1, GPIO_OUTPUT, GPIO_NO_PULL, |
| 152 | GPIO_2MA, GPIO_DISABLE); |
| 153 | gpio_tlmm_config(65, 1, GPIO_OUTPUT, GPIO_NO_PULL, |
| 154 | GPIO_2MA, GPIO_DISABLE); |
| 155 | break; |
| 156 | default: |
| 157 | break; |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | #ifdef DEBUG |
| 162 | static void qup_print_status(struct qup_i2c_dev *dev) |
| 163 | { |
| 164 | unsigned val; |
| 165 | val = readl(dev->base + QUP_CONFIG); |
| 166 | dprintf(INFO, "Qup config is :0x%x\n", val); |
| 167 | val = readl(dev->base + QUP_STATE); |
| 168 | dprintf(INFO, "Qup state is :0x%x\n", val); |
| 169 | val = readl(dev->base + QUP_IO_MODE); |
| 170 | dprintf(INFO, "Qup mode is :0x%x\n", val); |
| 171 | } |
| 172 | #else |
| 173 | static inline void qup_print_status(struct qup_i2c_dev *dev) |
| 174 | { |
| 175 | } |
| 176 | #endif |
| 177 | |
| 178 | void i2c_gpio_cfg(unsigned base); |
| 179 | |
| 180 | static irqreturn_t qup_i2c_interrupt(void) |
| 181 | { |
| 182 | struct qup_i2c_dev *dev = dev_addr; |
| 183 | if (!dev) { |
| 184 | dprintf(CRITICAL, |
| 185 | "dev_addr is NULL, that means i2c_qup_init failed...\n"); |
| 186 | return IRQ_FAIL; |
| 187 | } |
| 188 | unsigned status = readl(dev->base + QUP_I2C_STATUS); |
| 189 | unsigned status1 = readl(dev->base + QUP_ERROR_FLAGS); |
| 190 | unsigned op_flgs = readl(dev->base + QUP_OPERATIONAL); |
| 191 | int err = 0; |
| 192 | |
| 193 | if (!dev->msg) |
| 194 | return IRQ_HANDLED; |
| 195 | |
| 196 | if (status & I2C_STATUS_ERROR_MASK) { |
| 197 | dprintf(CRITICAL, "QUP: I2C status flags :0x%x \n", status); |
| 198 | err = -status; |
| 199 | /* Clear Error interrupt if it's a level triggered interrupt */ |
| 200 | if (dev->num_irqs == 1) { |
| 201 | writel(QUP_RESET_STATE, dev->base + QUP_STATE); |
| 202 | } |
| 203 | goto intr_done; |
| 204 | } |
| 205 | |
| 206 | if (status1 & 0x7F) { |
| 207 | dprintf(CRITICAL, "QUP: QUP status flags :0x%x\n", status1); |
| 208 | err = -status1; |
| 209 | /* Clear Error interrupt if it's a level triggered interrupt */ |
| 210 | if (dev->num_irqs == 1) |
| 211 | writel((status1 & QUP_STATUS_ERROR_FLAGS), |
| 212 | dev->base + QUP_ERROR_FLAGS); |
| 213 | goto intr_done; |
| 214 | } |
| 215 | |
| 216 | if (op_flgs & QUP_OUT_SVC_FLAG) |
| 217 | writel(QUP_OUT_SVC_FLAG, dev->base + QUP_OPERATIONAL); |
| 218 | if (dev->msg->flags == I2C_M_RD) { |
| 219 | if ((op_flgs & QUP_MX_INPUT_DONE) || (op_flgs & QUP_IN_SVC_FLAG)) |
| 220 | writel(QUP_IN_SVC_FLAG, dev->base + QUP_OPERATIONAL); |
| 221 | else |
| 222 | return IRQ_HANDLED; |
| 223 | } |
| 224 | |
| 225 | intr_done: |
| 226 | dev->err = err; |
| 227 | return IRQ_HANDLED; |
| 228 | } |
| 229 | |
| 230 | static int qup_i2c_poll_writeready(struct qup_i2c_dev *dev) |
| 231 | { |
| 232 | unsigned retries = 0; |
| 233 | |
| 234 | while (retries != 2000) { |
| 235 | unsigned status = readl(dev->base + QUP_I2C_STATUS); |
| 236 | |
| 237 | if (!(status & I2C_STATUS_WR_BUFFER_FULL)) { |
| 238 | if (!(status & I2C_STATUS_BUS_ACTIVE)) |
| 239 | return 0; |
| 240 | else /* 1-bit delay before we check for bus busy */ |
| 241 | udelay(dev->one_bit_t); |
| 242 | } |
| 243 | if (retries++ == 1000) |
| 244 | udelay(100); |
| 245 | } |
| 246 | qup_print_status(dev); |
| 247 | return -ETIMEDOUT; |
| 248 | } |
| 249 | |
| 250 | static int qup_i2c_poll_state(struct qup_i2c_dev *dev, unsigned state) |
| 251 | { |
| 252 | unsigned retries = 0; |
| 253 | |
| 254 | dprintf(CRITICAL, "Polling Status for state:0x%x\n", state); |
| 255 | |
| 256 | while (retries != 2000) { |
| 257 | unsigned status = readl(dev->base + QUP_STATE); |
| 258 | |
| 259 | if ((status & (QUP_STATE_VALID | state)) == (QUP_STATE_VALID | state)) |
| 260 | return 0; |
| 261 | else if (retries++ == 1000) |
| 262 | udelay(100); |
| 263 | } |
| 264 | return -ETIMEDOUT; |
| 265 | } |
| 266 | |
| 267 | #ifdef DEBUG |
| 268 | static void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val, |
| 269 | unsigned addr, int rdwr) |
| 270 | { |
| 271 | if (rdwr) |
| 272 | dprintf(INFO, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr); |
| 273 | else |
| 274 | dprintf(INFO, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr); |
| 275 | } |
| 276 | #else |
| 277 | static inline void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val, |
| 278 | unsigned addr, int rdwr) |
| 279 | { |
| 280 | } |
| 281 | #endif |
| 282 | |
| 283 | static void |
| 284 | qup_issue_read(struct qup_i2c_dev *dev, struct i2c_msg *msg, int *idx, |
| 285 | unsigned carry_over) |
| 286 | { |
| 287 | uint16_t addr = (msg->addr << 1) | 1; |
| 288 | /* QUP limit 256 bytes per read. By HW design, 0 in the 8-bit field is |
| 289 | treated as 256 byte read. */ |
| 290 | uint16_t rd_len = ((dev->cnt == 256) ? 0 : dev->cnt); |
| 291 | |
| 292 | if (*idx % 4) { |
| 293 | writel(carry_over | ((QUP_OUT_START | addr) << 16), |
| 294 | dev->base + QUP_OUT_FIFO_BASE); |
| 295 | |
| 296 | qup_verify_fifo(dev, carry_over | |
| 297 | ((QUP_OUT_START | addr) << 16), (unsigned)dev->base |
| 298 | + QUP_OUT_FIFO_BASE + (*idx - 2), 1); |
| 299 | writel((QUP_OUT_REC | rd_len), dev->base + QUP_OUT_FIFO_BASE); |
| 300 | |
| 301 | qup_verify_fifo(dev, (QUP_OUT_REC | rd_len), |
| 302 | (unsigned)dev->base + QUP_OUT_FIFO_BASE + (*idx + 2), |
| 303 | 1); |
| 304 | } else { |
| 305 | writel(((QUP_OUT_REC | rd_len) << 16) | |
| 306 | QUP_OUT_START | addr, dev->base + QUP_OUT_FIFO_BASE); |
| 307 | |
| 308 | qup_verify_fifo(dev, QUP_OUT_REC << 16 | rd_len << 16 | |
| 309 | QUP_OUT_START | addr, |
| 310 | (unsigned)dev->base + QUP_OUT_FIFO_BASE + (*idx), 1); |
| 311 | } |
| 312 | *idx += 4; |
| 313 | } |
| 314 | |
| 315 | static void |
| 316 | qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem, |
| 317 | int *idx, unsigned *carry_over) |
| 318 | { |
| 319 | int entries = dev->cnt; |
| 320 | int empty_sl = dev->wr_sz - ((*idx) >> 1); |
| 321 | int i = 0; |
| 322 | unsigned val = 0; |
| 323 | unsigned last_entry = 0; |
| 324 | uint16_t addr = msg->addr << 1; |
| 325 | |
| 326 | if (dev->pos == 0) { |
| 327 | if (*idx % 4) { |
| 328 | writel(*carry_over | ((QUP_OUT_START | addr) << 16), |
| 329 | dev->base + QUP_OUT_FIFO_BASE); |
| 330 | |
| 331 | qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 | |
| 332 | addr << 16, (unsigned)dev->base + |
| 333 | QUP_OUT_FIFO_BASE + (*idx) - 2, 0); |
| 334 | } else |
| 335 | val = QUP_OUT_START | addr; |
| 336 | *idx += 2; |
| 337 | i++; |
| 338 | entries++; |
| 339 | } else { |
| 340 | /* Avoid setp time issue by adding 1 NOP when number of bytes are more |
| 341 | than FIFO/BLOCK size. setup time issue can't appear otherwise since |
| 342 | next byte to be written will always be ready */ |
| 343 | val = (QUP_OUT_NOP | 1); |
| 344 | *idx += 2; |
| 345 | i++; |
| 346 | entries++; |
| 347 | } |
| 348 | if (entries > empty_sl) |
| 349 | entries = empty_sl; |
| 350 | |
| 351 | for (; i < (entries - 1); i++) { |
| 352 | if (*idx % 4) { |
| 353 | writel(val | ((QUP_OUT_DATA | |
| 354 | msg->buf[dev->pos]) << 16), |
| 355 | dev->base + QUP_OUT_FIFO_BASE); |
| 356 | |
| 357 | qup_verify_fifo(dev, val | QUP_OUT_DATA << 16 | |
| 358 | msg->buf[dev->pos] << 16, (unsigned)dev->base + |
| 359 | QUP_OUT_FIFO_BASE + (*idx) - 2, 0); |
| 360 | } else |
| 361 | val = QUP_OUT_DATA | msg->buf[dev->pos]; |
| 362 | (*idx) += 2; |
| 363 | dev->pos++; |
| 364 | } |
| 365 | if (dev->pos < (msg->len - 1)) |
| 366 | last_entry = QUP_OUT_DATA; |
| 367 | else if (rem > 1) /* not last array entry */ |
| 368 | last_entry = QUP_OUT_DATA; |
| 369 | else |
| 370 | last_entry = QUP_OUT_STOP; |
| 371 | if ((*idx % 4) == 0) { |
| 372 | /* |
| 373 | * If read-start and read-command end up in different fifos, it |
| 374 | * may result in extra-byte being read due to extra-read cycle. |
| 375 | * Avoid that by inserting NOP as the last entry of fifo only |
| 376 | * if write command(s) leave 1 space in fifo. |
| 377 | */ |
| 378 | if (rem > 1) { |
| 379 | struct i2c_msg *next = msg + 1; |
| 380 | if (next->addr == msg->addr && (next->flags | I2C_M_RD) |
| 381 | && *idx == ((dev->wr_sz * 2) - 4)) { |
| 382 | writel(((last_entry | msg->buf[dev->pos]) | |
| 383 | ((1 | QUP_OUT_NOP) << 16)), |
| 384 | dev->base + QUP_OUT_FIFO_BASE); |
| 385 | *idx += 2; |
| 386 | } else |
| 387 | *carry_over = (last_entry | msg->buf[dev->pos]); |
| 388 | } else { |
| 389 | writel((last_entry | msg->buf[dev->pos]), |
| 390 | dev->base + QUP_OUT_FIFO_BASE); |
| 391 | |
| 392 | qup_verify_fifo(dev, last_entry | msg->buf[dev->pos], |
| 393 | (unsigned)dev->base + QUP_OUT_FIFO_BASE + |
| 394 | (*idx), 0); |
| 395 | } |
| 396 | } else { |
| 397 | writel(val | ((last_entry | msg->buf[dev->pos]) << 16), |
| 398 | dev->base + QUP_OUT_FIFO_BASE); |
| 399 | |
| 400 | qup_verify_fifo(dev, val | (last_entry << 16) | |
| 401 | (msg->buf[dev->pos] << 16), (unsigned)dev->base + |
| 402 | QUP_OUT_FIFO_BASE + (*idx) - 2, 0); |
| 403 | } |
| 404 | |
| 405 | *idx += 2; |
| 406 | dev->pos++; |
| 407 | dev->cnt = msg->len - dev->pos; |
| 408 | } |
| 409 | |
| 410 | static int qup_update_state(struct qup_i2c_dev *dev, unsigned state) |
| 411 | { |
| 412 | if (qup_i2c_poll_state(dev, 0) != 0) |
| 413 | return -EIO; |
| 414 | writel(state, dev->base + QUP_STATE); |
| 415 | if (qup_i2c_poll_state(dev, state) != 0) |
| 416 | return -EIO; |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | static int qup_set_read_mode(struct qup_i2c_dev *dev, int rd_len) |
| 421 | { |
| 422 | unsigned wr_mode = (dev->wr_sz < dev->out_fifo_sz) ? QUP_WR_BLK_MODE : 0; |
| 423 | if (rd_len > 256) { |
| 424 | dprintf(INFO, "HW doesn't support READs > 256 bytes\n"); |
| 425 | return -EPROTONOSUPPORT; |
| 426 | } |
| 427 | if (rd_len <= dev->in_fifo_sz) { |
| 428 | writel(wr_mode | QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE); |
| 429 | writel(rd_len, dev->base + QUP_MX_READ_CNT); |
| 430 | } else { |
| 431 | writel(wr_mode | QUP_RD_BLK_MODE | |
| 432 | QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE); |
| 433 | writel(rd_len, dev->base + QUP_MX_INPUT_CNT); |
| 434 | } |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static int qup_set_wr_mode(struct qup_i2c_dev *dev, int rem) |
| 439 | { |
| 440 | int total_len = 0; |
| 441 | int ret = 0; |
| 442 | if (dev->msg->len >= (dev->out_fifo_sz - 1)) { |
| 443 | total_len = dev->msg->len + 1 + (dev->msg->len / (dev->out_blk_sz - 1)); |
| 444 | writel(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN, |
| 445 | dev->base + QUP_IO_MODE); |
| 446 | dev->wr_sz = dev->out_blk_sz; |
| 447 | } else |
| 448 | writel(QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE); |
| 449 | |
| 450 | if (rem > 1) { |
| 451 | struct i2c_msg *next = dev->msg + 1; |
| 452 | if (next->addr == dev->msg->addr && next->flags == I2C_M_RD) { |
| 453 | ret = qup_set_read_mode(dev, next->len); |
| 454 | /* make sure read start & read command are in 1 blk */ |
| 455 | if ((total_len % dev->out_blk_sz) == (dev->out_blk_sz - 1)) |
| 456 | total_len += 3; |
| 457 | else |
| 458 | total_len += 2; |
| 459 | } |
| 460 | } |
| 461 | /* WRITE COUNT register valid/used only in block mode */ |
| 462 | if (dev->wr_sz == dev->out_blk_sz) |
| 463 | writel(total_len, dev->base + QUP_MX_WR_CNT); |
| 464 | return ret; |
| 465 | } |
| 466 | |
| 467 | int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num) |
| 468 | { |
| 469 | int ret; |
| 470 | int rem = num; |
| 471 | int err; |
| 472 | |
| 473 | if (dev->suspended) { |
| 474 | return -EIO; |
| 475 | } |
| 476 | |
| 477 | /* Set the GSBIn_QUP_APPS_CLK to 24MHz, then below figure out what speed to |
| 478 | run I2C_MASTER_CORE at. */ |
| 479 | if (dev->clk_state == 0) { |
| 480 | if (dev->clk_ctl == 0) { |
| 481 | set_i2c_clk(dev); |
| 482 | } |
| 483 | } |
| 484 | /* Initialize QUP registers during first transfer */ |
| 485 | if (dev->clk_ctl == 0) { |
| 486 | int fs_div; |
| 487 | int hs_div; |
| 488 | unsigned fifo_reg; |
| 489 | /* Configure the GSBI Protocol Code for i2c */ |
| 490 | writel((GSBI_PROTOCOL_CODE_I2C << |
| 491 | GSBI_CTRL_REG_PROTOCOL_CODE_S), dev->base); |
| 492 | |
| 493 | fs_div = ((dev->src_clk_freq / dev->clk_freq) / 2) - 3; |
| 494 | hs_div = 3; |
| 495 | dev->clk_ctl = ((hs_div & 0x7) << 8) | (fs_div & 0xff); |
| 496 | fifo_reg = readl(dev->base + QUP_IO_MODE); |
| 497 | if (fifo_reg & 0x3) |
| 498 | dev->out_blk_sz = (fifo_reg & 0x3) * 16; |
| 499 | else |
| 500 | dev->out_blk_sz = 16; |
| 501 | if (fifo_reg & 0x60) |
| 502 | dev->in_blk_sz = ((fifo_reg & 0x60) >> 5) * 16; |
| 503 | else |
| 504 | dev->in_blk_sz = 16; |
| 505 | /* |
| 506 | * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' |
| 507 | * associated with each byte written/received |
| 508 | */ |
| 509 | dev->out_blk_sz /= 2; |
| 510 | dev->in_blk_sz /= 2; |
| 511 | dev->out_fifo_sz = dev->out_blk_sz * (2 << ((fifo_reg & 0x1C) >> 2)); |
| 512 | dev->in_fifo_sz = dev->in_blk_sz * (2 << ((fifo_reg & 0x380) >> 7)); |
| 513 | dprintf(CRITICAL, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n", |
| 514 | dev->in_blk_sz, dev->in_fifo_sz, |
| 515 | dev->out_blk_sz, dev->out_fifo_sz); |
| 516 | } |
| 517 | |
| 518 | unmask_interrupt(dev->qup_irq); |
| 519 | writel(1, dev->base + QUP_SW_RESET); |
| 520 | ret = qup_i2c_poll_state(dev, QUP_RESET_STATE); |
| 521 | if (ret) { |
| 522 | dprintf(INFO, "QUP Busy:Trying to recover\n"); |
| 523 | goto out_err; |
| 524 | } |
| 525 | |
| 526 | /* Initialize QUP registers */ |
| 527 | writel(0, dev->base + QUP_CONFIG); |
| 528 | writel(QUP_OPERATIONAL_RESET, dev->base + QUP_OPERATIONAL); |
| 529 | writel(QUP_STATUS_ERROR_FLAGS, dev->base + QUP_ERROR_FLAGS_EN); |
| 530 | |
| 531 | writel(I2C_MINI_CORE | I2C_N_VAL, dev->base + QUP_CONFIG); |
| 532 | |
| 533 | /* Initialize I2C mini core registers */ |
| 534 | writel(0, dev->base + QUP_I2C_CLK_CTL); |
| 535 | writel(QUP_I2C_STATUS_RESET, dev->base + QUP_I2C_STATUS); |
| 536 | |
| 537 | dev->cnt = msgs->len; |
| 538 | dev->pos = 0; |
| 539 | dev->msg = msgs; |
| 540 | while (rem) { |
| 541 | int filled = FALSE; |
| 542 | |
| 543 | dev->wr_sz = dev->out_fifo_sz; |
| 544 | dev->err = 0; |
| 545 | |
| 546 | if (qup_i2c_poll_state(dev, QUP_I2C_MAST_GEN) != 0) { |
| 547 | ret = -EIO; |
| 548 | goto out_err; |
| 549 | } |
| 550 | |
| 551 | qup_print_status(dev); |
| 552 | /* HW limits Read upto 256 bytes in 1 read without stop */ |
| 553 | if (dev->msg->flags & I2C_M_RD) { |
| 554 | ret = qup_set_read_mode(dev, dev->cnt); |
| 555 | if (ret != 0) |
| 556 | goto out_err; |
| 557 | } else { |
| 558 | ret = qup_set_wr_mode(dev, rem); |
| 559 | if (ret != 0) |
| 560 | goto out_err; |
| 561 | /* Don't fill block till we get interrupt */ |
| 562 | if (dev->wr_sz == dev->out_blk_sz) |
| 563 | filled = TRUE; |
| 564 | } |
| 565 | |
| 566 | err = qup_update_state(dev, QUP_RUN_STATE); |
| 567 | if (err < 0) { |
| 568 | ret = err; |
| 569 | goto out_err; |
| 570 | } |
| 571 | |
| 572 | qup_print_status(dev); |
| 573 | writel(dev->clk_ctl, dev->base + QUP_I2C_CLK_CTL); |
| 574 | |
| 575 | do { |
| 576 | int idx = 0; |
| 577 | unsigned carry_over = 0; |
| 578 | |
| 579 | /* Transition to PAUSE state only possible from RUN */ |
| 580 | err = qup_update_state(dev, QUP_PAUSE_STATE); |
| 581 | if (err < 0) { |
| 582 | ret = err; |
| 583 | goto out_err; |
| 584 | } |
| 585 | |
| 586 | qup_print_status(dev); |
| 587 | /* This operation is Write, check the next operation and decide |
| 588 | mode */ |
| 589 | while (filled == FALSE) { |
| 590 | if ((msgs->flags & I2C_M_RD) && (dev->cnt == msgs->len)) |
| 591 | qup_issue_read(dev, msgs, &idx, carry_over); |
| 592 | else if (!(msgs->flags & I2C_M_RD)) |
| 593 | qup_issue_write(dev, msgs, rem, &idx, &carry_over); |
| 594 | if (idx >= (dev->wr_sz << 1)) |
| 595 | filled = TRUE; |
| 596 | /* Start new message */ |
| 597 | if (filled == FALSE) { |
| 598 | if (msgs->flags & I2C_M_RD) |
| 599 | filled = TRUE; |
| 600 | else if (rem > 1) { |
| 601 | /* Only combine operations with same address */ |
| 602 | struct i2c_msg *next = msgs + 1; |
| 603 | if (next->addr != msgs->addr || next->flags == 0) |
| 604 | filled = TRUE; |
| 605 | else { |
| 606 | rem--; |
| 607 | msgs++; |
| 608 | dev->msg = msgs; |
| 609 | dev->pos = 0; |
| 610 | dev->cnt = msgs->len; |
| 611 | } |
| 612 | } else |
| 613 | filled = TRUE; |
| 614 | } |
| 615 | } |
| 616 | err = qup_update_state(dev, QUP_RUN_STATE); |
| 617 | if (err < 0) { |
| 618 | ret = err; |
| 619 | goto out_err; |
| 620 | } |
| 621 | dprintf(CRITICAL, "idx:%d, rem:%d, num:%d, mode:%d\n", |
| 622 | idx, rem, num, dev->mode); |
| 623 | |
| 624 | qup_print_status(dev); |
| 625 | if (dev->err) { |
| 626 | if (dev->err & QUP_I2C_NACK_FLAG) { |
| 627 | dprintf(CRITICAL, |
| 628 | "I2C slave addr:0x%x not connected\n", |
| 629 | dev->msg->addr); |
| 630 | } else { |
| 631 | dprintf(INFO, "QUP data xfer error %d\n", dev->err); |
| 632 | } |
| 633 | ret = dev->err; |
| 634 | goto out_err; |
| 635 | } |
| 636 | if (dev->msg->flags & I2C_M_RD) { |
| 637 | int i; |
| 638 | unsigned dval = 0; |
| 639 | for (i = 0; dev->pos < dev->msg->len; i++, dev->pos++) { |
| 640 | unsigned rd_status = readl(dev->base + QUP_OPERATIONAL); |
| 641 | if (i % 2 == 0) { |
| 642 | if ((rd_status & QUP_IN_NOT_EMPTY) == 0) |
| 643 | break; |
| 644 | dval = readl(dev->base + QUP_IN_FIFO_BASE); |
| 645 | dev->msg->buf[dev->pos] = dval & 0xFF; |
| 646 | } else |
| 647 | dev->msg->buf[dev->pos] = ((dval & 0xFF0000) >> 16); |
| 648 | } |
| 649 | dev->cnt -= i; |
| 650 | } else |
| 651 | filled = FALSE; /* refill output FIFO */ |
| 652 | } while (dev->cnt > 0); |
| 653 | if (dev->cnt == 0) { |
| 654 | rem--; |
| 655 | msgs++; |
| 656 | if (rem) { |
| 657 | dev->pos = 0; |
| 658 | dev->cnt = msgs->len; |
| 659 | dev->msg = msgs; |
| 660 | } |
| 661 | } |
| 662 | /* Wait for I2C bus to be idle */ |
| 663 | ret = qup_i2c_poll_writeready(dev); |
| 664 | if (ret) { |
| 665 | dprintf(INFO, "Error waiting for write ready\n"); |
| 666 | goto out_err; |
| 667 | } |
| 668 | } |
| 669 | |
| 670 | ret = num; |
| 671 | out_err: |
| 672 | dev->msg = NULL; |
| 673 | dev->pos = 0; |
| 674 | dev->err = 0; |
| 675 | dev->cnt = 0; |
| 676 | mask_interrupt(dev->qup_irq); |
| 677 | return ret; |
| 678 | } |
| 679 | |
| 680 | static int set_gsbi_number(struct qup_i2c_dev *dev) |
| 681 | { |
| 682 | switch (dev->base) { |
| 683 | case GSBI1_QUP_BASE: |
| 684 | dev->gsbi_number = 1; |
| 685 | break; |
| 686 | case GSBI2_QUP_BASE: |
| 687 | dev->gsbi_number = 2; |
| 688 | break; |
| 689 | case GSBI3_QUP_BASE: |
| 690 | dev->gsbi_number = 3; |
| 691 | break; |
| 692 | case GSBI4_QUP_BASE: |
| 693 | dev->gsbi_number = 4; |
| 694 | break; |
| 695 | case GSBI5_QUP_BASE: |
| 696 | dev->gsbi_number = 5; |
| 697 | break; |
| 698 | case GSBI6_QUP_BASE: |
| 699 | dev->gsbi_number = 6; |
| 700 | break; |
| 701 | case GSBI7_QUP_BASE: |
| 702 | dev->gsbi_number = 7; |
| 703 | break; |
| 704 | case GSBI8_QUP_BASE: |
| 705 | dev->gsbi_number = 8; |
| 706 | break; |
| 707 | case GSBI9_QUP_BASE: |
| 708 | dev->gsbi_number = 9; |
| 709 | break; |
| 710 | case GSBI10_QUP_BASE: |
| 711 | dev->gsbi_number = 10; |
| 712 | break; |
| 713 | case GSBI11_QUP_BASE: |
| 714 | dev->gsbi_number = 11; |
| 715 | break; |
| 716 | case GSBI12_QUP_BASE: |
| 717 | dev->gsbi_number = 12; |
| 718 | break; |
| 719 | default: |
| 720 | return 1; |
| 721 | } |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | static int set_qup_irq(struct qup_i2c_dev *dev) |
| 726 | { |
| 727 | switch (dev->base) { |
| 728 | case GSBI1_QUP_BASE: |
| 729 | dev->qup_irq = GSBI1_QUP_IRQ; |
| 730 | break; |
| 731 | case GSBI2_QUP_BASE: |
| 732 | dev->qup_irq = GSBI2_QUP_IRQ; |
| 733 | break; |
| 734 | case GSBI3_QUP_BASE: |
| 735 | dev->qup_irq = GSBI3_QUP_IRQ; |
| 736 | break; |
| 737 | case GSBI4_QUP_BASE: |
| 738 | dev->qup_irq = GSBI4_QUP_IRQ; |
| 739 | break; |
| 740 | case GSBI5_QUP_BASE: |
| 741 | dev->qup_irq = GSBI5_QUP_IRQ; |
| 742 | break; |
| 743 | case GSBI6_QUP_BASE: |
| 744 | dev->qup_irq = GSBI6_QUP_IRQ; |
| 745 | break; |
| 746 | case GSBI7_QUP_BASE: |
| 747 | dev->qup_irq = GSBI7_QUP_IRQ; |
| 748 | break; |
| 749 | case GSBI8_QUP_BASE: |
| 750 | dev->qup_irq = GSBI8_QUP_IRQ; |
| 751 | break; |
| 752 | case GSBI9_QUP_BASE: |
| 753 | dev->qup_irq = GSBI9_QUP_IRQ; |
| 754 | break; |
| 755 | case GSBI10_QUP_BASE: |
| 756 | dev->qup_irq = GSBI10_QUP_IRQ; |
| 757 | break; |
| 758 | case GSBI11_QUP_BASE: |
| 759 | dev->qup_irq = GSBI11_QUP_IRQ; |
| 760 | break; |
| 761 | case GSBI12_QUP_BASE: |
| 762 | dev->qup_irq = GSBI12_QUP_IRQ; |
| 763 | break; |
| 764 | default: |
| 765 | return 1; |
| 766 | } |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | struct qup_i2c_dev *qup_i2c_init(unsigned base, |
| 771 | unsigned clk_freq, unsigned src_clk_freq) |
| 772 | { |
| 773 | struct qup_i2c_dev *dev; |
| 774 | if (dev_addr != NULL) { |
| 775 | return dev_addr; |
| 776 | } |
| 777 | |
| 778 | dev = malloc(sizeof(struct qup_i2c_dev)); |
| 779 | if (!dev) { |
| 780 | return NULL; |
| 781 | } |
| 782 | dev = memset(dev, 0, sizeof(struct qup_i2c_dev)); |
| 783 | |
| 784 | /* This must be done for qup_i2c_interrupt to work. */ |
| 785 | dev_addr = dev; |
| 786 | |
| 787 | /* Initialize the GPIO for GSBIn as i2c */ |
| 788 | i2c_gpio_cfg(base); |
| 789 | |
| 790 | /* Configure GSBIn in i2c mode */ |
| 791 | writel(GSBI_CTL_PROTOCOL_CODE_I2C, base); |
| 792 | |
| 793 | /* Set the base address for GSBIn QUP The reason we add 0x80000 is to make |
| 794 | the GSBIn base address be the GSBIn QUP base address, which is what the |
| 795 | i2c driver wants. */ |
| 796 | dev->base = base + 0x80000; |
| 797 | |
| 798 | /* Set clk_freq and src_clk_freq for i2c. */ |
| 799 | dev->clk_freq = clk_freq; |
| 800 | dev->src_clk_freq = src_clk_freq; |
| 801 | |
| 802 | dev->num_irqs = 1; |
| 803 | |
| 804 | dev->one_bit_t = USEC_PER_SEC / dev->clk_freq; |
| 805 | dev->clk_ctl = 0; |
| 806 | |
| 807 | /* Set the IRQ number for GSBIn_BASE address */ |
| 808 | if (set_qup_irq(dev)) { |
| 809 | dprintf(INFO, |
| 810 | "Could not find a valid QUP IRQ value based on GSBIn_BASE: %d\n", |
| 811 | base); |
| 812 | dprintf(INFO, "Please double check the GSBIn_BASE address.\n"); |
| 813 | return NULL; |
| 814 | } |
| 815 | |
| 816 | /* Set the GSBI number based on GSBIn_BASE address */ |
| 817 | if (set_gsbi_number(dev)) { |
| 818 | dprintf(INFO, "Could not find a valid GSBI # based on GSBIn_BASE: %d\n", |
| 819 | base); |
| 820 | dprintf(INFO, "Please double check the GSBIn_BASE address.\n"); |
| 821 | return NULL; |
| 822 | } |
| 823 | |
| 824 | /* Register the GSBIn QUP IRQ */ |
| 825 | register_int_handler(dev->qup_irq, qup_i2c_interrupt, 0); |
| 826 | |
| 827 | /* Then disable it */ |
| 828 | mask_interrupt(dev->qup_irq); |
| 829 | |
| 830 | return dev; |
| 831 | } |
| 832 | |
| 833 | int qup_i2c_deinit(struct qup_i2c_dev *dev) |
| 834 | { |
| 835 | /* Disable the qup_irq */ |
| 836 | mask_interrupt(dev->qup_irq); |
| 837 | /* Free the memory used for dev */ |
| 838 | free(dev); |
| 839 | return 0; |
| 840 | } |