Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 1 | /* |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Linux Foundation nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <err.h> |
| 30 | #include <assert.h> |
| 31 | #include <debug.h> |
| 32 | #include <reg.h> |
| 33 | #include <clock.h> |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 34 | #include <pm8x41.h> |
Sundarajan Srinivasan | 4bbce72 | 2013-07-03 11:13:31 -0700 | [diff] [blame] | 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <platform/timer.h> |
| 38 | |
| 39 | void hsusb_clock_init(void) |
| 40 | { |
| 41 | int ret; |
| 42 | struct clk *iclk; |
| 43 | struct clk *cclk; |
| 44 | |
| 45 | iclk = clk_get("usb_iface_clk"); |
| 46 | cclk = clk_get("usb_core_clk"); |
| 47 | |
| 48 | ASSERT(iclk); |
| 49 | ASSERT(cclk); |
| 50 | |
| 51 | /* Disable interface and core clk */ |
| 52 | clk_disable(iclk); |
| 53 | clk_disable(cclk); |
| 54 | |
| 55 | /* Start the block reset for usb */ |
| 56 | writel(1, USB_HS_BCR); |
| 57 | |
| 58 | /* Take usb block out of reset */ |
| 59 | writel(0, USB_HS_BCR); |
| 60 | |
| 61 | ret = clk_enable(iclk); |
| 62 | if(ret) |
| 63 | { |
| 64 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 65 | ASSERT(0); |
| 66 | } |
| 67 | |
| 68 | ret = clk_set_rate(cclk, 75000000); |
| 69 | if(ret) |
| 70 | { |
| 71 | dprintf(CRITICAL, "failed to set_rate of usb_core_clk ret = %d\n", ret); |
| 72 | ASSERT(0); |
| 73 | } |
| 74 | |
| 75 | ret = clk_enable(cclk); |
| 76 | if(ret) |
| 77 | { |
| 78 | dprintf(CRITICAL, "failed to enable usb_core_clk ret = %d\n", ret); |
| 79 | ASSERT(0); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | void clock_config_uart_dm(uint8_t id) |
| 84 | { |
| 85 | int ret; |
| 86 | char clk_name[64]; |
| 87 | |
| 88 | ret = clk_get_set_enable("uart_iface_clk", 0, 1); |
| 89 | if (ret) |
| 90 | { |
| 91 | dprintf(CRITICAL, "failed to set uart_iface_clk ret = %d\n", ret); |
| 92 | ASSERT(0); |
| 93 | } |
| 94 | |
| 95 | snprintf(clk_name, 64, "uart%u_core_clk", id); |
| 96 | |
| 97 | ret = clk_get_set_enable(clk_name, 7372800, 1); |
| 98 | if (ret) |
| 99 | { |
| 100 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 101 | ASSERT(0); |
| 102 | } |
| 103 | } |
| 104 | |
Channagoud Kadabi | 5a83d2f | 2014-02-04 17:00:13 -0800 | [diff] [blame] | 105 | /* |
| 106 | * Disable power collapse using GDSCR: |
| 107 | * Globally Distributed Switch Controller Register |
| 108 | */ |
| 109 | void clock_usb30_gdsc_enable(void) |
| 110 | { |
| 111 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 112 | |
| 113 | reg &= ~(0x1); |
| 114 | |
| 115 | writel(reg, GCC_USB30_GDSCR); |
| 116 | } |
| 117 | |
| 118 | /* enables usb30 clocks */ |
| 119 | void clock_usb30_init(void) |
| 120 | { |
| 121 | int ret; |
| 122 | |
| 123 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 124 | if(ret) |
| 125 | { |
| 126 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 127 | ASSERT(0); |
| 128 | } |
| 129 | |
| 130 | clock_usb30_gdsc_enable(); |
| 131 | |
| 132 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 133 | if(ret) |
| 134 | { |
| 135 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 136 | ASSERT(0); |
| 137 | } |
| 138 | |
| 139 | ret = clk_get_set_enable("usb30_pipe_clk", 19200000, 1); |
| 140 | if(ret) |
| 141 | { |
| 142 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 143 | ASSERT(0); |
| 144 | } |
| 145 | |
| 146 | ret = clk_get_set_enable("usb30_aux_clk", 1000000, 1); |
| 147 | if(ret) |
| 148 | { |
| 149 | dprintf(CRITICAL, "failed to set usb30_aux_clk. ret = %d\n", ret); |
| 150 | ASSERT(0); |
| 151 | } |
| 152 | |
| 153 | ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1); |
| 154 | if(ret) |
| 155 | { |
| 156 | dprintf(CRITICAL, "failed to set usb_phy_cfg_ahb_clk ret = %d\n", ret); |
| 157 | ASSERT(0); |
| 158 | } |
| 159 | |
| 160 | pm8x41_lnbb_clock_ctrl(1); |
| 161 | } |
| 162 | |
| 163 | void clock_bumpup_pipe3_clk() |
| 164 | { |
| 165 | int ret = 0; |
| 166 | |
| 167 | ret = clk_get_set_enable("usb30_pipe_clk", 125000000, 0); |
| 168 | if(ret) |
| 169 | { |
| 170 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 171 | ASSERT(0); |
| 172 | } |
| 173 | } |