Channagoud Kadabi | 196b27c | 2015-01-19 13:53:38 -0500 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | 92db112 | 2014-06-25 16:00:13 -0400 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define mmpll0_mm_source_val 1 |
| 44 | #define mmpll1_mm_source_val 2 |
| 45 | #define mmpll3_mm_source_val 3 |
| 46 | #define gpll0_mm_source_val 5 |
| 47 | |
| 48 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 49 | |
| 50 | |
| 51 | /* Clock Operations */ |
Channagoud Kadabi | 196b27c | 2015-01-19 13:53:38 -0500 | [diff] [blame] | 52 | static struct clk_ops clk_ops_rst = |
| 53 | { |
| 54 | .reset = clock_lib2_reset_clk_reset, |
| 55 | }; |
| 56 | |
Channagoud Kadabi | 92db112 | 2014-06-25 16:00:13 -0400 | [diff] [blame] | 57 | static struct clk_ops clk_ops_branch = |
| 58 | { |
| 59 | .enable = clock_lib2_branch_clk_enable, |
| 60 | .disable = clock_lib2_branch_clk_disable, |
| 61 | .set_rate = clock_lib2_branch_set_rate, |
| 62 | }; |
| 63 | |
| 64 | static struct clk_ops clk_ops_rcg_mnd = |
| 65 | { |
| 66 | .enable = clock_lib2_rcg_enable, |
| 67 | .set_rate = clock_lib2_rcg_set_rate, |
| 68 | }; |
| 69 | |
| 70 | static struct clk_ops clk_ops_rcg = |
| 71 | { |
| 72 | .enable = clock_lib2_rcg_enable, |
| 73 | .set_rate = clock_lib2_rcg_set_rate, |
| 74 | }; |
| 75 | |
| 76 | static struct clk_ops clk_ops_cxo = |
| 77 | { |
| 78 | .enable = cxo_clk_enable, |
| 79 | .disable = cxo_clk_disable, |
| 80 | }; |
| 81 | |
| 82 | static struct clk_ops clk_ops_pll_vote = |
| 83 | { |
| 84 | .enable = pll_vote_clk_enable, |
| 85 | .disable = pll_vote_clk_disable, |
| 86 | .auto_off = pll_vote_clk_disable, |
| 87 | .is_enabled = pll_vote_clk_is_enabled, |
| 88 | }; |
| 89 | |
| 90 | static struct clk_ops clk_ops_vote = |
| 91 | { |
| 92 | .enable = clock_lib2_vote_clk_enable, |
| 93 | .disable = clock_lib2_vote_clk_disable, |
| 94 | }; |
| 95 | |
| 96 | /* Clock Sources */ |
| 97 | static struct fixed_clk cxo_clk_src = |
| 98 | { |
| 99 | .c = { |
| 100 | .rate = 19200000, |
| 101 | .dbg_name = "cxo_clk_src", |
| 102 | .ops = &clk_ops_cxo, |
| 103 | }, |
| 104 | }; |
| 105 | |
| 106 | static struct pll_vote_clk gpll0_clk_src = |
| 107 | { |
| 108 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 109 | .en_mask = BIT(0), |
| 110 | .status_reg = (void *) GPLL0_STATUS, |
| 111 | .status_mask = BIT(17), |
| 112 | .parent = &cxo_clk_src.c, |
| 113 | |
| 114 | .c = { |
| 115 | .rate = 600000000, |
| 116 | .dbg_name = "gpll0_clk_src", |
| 117 | .ops = &clk_ops_pll_vote, |
| 118 | }, |
| 119 | }; |
| 120 | |
| 121 | /* SDCC Clocks */ |
| 122 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 123 | { |
| 124 | F( 144000, cxo, 16, 3, 25), |
| 125 | F( 400000, cxo, 12, 1, 4), |
| 126 | F( 20000000, gpll0, 15, 1, 2), |
| 127 | F( 25000000, gpll0, 12, 1, 2), |
| 128 | F( 50000000, gpll0, 12, 0, 0), |
| 129 | F(100000000, gpll0, 6, 0, 0), |
| 130 | F(200000000, gpll0, 3, 0, 0), |
| 131 | F_END |
| 132 | }; |
| 133 | |
| 134 | static struct rcg_clk sdcc1_apps_clk_src = |
| 135 | { |
| 136 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 137 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 138 | .m_reg = (uint32_t *) SDCC1_M, |
| 139 | .n_reg = (uint32_t *) SDCC1_N, |
| 140 | .d_reg = (uint32_t *) SDCC1_D, |
| 141 | |
| 142 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 143 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 144 | .current_freq = &rcg_dummy_freq, |
| 145 | |
| 146 | .c = { |
| 147 | .dbg_name = "sdc1_clk", |
| 148 | .ops = &clk_ops_rcg_mnd, |
| 149 | }, |
| 150 | }; |
| 151 | |
| 152 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 153 | { |
| 154 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 155 | .parent = &sdcc1_apps_clk_src.c, |
| 156 | |
| 157 | .c = { |
| 158 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 159 | .ops = &clk_ops_branch, |
| 160 | }, |
| 161 | }; |
| 162 | |
| 163 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 164 | { |
| 165 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 166 | .has_sibling = 1, |
| 167 | |
| 168 | .c = { |
| 169 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 170 | .ops = &clk_ops_branch, |
| 171 | }, |
| 172 | }; |
| 173 | |
| 174 | /* UART Clocks */ |
| 175 | static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_4_apps_clk[] = |
| 176 | { |
| 177 | F( 3686400, gpll0, 1, 96, 15625), |
| 178 | F( 7372800, gpll0, 1, 192, 15625), |
| 179 | F(14745600, gpll0, 1, 384, 15625), |
| 180 | F(16000000, gpll0, 5, 2, 15), |
| 181 | F(19200000, cxo, 1, 0, 0), |
| 182 | F(24000000, gpll0, 5, 1, 5), |
| 183 | F(32000000, gpll0, 1, 4, 75), |
| 184 | F(40000000, gpll0, 15, 0, 0), |
| 185 | F(46400000, gpll0, 1, 29, 375), |
| 186 | F(48000000, gpll0, 12.5, 0, 0), |
| 187 | F(51200000, gpll0, 1, 32, 375), |
| 188 | F(56000000, gpll0, 1, 7, 75), |
| 189 | F(58982400, gpll0, 1, 1536, 15625), |
| 190 | F(60000000, gpll0, 10, 0, 0), |
| 191 | F_END |
| 192 | }; |
| 193 | |
| 194 | static struct rcg_clk blsp1_uart0_apps_clk_src = |
| 195 | { |
| 196 | .cmd_reg = (uint32_t *) BLSP1_UART0_APPS_CMD_RCGR, |
| 197 | .cfg_reg = (uint32_t *) BLSP1_UART0_APPS_CFG_RCGR, |
| 198 | .m_reg = (uint32_t *) BLSP1_UART0_APPS_M, |
| 199 | .n_reg = (uint32_t *) BLSP1_UART0_APPS_N, |
| 200 | .d_reg = (uint32_t *) BLSP1_UART0_APPS_D, |
| 201 | |
| 202 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 203 | .freq_tbl = ftbl_gcc_blsp1_uart1_4_apps_clk, |
| 204 | .current_freq = &rcg_dummy_freq, |
| 205 | |
| 206 | .c = { |
| 207 | .dbg_name = "blsp1_uart0_apps_clk", |
| 208 | .ops = &clk_ops_rcg_mnd, |
| 209 | }, |
| 210 | }; |
| 211 | |
| 212 | static struct branch_clk gcc_blsp1_uart0_apps_clk = |
| 213 | { |
| 214 | .cbcr_reg = (uint32_t *) BLSP1_UART0_APPS_CBCR, |
| 215 | .parent = &blsp1_uart0_apps_clk_src.c, |
| 216 | |
| 217 | .c = { |
| 218 | .dbg_name = "gcc_blsp1_uart0_apps_clk", |
| 219 | .ops = &clk_ops_branch, |
| 220 | }, |
| 221 | }; |
| 222 | |
| 223 | static struct rcg_clk blsp1_uart1_apps_clk_src = |
| 224 | { |
| 225 | .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR, |
| 226 | .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR, |
| 227 | .m_reg = (uint32_t *) BLSP1_UART1_APPS_M, |
| 228 | .n_reg = (uint32_t *) BLSP1_UART1_APPS_N, |
| 229 | .d_reg = (uint32_t *) BLSP1_UART1_APPS_D, |
| 230 | |
| 231 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 232 | .freq_tbl = ftbl_gcc_blsp1_uart1_4_apps_clk, |
| 233 | .current_freq = &rcg_dummy_freq, |
| 234 | |
| 235 | .c = { |
| 236 | .dbg_name = "blsp1_uart1_apps_clk", |
| 237 | .ops = &clk_ops_rcg_mnd, |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static struct branch_clk gcc_blsp1_uart1_apps_clk = |
| 242 | { |
| 243 | .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR, |
| 244 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 245 | |
| 246 | .c = { |
| 247 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 248 | .ops = &clk_ops_branch, |
| 249 | }, |
| 250 | }; |
| 251 | |
| 252 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 253 | { |
| 254 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 255 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 256 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 257 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 258 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 259 | |
| 260 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 261 | .freq_tbl = ftbl_gcc_blsp1_uart1_4_apps_clk, |
| 262 | .current_freq = &rcg_dummy_freq, |
| 263 | |
| 264 | .c = { |
| 265 | .dbg_name = "blsp1_uart2_apps_clk", |
| 266 | .ops = &clk_ops_rcg_mnd, |
| 267 | }, |
| 268 | }; |
| 269 | |
| 270 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 271 | { |
| 272 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 273 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 274 | |
| 275 | .c = { |
| 276 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 277 | .ops = &clk_ops_branch, |
| 278 | }, |
| 279 | }; |
| 280 | |
| 281 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
| 282 | { |
| 283 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 284 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 285 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 286 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 287 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
| 288 | |
| 289 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 290 | .freq_tbl = ftbl_gcc_blsp1_uart1_4_apps_clk, |
| 291 | .current_freq = &rcg_dummy_freq, |
| 292 | |
| 293 | .c = { |
| 294 | .dbg_name = "blsp1_uart3_apps_clk", |
| 295 | .ops = &clk_ops_rcg_mnd, |
| 296 | }, |
| 297 | }; |
| 298 | |
| 299 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
| 300 | { |
| 301 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 302 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 303 | |
| 304 | .c = { |
| 305 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 306 | .ops = &clk_ops_branch, |
| 307 | }, |
| 308 | }; |
| 309 | |
| 310 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 311 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 312 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 313 | .en_mask = BIT(17), |
| 314 | |
| 315 | .c = { |
| 316 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 317 | .ops = &clk_ops_vote, |
| 318 | }, |
| 319 | }; |
| 320 | |
| 321 | /* USB Clocks */ |
| 322 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 323 | { |
| 324 | F(75000000, gpll0, 8, 0, 0), |
| 325 | F_END |
| 326 | }; |
| 327 | |
| 328 | static struct rcg_clk usb_hs_system_clk_src = |
| 329 | { |
| 330 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 331 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 332 | |
| 333 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 334 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 335 | .current_freq = &rcg_dummy_freq, |
| 336 | |
| 337 | .c = { |
| 338 | .dbg_name = "usb_hs_system_clk", |
| 339 | .ops = &clk_ops_rcg, |
| 340 | }, |
| 341 | }; |
| 342 | |
| 343 | static struct branch_clk gcc_usb_hs_system_clk = |
| 344 | { |
| 345 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 346 | .parent = &usb_hs_system_clk_src.c, |
| 347 | |
| 348 | .c = { |
| 349 | .dbg_name = "gcc_usb_hs_system_clk", |
| 350 | .ops = &clk_ops_branch, |
| 351 | }, |
| 352 | }; |
| 353 | |
| 354 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 355 | { |
| 356 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 357 | .has_sibling = 1, |
| 358 | |
| 359 | .c = { |
| 360 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 361 | .ops = &clk_ops_branch, |
| 362 | }, |
| 363 | }; |
| 364 | |
Channagoud Kadabi | 196b27c | 2015-01-19 13:53:38 -0500 | [diff] [blame] | 365 | /* USB30 Clocks */ |
| 366 | |
| 367 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = { |
| 368 | .cbcr_reg = (uint32_t *) GCC_SYS_NOC_USB3_AXI_CBCR, |
| 369 | .has_sibling = 1, |
| 370 | |
| 371 | .c = { |
| 372 | .dbg_name = "sys_noc_usb30_axi_clk", |
| 373 | .ops = &clk_ops_branch, |
| 374 | }, |
| 375 | }; |
| 376 | |
| 377 | static struct branch_clk gcc_usb2b_phy_sleep_clk = { |
| 378 | .cbcr_reg = (uint32_t *) GCC_USB2A_PHY_SLEEP_CBCR, |
| 379 | .bcr_reg = (uint32_t *) GCC_USB2A_PHY_BCR, |
| 380 | .has_sibling = 1, |
| 381 | |
| 382 | .c = { |
| 383 | .dbg_name = "usb2b_phy_sleep_clk", |
| 384 | .ops = &clk_ops_branch, |
| 385 | }, |
| 386 | }; |
| 387 | |
| 388 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
| 389 | F( 125000000, gpll0, 1, 5, 24), |
| 390 | F_END |
| 391 | }; |
| 392 | |
| 393 | static struct rcg_clk usb30_master_clk_src = { |
| 394 | .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR, |
| 395 | .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR, |
| 396 | .m_reg = (uint32_t *) GCC_USB30_MASTER_M, |
| 397 | .n_reg = (uint32_t *) GCC_USB30_MASTER_N, |
| 398 | .d_reg = (uint32_t *) GCC_USB30_MASTER_D, |
| 399 | |
| 400 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 401 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 402 | .current_freq = &rcg_dummy_freq, |
| 403 | |
| 404 | .c = { |
| 405 | .dbg_name = "usb30_master_clk_src", |
| 406 | .ops = &clk_ops_rcg, |
| 407 | }, |
| 408 | }; |
| 409 | |
| 410 | static struct branch_clk gcc_usb30_master_clk = { |
| 411 | .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR, |
| 412 | .bcr_reg = (uint32_t *) GCC_USB30_BCR, |
| 413 | .parent = &usb30_master_clk_src.c, |
| 414 | |
| 415 | .c = { |
| 416 | .dbg_name = "usb30_master_clk", |
| 417 | .ops = &clk_ops_branch, |
| 418 | }, |
| 419 | }; |
| 420 | |
| 421 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 422 | F( 60000000, gpll0, 10, 0, 0), |
| 423 | F_END |
| 424 | }; |
| 425 | |
| 426 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 427 | .cmd_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CMD_RCGR, |
| 428 | .cfg_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CFG_RCGR, |
| 429 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 430 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 431 | .current_freq = &rcg_dummy_freq, |
| 432 | |
| 433 | .c = { |
| 434 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 435 | .ops = &clk_ops_rcg, |
| 436 | }, |
| 437 | }; |
| 438 | |
| 439 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 440 | .cbcr_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CBCR, |
| 441 | .has_sibling = 0, |
| 442 | .parent = &usb30_mock_utmi_clk_src.c, |
| 443 | |
| 444 | .c = { |
| 445 | .dbg_name = "usb30_mock_utmi_clk", |
| 446 | .ops = &clk_ops_branch, |
| 447 | }, |
| 448 | }; |
| 449 | |
| 450 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 451 | .cbcr_reg = (uint32_t *) GCC_USB30_SLEEP_CBCR, |
| 452 | .has_sibling = 1, |
| 453 | |
| 454 | .c = { |
| 455 | .dbg_name = "usb30_sleep_clk", |
| 456 | .ops = &clk_ops_branch, |
| 457 | }, |
| 458 | }; |
| 459 | |
| 460 | static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = { |
| 461 | F( 1200000, cxo, 16, 0, 0), |
| 462 | F_END |
| 463 | }; |
| 464 | |
| 465 | static struct rcg_clk usb30_phy_aux_clk_src = { |
| 466 | .cmd_reg = (uint32_t *) GCC_USB3_PHY_AUX_CMD_RCGR, |
| 467 | .cfg_reg = (uint32_t *) GCC_USB3_PHY_AUX_CFG_RCGR, |
| 468 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 469 | .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src, |
| 470 | .current_freq = &rcg_dummy_freq, |
| 471 | |
| 472 | .c = { |
| 473 | .dbg_name = "usb30_phy_aux_clk_src", |
| 474 | .ops = &clk_ops_rcg, |
| 475 | }, |
| 476 | }; |
| 477 | |
| 478 | static struct branch_clk gcc_usb30_phy_aux_clk = { |
| 479 | .cbcr_reg = (uint32_t *) GCC_USB3_PHY_AUX_CBCR, |
| 480 | .has_sibling = 0, |
| 481 | .parent = &usb30_phy_aux_clk_src.c, |
| 482 | |
| 483 | .c = { |
| 484 | .dbg_name = "usb30_phy_aux_clk", |
| 485 | .ops = &clk_ops_branch, |
| 486 | }, |
| 487 | }; |
| 488 | |
| 489 | static struct branch_clk gcc_usb30_pipe_clk = { |
Channagoud Kadabi | 52a6cfa | 2015-01-27 11:16:59 -0800 | [diff] [blame] | 490 | .bcr_reg = (uint32_t *) GCC_USB3PHY_PHY_BCR, |
Channagoud Kadabi | 196b27c | 2015-01-19 13:53:38 -0500 | [diff] [blame] | 491 | .cbcr_reg = (uint32_t *) GCC_USB3_PHY_PIPE_CBCR, |
| 492 | .has_sibling = 1, |
| 493 | |
| 494 | .c = { |
| 495 | .dbg_name = "usb30_pipe_clk", |
| 496 | .ops = &clk_ops_branch, |
| 497 | }, |
| 498 | }; |
| 499 | |
| 500 | static struct reset_clk gcc_usb30_phy_reset = { |
| 501 | .bcr_reg = (uint32_t ) GCC_USB3_PHY_BCR, |
| 502 | |
| 503 | .c = { |
| 504 | .dbg_name = "usb30_phy_reset", |
| 505 | .ops = &clk_ops_rst, |
| 506 | }, |
| 507 | }; |
| 508 | |
| 509 | static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { |
| 510 | .cbcr_reg = (uint32_t *) GCC_USB_HS_PHY_CFG_AHB_CBCR, |
| 511 | .has_sibling = 1, |
| 512 | |
| 513 | .c = { |
| 514 | .dbg_name = "usb_phy_cfg_ahb2phy_clk", |
| 515 | .ops = &clk_ops_branch, |
| 516 | }, |
| 517 | }; |
| 518 | |
Channagoud Kadabi | 92db112 | 2014-06-25 16:00:13 -0400 | [diff] [blame] | 519 | /* CE Clocks */ |
| 520 | static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = { |
| 521 | F( 50000000, gpll0, 12, 0, 0), |
| 522 | F(100000000, gpll0, 6, 0, 0), |
| 523 | F_END |
| 524 | }; |
| 525 | |
| 526 | static struct rcg_clk ce2_clk_src = { |
| 527 | .cmd_reg = (uint32_t *) GCC_CE2_CMD_RCGR, |
| 528 | .cfg_reg = (uint32_t *) GCC_CE2_CFG_RCGR, |
| 529 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 530 | .freq_tbl = ftbl_gcc_ce2_clk, |
| 531 | .current_freq = &rcg_dummy_freq, |
| 532 | |
| 533 | .c = { |
| 534 | .dbg_name = "ce2_clk_src", |
| 535 | .ops = &clk_ops_rcg, |
| 536 | }, |
| 537 | }; |
| 538 | |
| 539 | static struct vote_clk gcc_ce2_clk = { |
| 540 | .cbcr_reg = (uint32_t *) GCC_CE2_CBCR, |
| 541 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 542 | .en_mask = BIT(2), |
| 543 | |
| 544 | .c = { |
| 545 | .dbg_name = "gcc_ce2_clk", |
| 546 | .ops = &clk_ops_vote, |
| 547 | }, |
| 548 | }; |
| 549 | |
| 550 | static struct vote_clk gcc_ce2_ahb_clk = { |
| 551 | .cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR, |
| 552 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 553 | .en_mask = BIT(0), |
| 554 | |
| 555 | .c = { |
| 556 | .dbg_name = "gcc_ce2_ahb_clk", |
| 557 | .ops = &clk_ops_vote, |
| 558 | }, |
| 559 | }; |
| 560 | |
| 561 | static struct vote_clk gcc_ce2_axi_clk = { |
| 562 | .cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR, |
| 563 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 564 | .en_mask = BIT(1), |
| 565 | |
| 566 | .c = { |
| 567 | .dbg_name = "gcc_ce2_axi_clk", |
| 568 | .ops = &clk_ops_vote, |
| 569 | }, |
| 570 | }; |
| 571 | |
| 572 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 573 | F( 50000000, gpll0, 12, 0, 0), |
| 574 | F(100000000, gpll0, 6, 0, 0), |
| 575 | F_END |
| 576 | }; |
| 577 | |
| 578 | static struct rcg_clk ce1_clk_src = { |
| 579 | .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR, |
| 580 | .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR, |
| 581 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 582 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 583 | .current_freq = &rcg_dummy_freq, |
| 584 | |
| 585 | .c = { |
| 586 | .dbg_name = "ce1_clk_src", |
| 587 | .ops = &clk_ops_rcg, |
| 588 | }, |
| 589 | }; |
| 590 | |
| 591 | static struct vote_clk gcc_ce1_clk = { |
| 592 | .cbcr_reg = (uint32_t *) GCC_CE1_CBCR, |
| 593 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 594 | .en_mask = BIT(5), |
| 595 | |
| 596 | .c = { |
| 597 | .dbg_name = "gcc_ce1_clk", |
| 598 | .ops = &clk_ops_vote, |
| 599 | }, |
| 600 | }; |
| 601 | |
| 602 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 603 | .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR, |
| 604 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 605 | .en_mask = BIT(3), |
| 606 | |
| 607 | .c = { |
| 608 | .dbg_name = "gcc_ce1_ahb_clk", |
| 609 | .ops = &clk_ops_vote, |
| 610 | }, |
| 611 | }; |
| 612 | |
| 613 | static struct vote_clk gcc_ce1_axi_clk = { |
| 614 | .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR, |
| 615 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 616 | .en_mask = BIT(4), |
| 617 | |
| 618 | .c = { |
| 619 | .dbg_name = "gcc_ce1_axi_clk", |
| 620 | .ops = &clk_ops_vote, |
| 621 | }, |
| 622 | }; |
| 623 | |
| 624 | |
| 625 | /* Clock lookup table */ |
| 626 | static struct clk_lookup msm_clocks_fsm9010[] = |
| 627 | { |
| 628 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 629 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 630 | |
| 631 | CLK_LOOKUP("uart0_iface_clk", gcc_blsp1_ahb_clk.c), |
| 632 | CLK_LOOKUP("uart0_core_clk", gcc_blsp1_uart0_apps_clk.c), |
| 633 | CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c), |
| 634 | CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c), |
| 635 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 636 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 637 | CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c), |
| 638 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
| 639 | |
| 640 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 641 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 642 | |
Channagoud Kadabi | 196b27c | 2015-01-19 13:53:38 -0500 | [diff] [blame] | 643 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c), |
| 644 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 645 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 646 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 647 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
| 648 | CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c), |
| 649 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 650 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 651 | |
| 652 | CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c), |
| 653 | |
Channagoud Kadabi | 92db112 | 2014-06-25 16:00:13 -0400 | [diff] [blame] | 654 | CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c), |
| 655 | CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c), |
| 656 | CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c), |
| 657 | CLK_LOOKUP("ce2_src_clk", ce2_clk_src.c), |
| 658 | |
| 659 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 660 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 661 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 662 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 663 | }; |
| 664 | |
| 665 | |
| 666 | void platform_clock_init(void) |
| 667 | { |
| 668 | clk_init(msm_clocks_fsm9010, ARRAY_SIZE(msm_clocks_fsm9010)); |
| 669 | } |