Channagoud Kadabi | d317801 | 2015-02-03 13:22:59 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | afb8e17 | 2013-05-23 13:55:47 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef __SDHCI_MSM_H__ |
| 30 | #define __SDHCI_MSM_H__ |
| 31 | |
| 32 | #include <kernel/event.h> |
vijay kumar | 4f4405f | 2014-08-08 11:49:53 +0530 | [diff] [blame] | 33 | #include <mmc_sdhci.h> |
Channagoud Kadabi | afb8e17 | 2013-05-23 13:55:47 -0700 | [diff] [blame] | 34 | |
Channagoud Kadabi | 946848d | 2013-10-02 12:09:37 -0700 | [diff] [blame] | 35 | #define SDHCI_HC_START_BIT 0x0 |
| 36 | #define SDHCI_HC_WIDTH 0x1 |
| 37 | |
Channagoud Kadabi | d10f618 | 2013-12-30 11:51:53 -0800 | [diff] [blame] | 38 | #define SDCC_MCI_POWER 0x0 |
| 39 | #define CORE_SW_RST_START 0x7 |
| 40 | #define CORE_SW_RST_WIDTH 0x1 |
| 41 | |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 42 | /* DLL & CDC registers |
| 43 | * DLL: Delay Line |
| 44 | * CDC: Calibrated Delay Circuit |
| 45 | */ |
| 46 | #define SDCC_DLL_CONFIG_REG 0x100 |
| 47 | #define SDCC_VENDOR_SPECIFIC_FUNC 0x10C |
| 48 | #define SDCC_REG_DLL_STATUS 0x108 |
| 49 | #define SDCC_CDC_DDR200_CFG 0x184 |
| 50 | #define SDCC_VENDOR_SPEC_CSR_CDC_CFG 0x178 |
| 51 | #define SDCC_CSR_CDC_CTRL_CFG0 0x130 |
| 52 | #define SDCC_CSR_CDC_CTRL_CFG1 0x134 |
| 53 | #define SDCC_CSR_CDC_CAL_TIMER_CFG0 0x138 |
| 54 | #define SDCC_CSR_CDC_CAL_TIMER_CFG1 0x13C |
| 55 | #define SDCC_CSR_CDC_REFCOUNT_CFG 0x140 |
| 56 | #define SDCC_CSR_CDC_COARSE_CAL_CFG 0x144 |
| 57 | #define SDCC_CSR_CDC_DELAY_CFG 0x150 |
| 58 | #define SDCC_CDC_OFFSET_CFG 0x14C |
| 59 | #define SDCC_CDC_SLAVE_DDA_CFG 0x160 |
| 60 | #define SDCC_CSR_CDC_STATUS0 0x164 |
| 61 | |
Channagoud Kadabi | 756e1e3 | 2014-06-05 13:00:55 -0700 | [diff] [blame] | 62 | /* Macros for CM_DLL_SDC4 related macros */ |
| 63 | #define SDCC_HC_VENDOR_SPECIFIC_FUNC3 0x1B0 |
| 64 | #define SDCC_HC_REG_DLL_CONFIG_2 0x1B4 |
| 65 | #define SDCC_HC_REG_DDR_CONFIG 0x1B8 |
| 66 | |
| 67 | #define DDR_CAL_EN BIT(0) |
| 68 | #define DDR_CAL_TIMEOUT_MAX 50 |
| 69 | #define DDR_DLL_LOCK_JDR BIT(11) |
| 70 | #define PWRSAVE_DLL BIT(3) |
| 71 | #define DDR_CONFIG_VAL 0x80040853 |
| 72 | |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 73 | /* DLL & CDC helper macros */ |
| 74 | #define SDCC_DLL_PWR_SAVE_EN BIT(1) |
| 75 | #define SDCC_DLL_LOCK_STAT BIT(7) |
| 76 | #define SDCC_DLL_EN BIT(16) |
| 77 | #define SDCC_DLL_CDR_EN BIT(17) |
| 78 | #define SDCC_DLL_CLK_OUT_EN BIT(18) |
Channagoud Kadabi | d317801 | 2015-02-03 13:22:59 -0800 | [diff] [blame] | 79 | #define SDCC_FLL_CYCLE_CNT BIT(18) |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 80 | #define SDCC_DLL_CDR_EXT_EN BIT(19) |
Channagoud Kadabi | d317801 | 2015-02-03 13:22:59 -0800 | [diff] [blame] | 81 | #define SDCC_DLL_CLOCK_DISABLE BIT(21) |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 82 | #define SDCC_DLL_PDN_EN BIT(29) |
| 83 | #define SDCC_DLL_RESET_EN BIT(30) |
| 84 | #define SDCC_DLL_CONFIG_MCLK_START 0x18 |
| 85 | #define SDCC_DLL_CONFIG_MCLK_WIDTH 0x3 |
| 86 | #define SDCC_DLL_GRAY_CODE_START 0x14 |
| 87 | #define SDCC_DLL_GRAY_CODE_WIDTH 0x4 |
| 88 | #define CMD_DAT_TRACK_SEL BIT(0) |
| 89 | #define CDC_T4_DLY_SEL BIT(0) |
| 90 | #define CDC_SWITCH_BYPASS_OFF BIT(0) |
| 91 | #define CDC_SWITCH_RC_EN BIT(1) |
| 92 | #define START_CDC_TRAFFIC BIT(6) |
Channagoud Kadabi | e632e25 | 2014-03-31 15:26:00 -0700 | [diff] [blame] | 93 | #define FF_CLK_SW_RST_DIS_START 0xD |
| 94 | #define FF_CLK_SW_RST_DIS_WIDTH 0x1 |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 95 | #define CDC_SW_TRIGGER_FULL_CALIB BIT(16) |
| 96 | #define CDC_HW_AUTO_CAL_EN BIT(17) |
| 97 | #define CDC_TIMER_EN BIT(16) |
| 98 | #define CSR_CDC_ERROR_MASK 0x7000000 |
| 99 | |
| 100 | /* SDCC macros for HS400 */ |
| 101 | #define SDCC_HC_MCLK_SEL_HS400 0x3 |
| 102 | #define SDCC_HC_MCLK_HS400_START 0x8 |
| 103 | #define SDCC_HC_MCLK_HS400_WIDTH 0x2 |
| 104 | #define SDCC_HC_MCLK_SEL_IN_HS400 0x6 |
| 105 | #define SDCC_HC_MCLK_SEL_IN_DFLT 0x2 |
| 106 | #define SDCC_HC_MCLK_SEL_IN_UHS 0x4 |
| 107 | #define SDCC_HC_MCLK_SEL_IN_START 0x13 |
| 108 | #define SDCC_HC_MCLK_SEL_IN_WIDTH 0x3 |
| 109 | #define SDCC_HC_MCLK_SEL_IN_EN 0x1 |
| 110 | #define SDCC_HC_MCLK_SEL_IN_EN_START 0x12 |
| 111 | #define SDCC_HC_MCLK_SEL_IN_EN_WIDTH 0x1 |
| 112 | |
| 113 | #define MAX_PHASES 16 |
| 114 | |
Channagoud Kadabi | e9168e8 | 2014-01-28 21:33:34 -0800 | [diff] [blame] | 115 | /* SDCC version macros */ |
| 116 | #define MCI_VERSION 0x50 |
| 117 | #define CORE_VERSION_MAJOR_MASK 0xF0000000 |
| 118 | #define CORE_VERSION_MAJOR_SHIFT 0x1C |
Channagoud Kadabi | 756e1e3 | 2014-06-05 13:00:55 -0700 | [diff] [blame] | 119 | #define CORE_VERSION_MINOR_MASK 0x000000FF |
Channagoud Kadabi | e9168e8 | 2014-01-28 21:33:34 -0800 | [diff] [blame] | 120 | |
Channagoud Kadabi | e632e25 | 2014-03-31 15:26:00 -0700 | [diff] [blame] | 121 | #define SDHCI_DLL_TIMEOUT 50 |
| 122 | #define CDC_STATUS_TIMEOUT 50 |
| 123 | |
Channagoud Kadabi | 17e6997 | 2014-10-13 11:42:24 -0700 | [diff] [blame] | 124 | #define HC_IO_PAD_PWR_SWITCH_EN BIT(15) |
| 125 | #define HC_IO_PAD_PWR_SWITCH BIT(16) |
| 126 | |
Channagoud Kadabi | 0e657d0 | 2014-11-06 18:08:57 -0800 | [diff] [blame] | 127 | #define SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0 0x11C |
| 128 | |
Channagoud Kadabi | d317801 | 2015-02-03 13:22:59 -0800 | [diff] [blame] | 129 | #define TCXO_FREQ 19200000 |
| 130 | |
Channagoud Kadabi | afb8e17 | 2013-05-23 13:55:47 -0700 | [diff] [blame] | 131 | struct sdhci_msm_data |
| 132 | { |
| 133 | uint32_t pwrctl_base; |
| 134 | uint32_t pwr_irq; |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 135 | uint8_t tuning_done; |
| 136 | uint8_t calibration_done; |
| 137 | uint8_t saved_phase; |
| 138 | uint8_t slot; |
Channagoud Kadabi | 17e6997 | 2014-10-13 11:42:24 -0700 | [diff] [blame] | 139 | uint8_t use_io_switch; |
Channagoud Kadabi | afb8e17 | 2013-05-23 13:55:47 -0700 | [diff] [blame] | 140 | event_t* sdhc_event; |
| 141 | }; |
| 142 | |
Channagoud Kadabi | 9b8f8fc | 2013-07-26 12:02:49 -0700 | [diff] [blame] | 143 | void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *data); |
Channagoud Kadabi | e106d1f | 2014-04-25 18:26:26 -0700 | [diff] [blame] | 144 | uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, struct mmc_card * card, uint32_t bus_width); |
Channagoud Kadabi | 24146af | 2014-01-24 17:22:08 -0800 | [diff] [blame] | 145 | void sdhci_mode_disable(struct sdhci_host *host); |
Channagoud Kadabi | dd8a734 | 2014-07-09 10:35:01 -0700 | [diff] [blame] | 146 | /* API: Toggle the bit for clock-data recovery */ |
| 147 | void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable); |
vijay kumar | 4f4405f | 2014-08-08 11:49:53 +0530 | [diff] [blame] | 148 | void sdhci_msm_set_mci_clk(struct sdhci_host *host); |
Channagoud Kadabi | afb8e17 | 2013-05-23 13:55:47 -0700 | [diff] [blame] | 149 | #endif |